tjh.dev / kernel
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mtd: fsmc_nand: pass the ale and cmd resource via resource

Do not use the platform_data to pass resource and be smart in the drivers.
Just pass it via resource

Switch to devm_request_and_ioremap at the sametime

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-By: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>

authored by

Jean-Christophe PLAGNIOL-VILLARD and committed by
Artem Bityutskiy 6d7b42a4 fc05d5a3

+49 -66
+5 -7
Documentation/devicetree/bindings/mtd/fsmc-nand.txt
··· 3 3 Required properties: 4 4 - compatible : "st,spear600-fsmc-nand" 5 5 - reg : Address range of the mtd chip 6 - - reg-names: Should contain the reg names "fsmc_regs" and "nand_data" 7 - - st,ale-off : Chip specific offset to ALE 8 - - st,cle-off : Chip specific offset to CLE 6 + - reg-names: Should contain the reg names "fsmc_regs", "nand_data", "nand_addr" and "nand_cmd" 9 7 10 8 Optional properties: 11 9 - bank-width : Width (in bytes) of the device. If not present, the width ··· 17 19 #address-cells = <1>; 18 20 #size-cells = <1>; 19 21 reg = <0xd1800000 0x1000 /* FSMC Register */ 20 - 0xd2000000 0x4000>; /* NAND Base */ 21 - reg-names = "fsmc_regs", "nand_data"; 22 - st,ale-off = <0x20000>; 23 - st,cle-off = <0x10000>; 22 + 0xd2000000 0x0010 /* NAND Base DATA */ 23 + 0xd2020000 0x0010 /* NAND Base ADDR */ 24 + 0xd2010000 0x0010>; /* NAND Base CMD */ 25 + reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd"; 24 26 25 27 bank-width = <1>; 26 28 nand-skip-bbtscan;
+5 -5
arch/arm/boot/dts/spear13xx.dtsi
··· 104 104 compatible = "st,spear600-fsmc-nand"; 105 105 #address-cells = <1>; 106 106 #size-cells = <1>; 107 - reg = <0xb0000000 0x1000 /* FSMC Register */ 108 - 0xb0800000 0x0010>; /* NAND Base */ 109 - reg-names = "fsmc_regs", "nand_data"; 107 + reg = <0xb0000000 0x1000 /* FSMC Register*/ 108 + 0xb0800000 0x0010 /* NAND Base DATA */ 109 + 0xb0820000 0x0010 /* NAND Base ADDR */ 110 + 0xb0810000 0x0010>; /* NAND Base CMD */ 111 + reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd"; 110 112 interrupts = <0 20 0x4 111 113 0 21 0x4 112 114 0 22 0x4 113 115 0 23 0x4>; 114 - st,ale-off = <0x20000>; 115 - st,cle-off = <0x10000>; 116 116 status = "disabled"; 117 117 }; 118 118
+4 -4
arch/arm/boot/dts/spear300.dtsi
··· 38 38 #address-cells = <1>; 39 39 #size-cells = <1>; 40 40 reg = <0x94000000 0x1000 /* FSMC Register */ 41 - 0x80000000 0x0010>; /* NAND Base */ 42 - reg-names = "fsmc_regs", "nand_data"; 43 - st,ale-off = <0x20000>; 44 - st,cle-off = <0x10000>; 41 + 0x80000000 0x0010 /* NAND Base DATA */ 42 + 0x80020000 0x0010 /* NAND Base ADDR */ 43 + 0x80010000 0x0010>; /* NAND Base CMD */ 44 + reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd"; 45 45 status = "disabled"; 46 46 }; 47 47
+4 -4
arch/arm/boot/dts/spear310.dtsi
··· 32 32 #address-cells = <1>; 33 33 #size-cells = <1>; 34 34 reg = <0x44000000 0x1000 /* FSMC Register */ 35 - 0x40000000 0x0010>; /* NAND Base */ 36 - reg-names = "fsmc_regs", "nand_data"; 37 - st,ale-off = <0x10000>; 38 - st,cle-off = <0x20000>; 35 + 0x40000000 0x0010 /* NAND Base DATA */ 36 + 0x40020000 0x0010 /* NAND Base ADDR */ 37 + 0x40010000 0x0010>; /* NAND Base CMD */ 38 + reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd"; 39 39 status = "disabled"; 40 40 }; 41 41
+4 -4
arch/arm/boot/dts/spear320.dtsi
··· 38 38 #address-cells = <1>; 39 39 #size-cells = <1>; 40 40 reg = <0x4c000000 0x1000 /* FSMC Register */ 41 - 0x50000000 0x0010>; /* NAND Base */ 42 - reg-names = "fsmc_regs", "nand_data"; 43 - st,ale-off = <0x20000>; 44 - st,cle-off = <0x10000>; 41 + 0x50000000 0x0010 /* NAND Base DATA */ 42 + 0x50020000 0x0010 /* NAND Base ADDR */ 43 + 0x50010000 0x0010>; /* NAND Base CMD */ 44 + reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd"; 45 45 status = "disabled"; 46 46 }; 47 47
+4 -4
arch/arm/boot/dts/spear600.dtsi
··· 67 67 #address-cells = <1>; 68 68 #size-cells = <1>; 69 69 reg = <0xd1800000 0x1000 /* FSMC Register */ 70 - 0xd2000000 0x4000>; /* NAND Base */ 71 - reg-names = "fsmc_regs", "nand_data"; 72 - st,ale-off = <0x20000>; 73 - st,cle-off = <0x10000>; 70 + 0xd2000000 0x0010 /* NAND Base DATA */ 71 + 0xd2020000 0x0010 /* NAND Base ADDR */ 72 + 0xd2010000 0x0010>; /* NAND Base CMD */ 73 + reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd"; 74 74 status = "disabled"; 75 75 }; 76 76
+12 -2
arch/arm/mach-u300/core.c
··· 252 252 */ 253 253 static struct resource fsmc_resources[] = { 254 254 { 255 + .name = "nand_addr", 256 + .start = U300_NAND_CS0_PHYS_BASE + PLAT_NAND_ALE, 257 + .end = U300_NAND_CS0_PHYS_BASE + PLAT_NAND_ALE + SZ_16K - 1, 258 + .flags = IORESOURCE_MEM, 259 + }, 260 + { 261 + .name = "nand_cmd", 262 + .start = U300_NAND_CS0_PHYS_BASE + PLAT_NAND_CLE, 263 + .end = U300_NAND_CS0_PHYS_BASE + PLAT_NAND_CLE + SZ_16K - 1, 264 + .flags = IORESOURCE_MEM, 265 + }, 266 + { 255 267 .name = "nand_data", 256 268 .start = U300_NAND_CS0_PHYS_BASE, 257 269 .end = U300_NAND_CS0_PHYS_BASE + SZ_16K - 1, ··· 1508 1496 .nr_partitions = ARRAY_SIZE(u300_partitions), 1509 1497 .options = NAND_SKIP_BBTSCAN, 1510 1498 .width = FSMC_NAND_BW8, 1511 - .ale_off = PLAT_NAND_ALE, 1512 - .cle_off = PLAT_NAND_CLE, 1513 1499 }; 1514 1500 1515 1501 static struct platform_device nand_device = {
+11 -33
drivers/mtd/nand/fsmc_nand.c
··· 876 876 return -EINVAL; 877 877 } 878 878 } 879 - of_property_read_u32(np, "st,ale-off", &pdata->ale_off); 880 - of_property_read_u32(np, "st,cle-off", &pdata->cle_off); 881 879 if (of_get_property(np, "nand-skip-bbtscan", NULL)) 882 880 pdata->options = NAND_SKIP_BBTSCAN; 883 881 ··· 933 935 if (!res) 934 936 return -EINVAL; 935 937 936 - if (!devm_request_mem_region(&pdev->dev, res->start, resource_size(res), 937 - pdev->name)) { 938 - dev_err(&pdev->dev, "Failed to get memory data resourse\n"); 939 - return -ENOENT; 940 - } 941 - 942 - host->data_pa = (dma_addr_t)res->start; 943 - host->data_va = devm_ioremap(&pdev->dev, res->start, 944 - resource_size(res)); 938 + host->data_va = devm_request_and_ioremap(&pdev->dev, res); 945 939 if (!host->data_va) { 946 940 dev_err(&pdev->dev, "data ioremap failed\n"); 947 941 return -ENOMEM; 948 942 } 943 + host->data_pa = (dma_addr_t)res->start; 949 944 950 - if (!devm_request_mem_region(&pdev->dev, res->start + pdata->ale_off, 951 - resource_size(res), pdev->name)) { 952 - dev_err(&pdev->dev, "Failed to get memory ale resourse\n"); 953 - return -ENOENT; 954 - } 945 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_addr"); 946 + if (!res) 947 + return -EINVAL; 955 948 956 - host->addr_va = devm_ioremap(&pdev->dev, res->start + pdata->ale_off, 957 - resource_size(res)); 949 + host->addr_va = devm_request_and_ioremap(&pdev->dev, res); 958 950 if (!host->addr_va) { 959 951 dev_err(&pdev->dev, "ale ioremap failed\n"); 960 952 return -ENOMEM; 961 953 } 962 954 963 - if (!devm_request_mem_region(&pdev->dev, res->start + pdata->cle_off, 964 - resource_size(res), pdev->name)) { 965 - dev_err(&pdev->dev, "Failed to get memory cle resourse\n"); 966 - return -ENOENT; 967 - } 955 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_cmd"); 956 + if (!res) 957 + return -EINVAL; 968 958 969 - host->cmd_va = devm_ioremap(&pdev->dev, res->start + pdata->cle_off, 970 - resource_size(res)); 959 + host->cmd_va = devm_request_and_ioremap(&pdev->dev, res); 971 960 if (!host->cmd_va) { 972 961 dev_err(&pdev->dev, "ale ioremap failed\n"); 973 962 return -ENOMEM; ··· 964 979 if (!res) 965 980 return -EINVAL; 966 981 967 - if (!devm_request_mem_region(&pdev->dev, res->start, resource_size(res), 968 - pdev->name)) { 969 - dev_err(&pdev->dev, "Failed to get memory regs resourse\n"); 970 - return -ENOENT; 971 - } 972 - 973 - host->regs_va = devm_ioremap(&pdev->dev, res->start, 974 - resource_size(res)); 982 + host->regs_va = devm_request_and_ioremap(&pdev->dev, res); 975 983 if (!host->regs_va) { 976 984 dev_err(&pdev->dev, "regs ioremap failed\n"); 977 985 return -ENOMEM;
-3
include/linux/mtd/fsmc.h
··· 155 155 unsigned int width; 156 156 unsigned int bank; 157 157 158 - /* CLE, ALE offsets */ 159 - unsigned int cle_off; 160 - unsigned int ale_off; 161 158 enum access_mode mode; 162 159 163 160 void (*select_bank)(uint32_t bank, uint32_t busw);