staging: ft1000: Fix line over 80 characters.

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

Fix checkpatch.pl issues with line over 80 characters in ft1000.h

Signed-off-by: Gulsah Kose <gulsah.1004@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

authored by

Gulsah Kose and committed by

Greg Kroah-Hartman 12 years ago 6d56be08 8e3a3ce6

+117 -39

1 changed file

expand all

drivers

staging

ft1000

ft1000.h

+117 -39

drivers/staging/ft1000/ft1000.h

··· 21 21 #define FT1000_REG_SUP_CTRL 0x0020 /* HCTR - Host Control Register */ 22 22 #define FT1000_REG_SUP_STAT 0x0022 /* HSTAT - Host Status Register */ 23 23 #define FT1000_REG_RESET 0x0024 /* HCTR - Host Control Register */ 24 - #define FT1000_REG_SUP_ISR 0x0026 /* HISR - Host Interrupt Status Register */ 24 + #define FT1000_REG_SUP_ISR 0x0026 /* HISR - Host Interrupt Status 25 + * Register 26 + */ 25 27 #define FT1000_REG_SUP_IMASK 0x0028 /* HIMASK - Host Interrupt Mask */ 26 28 #define FT1000_REG_DOORBELL 0x002a /* DBELL - Door Bell Register */ 27 - #define FT1000_REG_ASIC_ID 0x002e /* ASICID - ASIC Identification Number */ 29 + #define FT1000_REG_ASIC_ID 0x002e /* ASICID - ASIC Identification 30 + * Number 31 + */ 28 32 29 33 /* MEMORY MAP FOR ELECTRABUZZ ASIC */ 30 34 #define FT1000_REG_UFIFO_STAT 0x0000 /* UFSR - Uplink FIFO status register */ 31 - #define FT1000_REG_UFIFO_BEG 0x0002 /* UFBR - Uplink FIFO beginning register */ 35 + #define FT1000_REG_UFIFO_BEG 0x0002 /* UFBR - Uplink FIFO beginning 36 + * register 37 + */ 32 38 #define FT1000_REG_UFIFO_MID 0x0004 /* UFMR - Uplink FIFO middle register */ 33 39 #define FT1000_REG_UFIFO_END 0x0006 /* UFER - Uplink FIFO end register */ 34 - #define FT1000_REG_DFIFO_STAT 0x0008 /* DFSR - Downlink FIFO status register */ 40 + #define FT1000_REG_DFIFO_STAT 0x0008 /* DFSR - Downlink FIFO status 41 + * register 42 + */ 35 43 #define FT1000_REG_DFIFO 0x000A /* DFR - Downlink FIFO Register */ 36 - #define FT1000_REG_DPRAM_DATA 0x000C /* DPRAM - Dual Port Indirect Data Register */ 44 + #define FT1000_REG_DPRAM_DATA 0x000C /* DPRAM - Dual Port Indirect 45 + * Data Register 46 + */ 37 47 #define FT1000_REG_WATERMARK 0x0010 /* WMARK - Watermark Register */ 38 48 39 49 /* MEMORY MAP FOR MAGNEMITE */ 40 - #define FT1000_REG_MAG_UFDR 0x0000 /* UFDR - Uplink FIFO Data Register (32-bits) */ 41 - #define FT1000_REG_MAG_UFDRL 0x0000 /* UFDRL - Uplink FIFO Data Register low-word (16-bits) */ 42 - #define FT1000_REG_MAG_UFDRH 0x0002 /* UFDRH - Uplink FIFO Data Register high-word (16-bits) */ 50 + #define FT1000_REG_MAG_UFDR 0x0000 /* UFDR - Uplink FIFO Data 51 + * Register (32-bits) 52 + */ 53 + #define FT1000_REG_MAG_UFDRL 0x0000 /* UFDRL - Uplink FIFO Data 54 + * Register low-word (16-bits) 55 + */ 56 + #define FT1000_REG_MAG_UFDRH 0x0002 /* UFDRH - Uplink FIFO Data Register 57 + * high-word (16-bits) 58 + */ 43 59 #define FT1000_REG_MAG_UFER 0x0004 /* UFER - Uplink FIFO End Register */ 44 60 #define FT1000_REG_MAG_UFSR 0x0006 /* UFSR - Uplink FIFO Status Register */ 45 - #define FT1000_REG_MAG_DFR 0x0008 /* DFR - Downlink FIFO Register (32-bits) */ 46 - #define FT1000_REG_MAG_DFRL 0x0008 /* DFRL - Downlink FIFO Register low-word (16-bits) */ 47 - #define FT1000_REG_MAG_DFRH 0x000a /* DFRH - Downlink FIFO Register high-word (16-bits) */ 48 - #define FT1000_REG_MAG_DFSR 0x000c /* DFSR - Downlink FIFO Status Register */ 49 - #define FT1000_REG_MAG_DPDATA 0x0010 /* DPDATA - Dual Port RAM Indirect Data Register (32-bits) */ 50 - #define FT1000_REG_MAG_DPDATAL 0x0010 /* DPDATAL - Dual Port RAM Indirect Data Register low-word (16-bits) */ 51 - #define FT1000_REG_MAG_DPDATAH 0x0012 /* DPDATAH - Dual Port RAM Indirect Data Register high-word (16-bits) */ 61 + #define FT1000_REG_MAG_DFR 0x0008 /* DFR - Downlink FIFO Register 62 + * (32-bits) 63 + */ 64 + #define FT1000_REG_MAG_DFRL 0x0008 /* DFRL - Downlink FIFO Register 65 + * low-word (16-bits) 66 + */ 67 + #define FT1000_REG_MAG_DFRH 0x000a /* DFRH - Downlink FIFO Register 68 + * high-word (16-bits) 69 + */ 70 + #define FT1000_REG_MAG_DFSR 0x000c /* DFSR - Downlink FIFO Status 71 + * Register 72 + */ 73 + #define FT1000_REG_MAG_DPDATA 0x0010 /* DPDATA - Dual Port RAM Indirect 74 + * Data Register (32-bits) 75 + */ 76 + #define FT1000_REG_MAG_DPDATAL 0x0010 /* DPDATAL - Dual Port RAM Indirect 77 + * Data Register low-word (16-bits) 78 + */ 79 + #define FT1000_REG_MAG_DPDATAH 0x0012 /* DPDATAH - Dual Port RAM Indirect Data 80 + * Register high-word (16-bits) 81 + */ 52 82 #define FT1000_REG_MAG_WATERMARK 0x002c /* WMARK - Watermark Register */ 53 83 #define FT1000_REG_MAG_VERSION 0x0030 /* LLC Version */ 54 84 ··· 87 57 #define FT1000_DPRAM_RX_BASE 0x0800 /* PC Card to Host Messaging Area */ 88 58 #define FT1000_FIFO_LEN 0x07FC /* total length for DSP FIFO tracking */ 89 59 #define FT1000_HI_HO 0x07FE /* heartbeat with HI/HO */ 90 - #define FT1000_DSP_STATUS 0x0FFE /* dsp status - non-zero is a request to reset dsp */ 60 + #define FT1000_DSP_STATUS 0x0FFE /* dsp status - non-zero is a request 61 + * to reset dsp 62 + */ 91 63 #define FT1000_DSP_LED 0x0FFA /* dsp led status for PAD device */ 92 64 #define FT1000_DSP_CON_STATE 0x0FF8 /* DSP Connection Status Info */ 93 65 #define FT1000_DPRAM_FEFE 0x0002 /* location for dsp ready indicator */ ··· 99 67 #define FT1000_DSP_TIMER3 0x1FF6 /* Timer Field from Basestation */ 100 68 101 69 /* Reserved Dual Port RAM offsets for Magnemite */ 102 - #define FT1000_DPRAM_MAG_TX_BASE 0x0000 /* Host to PC Card Messaging Area */ 103 - #define FT1000_DPRAM_MAG_RX_BASE 0x0200 /* PC Card to Host Messaging Area */ 70 + #define FT1000_DPRAM_MAG_TX_BASE 0x0000 /* Host to PC Card 71 + * Messaging Area 72 + */ 73 + #define FT1000_DPRAM_MAG_RX_BASE 0x0200 /* PC Card to Host 74 + * Messaging Area 75 + */ 104 76 105 - #define FT1000_MAG_FIFO_LEN 0x1FF /* total length for DSP FIFO tracking */ 77 + #define FT1000_MAG_FIFO_LEN 0x1FF /* total length for DSP 78 + * FIFO tracking 79 + */ 106 80 #define FT1000_MAG_FIFO_LEN_INDX 0x1 /* low-word index */ 107 81 #define FT1000_MAG_HI_HO 0x1FF /* heartbeat with HI/HO */ 108 82 #define FT1000_MAG_HI_HO_INDX 0x0 /* high-word index */ 109 - #define FT1000_MAG_DSP_LED 0x3FE /* dsp led status for PAD device */ 110 - #define FT1000_MAG_DSP_LED_INDX 0x0 /* dsp led status for PAD device */ 83 + #define FT1000_MAG_DSP_LED 0x3FE /* dsp led status for 84 + * PAD device 85 + */ 86 + #define FT1000_MAG_DSP_LED_INDX 0x0 /* dsp led status for 87 + * PAD device 88 + */ 111 89 #define FT1000_MAG_DSP_CON_STATE 0x3FE /* DSP Connection Status Info */ 112 90 #define FT1000_MAG_DSP_CON_STATE_INDX 0x1 /* DSP Connection Status Info */ 113 - #define FT1000_MAG_DPRAM_FEFE 0x000 /* location for dsp ready indicator */ 114 - #define FT1000_MAG_DPRAM_FEFE_INDX 0x0 /* location for dsp ready indicator */ 115 - #define FT1000_MAG_DSP_TIMER0 0x3FC /* Timer Field from Basestation */ 91 + #define FT1000_MAG_DPRAM_FEFE 0x000 /* location for dsp ready 92 + * indicator 93 + */ 94 + #define FT1000_MAG_DPRAM_FEFE_INDX 0x0 /* location for dsp ready 95 + * indicator 96 + */ 97 + #define FT1000_MAG_DSP_TIMER0 0x3FC /* Timer Field from 98 + * Basestation 99 + */ 116 100 #define FT1000_MAG_DSP_TIMER0_INDX 0x1 117 - #define FT1000_MAG_DSP_TIMER1 0x3FC /* Timer Field from Basestation */ 101 + #define FT1000_MAG_DSP_TIMER1 0x3FC /* Timer Field from 102 + * Basestation 103 + */ 118 104 #define FT1000_MAG_DSP_TIMER1_INDX 0x0 119 - #define FT1000_MAG_DSP_TIMER2 0x3FD /* Timer Field from Basestation */ 105 + #define FT1000_MAG_DSP_TIMER2 0x3FD /* Timer Field from 106 + * Basestation 107 + */ 120 108 #define FT1000_MAG_DSP_TIMER2_INDX 0x1 121 - #define FT1000_MAG_DSP_TIMER3 0x3FD /* Timer Field from Basestation */ 109 + #define FT1000_MAG_DSP_TIMER3 0x3FD /* Timer Field from 110 + * Basestation 111 + */ 122 112 #define FT1000_MAG_DSP_TIMER3_INDX 0x0 123 113 #define FT1000_MAG_TOTAL_LEN 0x200 124 114 #define FT1000_MAG_TOTAL_LEN_INDX 0x1 ··· 153 99 #define HOST_INTF_BE 0x1 /* Host interface big endian mode */ 154 100 155 101 /* FT1000 to Host Doorbell assignments */ 156 - #define FT1000_DB_DPRAM_RX 0x0001 /* this value indicates that DSP has data for host in DPRAM */ 102 + #define FT1000_DB_DPRAM_RX 0x0001 /* this value indicates that DSP 103 + * has data for host in DPRAM 104 + */ 157 105 #define FT1000_DB_DNLD_RX 0x0002 /* Downloader handshake doorbell */ 158 - #define FT1000_ASIC_RESET_REQ 0x0004 /* DSP requesting host to reset the ASIC */ 159 - #define FT1000_DSP_ASIC_RESET 0x0008 /* DSP indicating host that it will reset the ASIC */ 106 + #define FT1000_ASIC_RESET_REQ 0x0004 /* DSP requesting host to 107 + * reset the ASIC 108 + */ 109 + #define FT1000_DSP_ASIC_RESET 0x0008 /* DSP indicating host that 110 + * it will reset the ASIC 111 + */ 160 112 #define FT1000_DB_COND_RESET 0x0010 /* DSP request for a card reset. */ 161 113 162 114 /* Host to FT1000 Doorbell assignments */ 163 - #define FT1000_DB_DPRAM_TX 0x0100 /* this value indicates that host has data for DSP in DPRAM. */ 115 + #define FT1000_DB_DPRAM_TX 0x0100 /* this value indicates that host 116 + * has data for DSP in DPRAM. 117 + */ 164 118 #define FT1000_DB_DNLD_TX 0x0200 /* Downloader handshake doorbell */ 165 119 #define FT1000_ASIC_RESET_DSP 0x0400 /* Responds to FT1000_ASIC_RESET_REQ */ 166 - #define FT1000_DB_HB 0x1000 /* Indicates that supervisor has a heartbeat message for DSP. */ 120 + #define FT1000_DB_HB 0x1000 /* Indicates that supervisor has a 121 + * heartbeat message for DSP. 122 + */ 167 123 168 124 #define hi 0x6869 /* PC Card heartbeat values */ 169 125 #define ho 0x686f /* PC Card heartbeat values */ 170 126 171 127 /* Magnemite specific defines */ 172 - #define hi_mag 0x6968 /* Byte swap hi to avoid additional system call */ 173 - #define ho_mag 0x6f68 /* Byte swap ho to avoid additional system call */ 128 + #define hi_mag 0x6968 /* Byte swap hi to avoid 129 + * additional system call 130 + */ 131 + #define ho_mag 0x6f68 /* Byte swap ho to avoid 132 + * additional system call 133 + */ 174 134 175 135 /* Bit field definitions for Host Interrupt Status Register */ 176 136 /* Indicate the cause of an interrupt. */ ··· 201 133 #define ISR_MASK_RCV 0x0004 /* Downlink Packet available mask */ 202 134 #define ISR_MASK_WATERMARK 0x0008 /* Watermark interrupt mask */ 203 135 #define ISR_MASK_ALL 0xffff /* Mask all interrupts */ 204 - /* Default interrupt mask (Enable Doorbell pending and Packet available interrupts) */ 136 + /* Default interrupt mask 137 + * (Enable Doorbell pending and Packet available interrupts) 138 + */ 205 139 #define ISR_DEFAULT_MASK 0x7ff9 206 140 207 141 /* Bit field definition for Host Control Register */ 208 - #define DSP_RESET_BIT 0x0001 /* Bit field to control dsp reset state */ 142 + #define DSP_RESET_BIT 0x0001 /* Bit field to control 143 + * dsp reset state 144 + */ 209 145 /* (0 = out of reset 1 = reset) */ 210 - #define ASIC_RESET_BIT 0x0002 /* Bit field to control ASIC reset state */ 146 + #define ASIC_RESET_BIT 0x0002 /* Bit field to control 147 + * ASIC reset state 148 + */ 211 149 /* (0 = out of reset 1 = reset) */ 212 150 #define DSP_UNENCRYPTED 0x0004 213 151 #define DSP_ENCRYPTED 0x0008 ··· 269 195 unsigned char source; /* hardware source id */ 270 196 /* Host = 0x10 */ 271 197 /* Dsp = 0x20 */ 272 - unsigned char destination; /* hardware destination id (refer to source) */ 198 + unsigned char destination; /* hardware destination id 199 + * (refer to source) 200 + */ 273 201 unsigned char portdest; /* software destination port id */ 274 202 /* Host = 0x00 */ 275 203 /* Applicaton Broadcast = 0x10 */ ··· 280 204 /* Dsp Airlink = 0x90 */ 281 205 /* Dsp Loader = 0xa0 */ 282 206 /* Dsp MIP = 0xb0 */ 283 - unsigned char portsrc; /* software source port id (refer to portdest) */ 207 + unsigned char portsrc; /* software source port id 208 + * (refer to portdest) 209 + */ 284 210 unsigned short sh_str_id; /* not used */ 285 211 unsigned char control; /* not used */ 286 212 unsigned char rsvd1;