tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

drm/amdgpu: add OSS 3.0 register headers

These are register headers for the OSS (OS Services)
block on the GPU.

Acked-by: Christian König <christian.koenig@amd.com>
Acked-by: Jammy Zhou <Jammy.Zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

Alex Deucher 6d5506b6 3f2ec6f5

+5845
+688
drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_d.h
··· 1 + /* 2 + * OSS_3_0 Register documentation 3 + * 4 + * Copyright (C) 2014 Advanced Micro Devices, Inc. 5 + * 6 + * Permission is hereby granted, free of charge, to any person obtaining a 7 + * copy of this software and associated documentation files (the "Software"), 8 + * to deal in the Software without restriction, including without limitation 9 + * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 + * and/or sell copies of the Software, and to permit persons to whom the 11 + * Software is furnished to do so, subject to the following conditions: 12 + * 13 + * The above copyright notice and this permission notice shall be included 14 + * in all copies or substantial portions of the Software. 15 + * 16 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 20 + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21 + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22 + */ 23 + 24 + #ifndef OSS_3_0_D_H 25 + #define OSS_3_0_D_H 26 + 27 + #define mmIH_VMID_0_LUT 0xe00 28 + #define mmIH_VMID_1_LUT 0xe01 29 + #define mmIH_VMID_2_LUT 0xe02 30 + #define mmIH_VMID_3_LUT 0xe03 31 + #define mmIH_VMID_4_LUT 0xe04 32 + #define mmIH_VMID_5_LUT 0xe05 33 + #define mmIH_VMID_6_LUT 0xe06 34 + #define mmIH_VMID_7_LUT 0xe07 35 + #define mmIH_VMID_8_LUT 0xe08 36 + #define mmIH_VMID_9_LUT 0xe09 37 + #define mmIH_VMID_10_LUT 0xe0a 38 + #define mmIH_VMID_11_LUT 0xe0b 39 + #define mmIH_VMID_12_LUT 0xe0c 40 + #define mmIH_VMID_13_LUT 0xe0d 41 + #define mmIH_VMID_14_LUT 0xe0e 42 + #define mmIH_VMID_15_LUT 0xe0f 43 + #define mmIH_RB_CNTL 0xe30 44 + #define mmIH_RB_BASE 0xe31 45 + #define mmIH_RB_RPTR 0xe32 46 + #define mmIH_RB_WPTR 0xe33 47 + #define mmIH_RB_WPTR_ADDR_HI 0xe34 48 + #define mmIH_RB_WPTR_ADDR_LO 0xe35 49 + #define mmIH_CNTL 0xe36 50 + #define mmIH_LEVEL_STATUS 0xe37 51 + #define mmIH_STATUS 0xe38 52 + #define mmIH_PERFMON_CNTL 0xe39 53 + #define mmIH_PERFCOUNTER0_RESULT 0xe3a 54 + #define mmIH_PERFCOUNTER1_RESULT 0xe3b 55 + #define mmIH_DEBUG 0xe3c 56 + #define mmIH_DSM_MATCH_VALUE_BIT_31_0 0xe3d 57 + #define mmIH_DSM_MATCH_VALUE_BIT_63_32 0xe3e 58 + #define mmIH_DSM_MATCH_VALUE_BIT_95_64 0xe3f 59 + #define mmIH_DSM_MATCH_FIELD_CONTROL 0xe40 60 + #define mmIH_DSM_MATCH_DATA_CONTROL 0xe41 61 + #define mmIH_DOORBELL_RPTR 0xe42 62 + #define mmIH_ACTIVE_FCN_ID 0xe43 63 + #define mmIH_VF_RB_STATUS 0xe44 64 + #define mmIH_VF_ENABLE 0xe45 65 + #define mmIH_VIRT_RESET_REQ 0xe46 66 + #define mmIH_VF_RB_BIF_STATUS 0xe47 67 + #define mmIH_VERSION 0xe48 68 + #define mmIH_LEVEL_INTR_MASK 0xe49 69 + #define mmIH_RESET_INCOMPLETE_INT_CNTL 0xe4a 70 + #define mmIH_CLIENT_MAY_SEND_INCOMPLETE_INT 0xe4b 71 + #define mmSEM_MCIF_CONFIG 0xf90 72 + #define mmSDMA_CONFIG 0xf91 73 + #define mmSDMA1_CONFIG 0xf92 74 + #define mmUVD_CONFIG 0xf93 75 + #define mmVCE_CONFIG 0xf94 76 + #define mmSEM_VF_ENABLE 0xf95 77 + #define mmCP_CONFIG 0xf96 78 + #define mmSEM_ACTIVE_FCN_ID 0xf97 79 + #define mmSEM_VIRT_RESET_REQ 0xf98 80 + #define mmSEM_STATUS 0xf99 81 + #define mmSEM_EDC_CONFIG 0xf9a 82 + #define mmSEM_MAILBOX_CLIENTCONFIG 0xf9b 83 + #define mmSEM_MAILBOX 0xf9c 84 + #define mmSEM_MAILBOX_CONTROL 0xf9d 85 + #define mmSEM_CHICKEN_BITS 0xf9e 86 + #define mmSEM_MAILBOX_CLIENTCONFIG_EXTRA 0xf9f 87 + #define mmSRBM_CNTL 0x390 88 + #define mmSRBM_GFX_CNTL 0x391 89 + #define mmSRBM_READ_CNTL 0x392 90 + #define mmSRBM_STATUS2 0x393 91 + #define mmSRBM_STATUS 0x394 92 + #define mmSRBM_STATUS3 0x395 93 + #define mmSRBM_SOFT_RESET 0x398 94 + #define mmSRBM_DEBUG_CNTL 0x399 95 + #define mmSRBM_DEBUG_DATA 0x39a 96 + #define mmSRBM_CHIP_REVISION 0x39b 97 + #define mmSRBM_CREDIT_RECOVER_CNTL 0x39c 98 + #define mmSRBM_CREDIT_RECOVER 0x39d 99 + #define mmSRBM_CREDIT_RESET 0x39e 100 + #define mmCC_SYS_RB_REDUNDANCY 0x39f 101 + #define mmCC_SYS_RB_BACKEND_DISABLE 0x3a0 102 + #define mmGC_USER_SYS_RB_BACKEND_DISABLE 0x3a1 103 + #define mmSRBM_MC_CLKEN_CNTL 0x3b3 104 + #define mmSRBM_SYS_CLKEN_CNTL 0x3b4 105 + #define mmSRBM_VCE_CLKEN_CNTL 0x3b5 106 + #define mmSRBM_UVD_CLKEN_CNTL 0x3b6 107 + #define mmSRBM_SDMA_CLKEN_CNTL 0x3b7 108 + #define mmSRBM_SAM_CLKEN_CNTL 0x3b8 109 + #define mmSRBM_ISP_CLKEN_CNTL 0x3b9 110 + #define mmSRBM_VP8_CLKEN_CNTL 0x3ba 111 + #define mmSRBM_DEBUG 0x3a4 112 + #define mmSRBM_DEBUG_SNAPSHOT 0x3a5 113 + #define mmSRBM_DEBUG_SNAPSHOT2 0x3ad 114 + #define mmSRBM_READ_ERROR 0x3a6 115 + #define mmSRBM_READ_ERROR2 0x3ae 116 + #define mmSRBM_INT_CNTL 0x3a8 117 + #define mmSRBM_INT_STATUS 0x3a9 118 + #define mmSRBM_INT_ACK 0x3aa 119 + #define mmSRBM_FIREWALL_ERROR_SRC 0x3ab 120 + #define mmSRBM_FIREWALL_ERROR_ADDR 0x3ac 121 + #define mmSRBM_DSM_TRIG_CNTL0 0x3af 122 + #define mmSRBM_DSM_TRIG_CNTL1 0x3b0 123 + #define mmSRBM_DSM_TRIG_MASK0 0x3b1 124 + #define mmSRBM_DSM_TRIG_MASK1 0x3b2 125 + #define mmSRBM_PERFMON_CNTL 0x7c00 126 + #define mmSRBM_PERFCOUNTER0_SELECT 0x7c01 127 + #define mmSRBM_PERFCOUNTER1_SELECT 0x7c02 128 + #define mmSRBM_PERFCOUNTER0_LO 0x7c03 129 + #define mmSRBM_PERFCOUNTER0_HI 0x7c04 130 + #define mmSRBM_PERFCOUNTER1_LO 0x7c05 131 + #define mmSRBM_PERFCOUNTER1_HI 0x7c06 132 + #define mmSRBM_CAM_INDEX 0xfe34 133 + #define mmSRBM_CAM_DATA 0xfe35 134 + #define mmSRBM_MC_DOMAIN_ADDR0 0xfa00 135 + #define mmSRBM_MC_DOMAIN_ADDR1 0xfa01 136 + #define mmSRBM_MC_DOMAIN_ADDR2 0xfa02 137 + #define mmSRBM_MC_DOMAIN_ADDR3 0xfa03 138 + #define mmSRBM_MC_DOMAIN_ADDR4 0xfa04 139 + #define mmSRBM_MC_DOMAIN_ADDR5 0xfa05 140 + #define mmSRBM_MC_DOMAIN_ADDR6 0xfa06 141 + #define mmSRBM_SYS_DOMAIN_ADDR0 0xfa08 142 + #define mmSRBM_SYS_DOMAIN_ADDR1 0xfa09 143 + #define mmSRBM_SYS_DOMAIN_ADDR2 0xfa0a 144 + #define mmSRBM_SYS_DOMAIN_ADDR3 0xfa0b 145 + #define mmSRBM_SYS_DOMAIN_ADDR4 0xfa0c 146 + #define mmSRBM_SYS_DOMAIN_ADDR5 0xfa0d 147 + #define mmSRBM_SYS_DOMAIN_ADDR6 0xfa0e 148 + #define mmSRBM_SDMA_DOMAIN_ADDR0 0xfa10 149 + #define mmSRBM_SDMA_DOMAIN_ADDR1 0xfa11 150 + #define mmSRBM_SDMA_DOMAIN_ADDR2 0xfa12 151 + #define mmSRBM_SDMA_DOMAIN_ADDR3 0xfa13 152 + #define mmSRBM_UVD_DOMAIN_ADDR0 0xfa14 153 + #define mmSRBM_UVD_DOMAIN_ADDR1 0xfa15 154 + #define mmSRBM_UVD_DOMAIN_ADDR2 0xfa16 155 + #define mmSRBM_VCE_DOMAIN_ADDR0 0xfa18 156 + #define mmSRBM_VCE_DOMAIN_ADDR1 0xfa19 157 + #define mmSRBM_VCE_DOMAIN_ADDR2 0xfa1a 158 + #define mmSRBM_SAM_DOMAIN_ADDR0 0xfa1c 159 + #define mmSRBM_SAM_DOMAIN_ADDR1 0xfa1d 160 + #define mmSRBM_SAM_DOMAIN_ADDR2 0xfa1e 161 + #define mmSRBM_ISP_DOMAIN_ADDR0 0xfa20 162 + #define mmSRBM_ISP_DOMAIN_ADDR1 0xfa21 163 + #define mmSRBM_ISP_DOMAIN_ADDR2 0xfa22 164 + #define mmSRBM_VP8_DOMAIN_ADDR0 0xfa24 165 + #define mmSYS_GRBM_GFX_INDEX_SELECT 0xfa2c 166 + #define mmSYS_GRBM_GFX_INDEX_DATA 0xfa2d 167 + #define mmSRBM_GFX_CNTL_SELECT 0xfa2e 168 + #define mmSRBM_GFX_CNTL_DATA 0xfa2f 169 + #define mmSRBM_VF_ENABLE 0xfa30 170 + #define mmSRBM_VIRT_CNTL 0xfa31 171 + #define mmSRBM_VIRT_RESET_REQ 0xfa32 172 + #define mmCC_DRM_ID_STRAPS 0x1559 173 + #define mmCGTT_DRM_CLK_CTRL0 0x1579 174 + #define ixDH_TEST 0x0 175 + #define ixKHFS0 0x4 176 + #define ixKHFS1 0x8 177 + #define ixKHFS2 0xc 178 + #define ixKHFS3 0x10 179 + #define ixKSESSION0 0x14 180 + #define ixKSESSION1 0x18 181 + #define ixKSESSION2 0x1c 182 + #define ixKSESSION3 0x20 183 + #define ixKSIG0 0x24 184 + #define ixKSIG1 0x28 185 + #define ixKSIG2 0x2c 186 + #define ixKSIG3 0x30 187 + #define ixEXP0 0x34 188 + #define ixEXP1 0x38 189 + #define ixEXP2 0x3c 190 + #define ixEXP3 0x40 191 + #define ixEXP4 0x44 192 + #define ixEXP5 0x48 193 + #define ixEXP6 0x4c 194 + #define ixEXP7 0x50 195 + #define ixLX0 0x54 196 + #define ixLX1 0x58 197 + #define ixLX2 0x5c 198 + #define ixLX3 0x60 199 + #define ixCLIENT2_K0 0x1b4 200 + #define ixCLIENT2_K1 0x1b8 201 + #define ixCLIENT2_K2 0x1bc 202 + #define ixCLIENT2_K3 0x1c0 203 + #define ixCLIENT2_CK0 0x1c4 204 + #define ixCLIENT2_CK1 0x1c8 205 + #define ixCLIENT2_CK2 0x1cc 206 + #define ixCLIENT2_CK3 0x1d0 207 + #define ixCLIENT2_CD0 0x1d4 208 + #define ixCLIENT2_CD1 0x1d8 209 + #define ixCLIENT2_CD2 0x1dc 210 + #define ixCLIENT2_CD3 0x1e0 211 + #define ixCLIENT2_BM 0x1e4 212 + #define ixCLIENT2_OFFSET 0x1e8 213 + #define ixCLIENT2_STATUS 0x1ec 214 + #define ixCLIENT0_K0 0x1f0 215 + #define ixCLIENT0_K1 0x1f4 216 + #define ixCLIENT0_K2 0x1f8 217 + #define ixCLIENT0_K3 0x1fc 218 + #define ixCLIENT0_CK0 0x200 219 + #define ixCLIENT0_CK1 0x204 220 + #define ixCLIENT0_CK2 0x208 221 + #define ixCLIENT0_CK3 0x20c 222 + #define ixCLIENT0_CD0 0x210 223 + #define ixCLIENT0_CD1 0x214 224 + #define ixCLIENT0_CD2 0x218 225 + #define ixCLIENT0_CD3 0x21c 226 + #define ixCLIENT0_BM 0x220 227 + #define ixCLIENT0_OFFSET 0x224 228 + #define ixCLIENT0_STATUS 0x228 229 + #define ixCLIENT1_K0 0x22c 230 + #define ixCLIENT1_K1 0x230 231 + #define ixCLIENT1_K2 0x234 232 + #define ixCLIENT1_K3 0x238 233 + #define ixCLIENT1_CK0 0x23c 234 + #define ixCLIENT1_CK1 0x240 235 + #define ixCLIENT1_CK2 0x244 236 + #define ixCLIENT1_CK3 0x248 237 + #define ixCLIENT1_CD0 0x24c 238 + #define ixCLIENT1_CD1 0x250 239 + #define ixCLIENT1_CD2 0x254 240 + #define ixCLIENT1_CD3 0x258 241 + #define ixCLIENT1_BM 0x25c 242 + #define ixCLIENT1_OFFSET 0x260 243 + #define ixCLIENT1_PORT_STATUS 0x264 244 + #define ixKEFUSE0 0x268 245 + #define ixKEFUSE1 0x26c 246 + #define ixKEFUSE2 0x270 247 + #define ixKEFUSE3 0x274 248 + #define ixHFS_SEED0 0x278 249 + #define ixHFS_SEED1 0x27c 250 + #define ixHFS_SEED2 0x280 251 + #define ixHFS_SEED3 0x284 252 + #define ixRINGOSC_MASK 0x288 253 + #define ixCLIENT0_OFFSET_HI 0x290 254 + #define ixCLIENT1_OFFSET_HI 0x294 255 + #define ixCLIENT2_OFFSET_HI 0x298 256 + #define ixSPU_PORT_STATUS 0x29c 257 + #define ixCLIENT3_OFFSET_HI 0x2a0 258 + #define ixCLIENT3_K0 0x2a4 259 + #define ixCLIENT3_K1 0x2a8 260 + #define ixCLIENT3_K2 0x2ac 261 + #define ixCLIENT3_K3 0x2b0 262 + #define ixCLIENT3_CK0 0x2b4 263 + #define ixCLIENT3_CK1 0x2b8 264 + #define ixCLIENT3_CK2 0x2bc 265 + #define ixCLIENT3_CK3 0x2c0 266 + #define ixCLIENT3_CD0 0x2c4 267 + #define ixCLIENT3_CD1 0x2c8 268 + #define ixCLIENT3_CD2 0x2cc 269 + #define ixCLIENT3_CD3 0x2d0 270 + #define ixCLIENT3_BM 0x2d4 271 + #define ixCLIENT3_OFFSET 0x2d8 272 + #define ixCLIENT3_STATUS 0x2dc 273 + #define ixCLIENT4_OFFSET_HI 0x2e0 274 + #define ixCLIENT4_K0 0x2e4 275 + #define ixCLIENT4_K1 0x2e8 276 + #define ixCLIENT4_K2 0x2ec 277 + #define ixCLIENT4_K3 0x2f0 278 + #define ixCLIENT4_CK0 0x2f4 279 + #define ixCLIENT4_CK1 0x2f8 280 + #define ixCLIENT4_CK2 0x2fc 281 + #define ixCLIENT4_CK3 0x300 282 + #define ixCLIENT4_CD0 0x304 283 + #define ixCLIENT4_CD1 0x308 284 + #define ixCLIENT4_CD2 0x30c 285 + #define ixCLIENT4_CD3 0x310 286 + #define ixCLIENT4_BM 0x314 287 + #define ixCLIENT4_OFFSET 0x318 288 + #define ixCLIENT4_STATUS 0x31c 289 + #define mmDC_TEST_DEBUG_INDEX 0x157c 290 + #define mmDC_TEST_DEBUG_DATA 0x157d 291 + #define mmSDMA0_UCODE_ADDR 0x3400 292 + #define mmSDMA0_UCODE_DATA 0x3401 293 + #define mmSDMA0_POWER_CNTL 0x3402 294 + #define mmSDMA0_CLK_CTRL 0x3403 295 + #define mmSDMA0_CNTL 0x3404 296 + #define mmSDMA0_CHICKEN_BITS 0x3405 297 + #define mmSDMA0_TILING_CONFIG 0x3406 298 + #define mmSDMA0_HASH 0x3407 299 + #define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL 0x3409 300 + #define mmSDMA0_RB_RPTR_FETCH 0x340a 301 + #define mmSDMA0_IB_OFFSET_FETCH 0x340b 302 + #define mmSDMA0_PROGRAM 0x340c 303 + #define mmSDMA0_STATUS_REG 0x340d 304 + #define mmSDMA0_STATUS1_REG 0x340e 305 + #define mmSDMA0_RD_BURST_CNTL 0x340f 306 + #define mmSDMA0_PERFMON_CNTL 0x9000 307 + #define mmSDMA0_PERFCOUNTER0_RESULT 0x9001 308 + #define mmSDMA0_PERFCOUNTER1_RESULT 0x9002 309 + #define mmSDMA0_F32_CNTL 0x3412 310 + #define mmSDMA0_FREEZE 0x3413 311 + #define mmSDMA0_PHASE0_QUANTUM 0x3414 312 + #define mmSDMA0_PHASE1_QUANTUM 0x3415 313 + #define mmSDMA_POWER_GATING 0x3416 314 + #define mmSDMA_PGFSM_CONFIG 0x3417 315 + #define mmSDMA_PGFSM_WRITE 0x3418 316 + #define mmSDMA_PGFSM_READ 0x3419 317 + #define mmSDMA0_EDC_CONFIG 0x341a 318 + #define mmSDMA0_VM_CNTL 0x3420 319 + #define mmSDMA0_VM_CTX_LO 0x3421 320 + #define mmSDMA0_VM_CTX_HI 0x3422 321 + #define mmSDMA0_STATUS2_REG 0x3423 322 + #define mmSDMA0_ACTIVE_FCN_ID 0x3424 323 + #define mmSDMA0_VM_CTX_CNTL 0x3425 324 + #define mmSDMA0_VIRT_RESET_REQ 0x3426 325 + #define mmSDMA0_VF_ENABLE 0x3427 326 + #define mmSDMA0_BA_THRESHOLD 0x341b 327 + #define mmSDMA0_ID 0x341c 328 + #define mmSDMA0_VERSION 0x341d 329 + #define mmSDMA0_ATOMIC_CNTL 0x3428 330 + #define mmSDMA0_ATOMIC_PREOP_LO 0x3429 331 + #define mmSDMA0_ATOMIC_PREOP_HI 0x342a 332 + #define mmSDMA0_POWER_CNTL_IDLE 0x342c 333 + #define mmSDMA0_PERF_REG_TYPE0 0x3477 334 + #define mmSDMA0_CONTEXT_REG_TYPE0 0x3478 335 + #define mmSDMA0_CONTEXT_REG_TYPE1 0x3479 336 + #define mmSDMA0_CONTEXT_REG_TYPE2 0x347a 337 + #define mmSDMA0_PUB_REG_TYPE0 0x347c 338 + #define mmSDMA0_PUB_REG_TYPE1 0x347d 339 + #define mmSDMA0_GFX_RB_CNTL 0x3480 340 + #define mmSDMA0_GFX_RB_BASE 0x3481 341 + #define mmSDMA0_GFX_RB_BASE_HI 0x3482 342 + #define mmSDMA0_GFX_RB_RPTR 0x3483 343 + #define mmSDMA0_GFX_RB_WPTR 0x3484 344 + #define mmSDMA0_GFX_RB_WPTR_POLL_CNTL 0x3485 345 + #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI 0x3486 346 + #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO 0x3487 347 + #define mmSDMA0_GFX_RB_RPTR_ADDR_HI 0x3488 348 + #define mmSDMA0_GFX_RB_RPTR_ADDR_LO 0x3489 349 + #define mmSDMA0_GFX_IB_CNTL 0x348a 350 + #define mmSDMA0_GFX_IB_RPTR 0x348b 351 + #define mmSDMA0_GFX_IB_OFFSET 0x348c 352 + #define mmSDMA0_GFX_IB_BASE_LO 0x348d 353 + #define mmSDMA0_GFX_IB_BASE_HI 0x348e 354 + #define mmSDMA0_GFX_IB_SIZE 0x348f 355 + #define mmSDMA0_GFX_SKIP_CNTL 0x3490 356 + #define mmSDMA0_GFX_CONTEXT_STATUS 0x3491 357 + #define mmSDMA0_GFX_DOORBELL 0x3492 358 + #define mmSDMA0_GFX_CONTEXT_CNTL 0x3493 359 + #define mmSDMA0_GFX_VIRTUAL_ADDR 0x34a7 360 + #define mmSDMA0_GFX_APE1_CNTL 0x34a8 361 + #define mmSDMA0_GFX_DOORBELL_LOG 0x34a9 362 + #define mmSDMA0_GFX_WATERMARK 0x34aa 363 + #define mmSDMA0_GFX_CSA_ADDR_LO 0x34ac 364 + #define mmSDMA0_GFX_CSA_ADDR_HI 0x34ad 365 + #define mmSDMA0_GFX_IB_SUB_REMAIN 0x34af 366 + #define mmSDMA0_GFX_PREEMPT 0x34b0 367 + #define mmSDMA0_GFX_DUMMY_REG 0x34b1 368 + #define mmSDMA0_GFX_MIDCMD_DATA0 0x34c1 369 + #define mmSDMA0_GFX_MIDCMD_DATA1 0x34c2 370 + #define mmSDMA0_GFX_MIDCMD_DATA2 0x34c3 371 + #define mmSDMA0_GFX_MIDCMD_DATA3 0x34c4 372 + #define mmSDMA0_GFX_MIDCMD_DATA4 0x34c5 373 + #define mmSDMA0_GFX_MIDCMD_DATA5 0x34c6 374 + #define mmSDMA0_GFX_MIDCMD_CNTL 0x34c7 375 + #define mmSDMA0_RLC0_RB_CNTL 0x3500 376 + #define mmSDMA0_RLC0_RB_BASE 0x3501 377 + #define mmSDMA0_RLC0_RB_BASE_HI 0x3502 378 + #define mmSDMA0_RLC0_RB_RPTR 0x3503 379 + #define mmSDMA0_RLC0_RB_WPTR 0x3504 380 + #define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL 0x3505 381 + #define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI 0x3506 382 + #define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO 0x3507 383 + #define mmSDMA0_RLC0_RB_RPTR_ADDR_HI 0x3508 384 + #define mmSDMA0_RLC0_RB_RPTR_ADDR_LO 0x3509 385 + #define mmSDMA0_RLC0_IB_CNTL 0x350a 386 + #define mmSDMA0_RLC0_IB_RPTR 0x350b 387 + #define mmSDMA0_RLC0_IB_OFFSET 0x350c 388 + #define mmSDMA0_RLC0_IB_BASE_LO 0x350d 389 + #define mmSDMA0_RLC0_IB_BASE_HI 0x350e 390 + #define mmSDMA0_RLC0_IB_SIZE 0x350f 391 + #define mmSDMA0_RLC0_SKIP_CNTL 0x3510 392 + #define mmSDMA0_RLC0_CONTEXT_STATUS 0x3511 393 + #define mmSDMA0_RLC0_DOORBELL 0x3512 394 + #define mmSDMA0_RLC0_VIRTUAL_ADDR 0x3527 395 + #define mmSDMA0_RLC0_APE1_CNTL 0x3528 396 + #define mmSDMA0_RLC0_DOORBELL_LOG 0x3529 397 + #define mmSDMA0_RLC0_WATERMARK 0x352a 398 + #define mmSDMA0_RLC0_CSA_ADDR_LO 0x352c 399 + #define mmSDMA0_RLC0_CSA_ADDR_HI 0x352d 400 + #define mmSDMA0_RLC0_IB_SUB_REMAIN 0x352f 401 + #define mmSDMA0_RLC0_PREEMPT 0x3530 402 + #define mmSDMA0_RLC0_DUMMY_REG 0x3531 403 + #define mmSDMA0_RLC0_MIDCMD_DATA0 0x3541 404 + #define mmSDMA0_RLC0_MIDCMD_DATA1 0x3542 405 + #define mmSDMA0_RLC0_MIDCMD_DATA2 0x3543 406 + #define mmSDMA0_RLC0_MIDCMD_DATA3 0x3544 407 + #define mmSDMA0_RLC0_MIDCMD_DATA4 0x3545 408 + #define mmSDMA0_RLC0_MIDCMD_DATA5 0x3546 409 + #define mmSDMA0_RLC0_MIDCMD_CNTL 0x3547 410 + #define mmSDMA0_RLC1_RB_CNTL 0x3580 411 + #define mmSDMA0_RLC1_RB_BASE 0x3581 412 + #define mmSDMA0_RLC1_RB_BASE_HI 0x3582 413 + #define mmSDMA0_RLC1_RB_RPTR 0x3583 414 + #define mmSDMA0_RLC1_RB_WPTR 0x3584 415 + #define mmSDMA0_RLC1_RB_WPTR_POLL_CNTL 0x3585 416 + #define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI 0x3586 417 + #define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO 0x3587 418 + #define mmSDMA0_RLC1_RB_RPTR_ADDR_HI 0x3588 419 + #define mmSDMA0_RLC1_RB_RPTR_ADDR_LO 0x3589 420 + #define mmSDMA0_RLC1_IB_CNTL 0x358a 421 + #define mmSDMA0_RLC1_IB_RPTR 0x358b 422 + #define mmSDMA0_RLC1_IB_OFFSET 0x358c 423 + #define mmSDMA0_RLC1_IB_BASE_LO 0x358d 424 + #define mmSDMA0_RLC1_IB_BASE_HI 0x358e 425 + #define mmSDMA0_RLC1_IB_SIZE 0x358f 426 + #define mmSDMA0_RLC1_SKIP_CNTL 0x3590 427 + #define mmSDMA0_RLC1_CONTEXT_STATUS 0x3591 428 + #define mmSDMA0_RLC1_DOORBELL 0x3592 429 + #define mmSDMA0_RLC1_VIRTUAL_ADDR 0x35a7 430 + #define mmSDMA0_RLC1_APE1_CNTL 0x35a8 431 + #define mmSDMA0_RLC1_DOORBELL_LOG 0x35a9 432 + #define mmSDMA0_RLC1_WATERMARK 0x35aa 433 + #define mmSDMA0_RLC1_CSA_ADDR_LO 0x35ac 434 + #define mmSDMA0_RLC1_CSA_ADDR_HI 0x35ad 435 + #define mmSDMA0_RLC1_IB_SUB_REMAIN 0x35af 436 + #define mmSDMA0_RLC1_PREEMPT 0x35b0 437 + #define mmSDMA0_RLC1_DUMMY_REG 0x35b1 438 + #define mmSDMA0_RLC1_MIDCMD_DATA0 0x35c1 439 + #define mmSDMA0_RLC1_MIDCMD_DATA1 0x35c2 440 + #define mmSDMA0_RLC1_MIDCMD_DATA2 0x35c3 441 + #define mmSDMA0_RLC1_MIDCMD_DATA3 0x35c4 442 + #define mmSDMA0_RLC1_MIDCMD_DATA4 0x35c5 443 + #define mmSDMA0_RLC1_MIDCMD_DATA5 0x35c6 444 + #define mmSDMA0_RLC1_MIDCMD_CNTL 0x35c7 445 + #define mmSDMA1_UCODE_ADDR 0x3600 446 + #define mmSDMA1_UCODE_DATA 0x3601 447 + #define mmSDMA1_POWER_CNTL 0x3602 448 + #define mmSDMA1_CLK_CTRL 0x3603 449 + #define mmSDMA1_CNTL 0x3604 450 + #define mmSDMA1_CHICKEN_BITS 0x3605 451 + #define mmSDMA1_TILING_CONFIG 0x3606 452 + #define mmSDMA1_HASH 0x3607 453 + #define mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL 0x3609 454 + #define mmSDMA1_RB_RPTR_FETCH 0x360a 455 + #define mmSDMA1_IB_OFFSET_FETCH 0x360b 456 + #define mmSDMA1_PROGRAM 0x360c 457 + #define mmSDMA1_STATUS_REG 0x360d 458 + #define mmSDMA1_STATUS1_REG 0x360e 459 + #define mmSDMA1_RD_BURST_CNTL 0x360f 460 + #define mmSDMA1_PERFMON_CNTL 0x9010 461 + #define mmSDMA1_PERFCOUNTER0_RESULT 0x9011 462 + #define mmSDMA1_PERFCOUNTER1_RESULT 0x9012 463 + #define mmSDMA1_F32_CNTL 0x3612 464 + #define mmSDMA1_FREEZE 0x3613 465 + #define mmSDMA1_PHASE0_QUANTUM 0x3614 466 + #define mmSDMA1_PHASE1_QUANTUM 0x3615 467 + #define mmSDMA1_EDC_CONFIG 0x361a 468 + #define mmSDMA1_VM_CNTL 0x3620 469 + #define mmSDMA1_VM_CTX_LO 0x3621 470 + #define mmSDMA1_VM_CTX_HI 0x3622 471 + #define mmSDMA1_STATUS2_REG 0x3623 472 + #define mmSDMA1_ACTIVE_FCN_ID 0x3624 473 + #define mmSDMA1_VM_CTX_CNTL 0x3625 474 + #define mmSDMA1_VIRT_RESET_REQ 0x3626 475 + #define mmSDMA1_VF_ENABLE 0x3627 476 + #define mmSDMA1_BA_THRESHOLD 0x361b 477 + #define mmSDMA1_ID 0x361c 478 + #define mmSDMA1_VERSION 0x361d 479 + #define mmSDMA1_ATOMIC_CNTL 0x3628 480 + #define mmSDMA1_ATOMIC_PREOP_LO 0x3629 481 + #define mmSDMA1_ATOMIC_PREOP_HI 0x362a 482 + #define mmSDMA1_POWER_CNTL_IDLE 0x362c 483 + #define mmSDMA1_PERF_REG_TYPE0 0x3677 484 + #define mmSDMA1_CONTEXT_REG_TYPE0 0x3678 485 + #define mmSDMA1_CONTEXT_REG_TYPE1 0x3679 486 + #define mmSDMA1_CONTEXT_REG_TYPE2 0x367a 487 + #define mmSDMA1_PUB_REG_TYPE0 0x367c 488 + #define mmSDMA1_PUB_REG_TYPE1 0x367d 489 + #define mmSDMA1_GFX_RB_CNTL 0x3680 490 + #define mmSDMA1_GFX_RB_BASE 0x3681 491 + #define mmSDMA1_GFX_RB_BASE_HI 0x3682 492 + #define mmSDMA1_GFX_RB_RPTR 0x3683 493 + #define mmSDMA1_GFX_RB_WPTR 0x3684 494 + #define mmSDMA1_GFX_RB_WPTR_POLL_CNTL 0x3685 495 + #define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI 0x3686 496 + #define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO 0x3687 497 + #define mmSDMA1_GFX_RB_RPTR_ADDR_HI 0x3688 498 + #define mmSDMA1_GFX_RB_RPTR_ADDR_LO 0x3689 499 + #define mmSDMA1_GFX_IB_CNTL 0x368a 500 + #define mmSDMA1_GFX_IB_RPTR 0x368b 501 + #define mmSDMA1_GFX_IB_OFFSET 0x368c 502 + #define mmSDMA1_GFX_IB_BASE_LO 0x368d 503 + #define mmSDMA1_GFX_IB_BASE_HI 0x368e 504 + #define mmSDMA1_GFX_IB_SIZE 0x368f 505 + #define mmSDMA1_GFX_SKIP_CNTL 0x3690 506 + #define mmSDMA1_GFX_CONTEXT_STATUS 0x3691 507 + #define mmSDMA1_GFX_DOORBELL 0x3692 508 + #define mmSDMA1_GFX_CONTEXT_CNTL 0x3693 509 + #define mmSDMA1_GFX_VIRTUAL_ADDR 0x36a7 510 + #define mmSDMA1_GFX_APE1_CNTL 0x36a8 511 + #define mmSDMA1_GFX_DOORBELL_LOG 0x36a9 512 + #define mmSDMA1_GFX_WATERMARK 0x36aa 513 + #define mmSDMA1_GFX_CSA_ADDR_LO 0x36ac 514 + #define mmSDMA1_GFX_CSA_ADDR_HI 0x36ad 515 + #define mmSDMA1_GFX_IB_SUB_REMAIN 0x36af 516 + #define mmSDMA1_GFX_PREEMPT 0x36b0 517 + #define mmSDMA1_GFX_DUMMY_REG 0x36b1 518 + #define mmSDMA1_GFX_MIDCMD_DATA0 0x36c1 519 + #define mmSDMA1_GFX_MIDCMD_DATA1 0x36c2 520 + #define mmSDMA1_GFX_MIDCMD_DATA2 0x36c3 521 + #define mmSDMA1_GFX_MIDCMD_DATA3 0x36c4 522 + #define mmSDMA1_GFX_MIDCMD_DATA4 0x36c5 523 + #define mmSDMA1_GFX_MIDCMD_DATA5 0x36c6 524 + #define mmSDMA1_GFX_MIDCMD_CNTL 0x36c7 525 + #define mmSDMA1_RLC0_RB_CNTL 0x3700 526 + #define mmSDMA1_RLC0_RB_BASE 0x3701 527 + #define mmSDMA1_RLC0_RB_BASE_HI 0x3702 528 + #define mmSDMA1_RLC0_RB_RPTR 0x3703 529 + #define mmSDMA1_RLC0_RB_WPTR 0x3704 530 + #define mmSDMA1_RLC0_RB_WPTR_POLL_CNTL 0x3705 531 + #define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI 0x3706 532 + #define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO 0x3707 533 + #define mmSDMA1_RLC0_RB_RPTR_ADDR_HI 0x3708 534 + #define mmSDMA1_RLC0_RB_RPTR_ADDR_LO 0x3709 535 + #define mmSDMA1_RLC0_IB_CNTL 0x370a 536 + #define mmSDMA1_RLC0_IB_RPTR 0x370b 537 + #define mmSDMA1_RLC0_IB_OFFSET 0x370c 538 + #define mmSDMA1_RLC0_IB_BASE_LO 0x370d 539 + #define mmSDMA1_RLC0_IB_BASE_HI 0x370e 540 + #define mmSDMA1_RLC0_IB_SIZE 0x370f 541 + #define mmSDMA1_RLC0_SKIP_CNTL 0x3710 542 + #define mmSDMA1_RLC0_CONTEXT_STATUS 0x3711 543 + #define mmSDMA1_RLC0_DOORBELL 0x3712 544 + #define mmSDMA1_RLC0_VIRTUAL_ADDR 0x3727 545 + #define mmSDMA1_RLC0_APE1_CNTL 0x3728 546 + #define mmSDMA1_RLC0_DOORBELL_LOG 0x3729 547 + #define mmSDMA1_RLC0_WATERMARK 0x372a 548 + #define mmSDMA1_RLC0_CSA_ADDR_LO 0x372c 549 + #define mmSDMA1_RLC0_CSA_ADDR_HI 0x372d 550 + #define mmSDMA1_RLC0_IB_SUB_REMAIN 0x372f 551 + #define mmSDMA1_RLC0_PREEMPT 0x3730 552 + #define mmSDMA1_RLC0_DUMMY_REG 0x3731 553 + #define mmSDMA1_RLC0_MIDCMD_DATA0 0x3741 554 + #define mmSDMA1_RLC0_MIDCMD_DATA1 0x3742 555 + #define mmSDMA1_RLC0_MIDCMD_DATA2 0x3743 556 + #define mmSDMA1_RLC0_MIDCMD_DATA3 0x3744 557 + #define mmSDMA1_RLC0_MIDCMD_DATA4 0x3745 558 + #define mmSDMA1_RLC0_MIDCMD_DATA5 0x3746 559 + #define mmSDMA1_RLC0_MIDCMD_CNTL 0x3747 560 + #define mmSDMA1_RLC1_RB_CNTL 0x3780 561 + #define mmSDMA1_RLC1_RB_BASE 0x3781 562 + #define mmSDMA1_RLC1_RB_BASE_HI 0x3782 563 + #define mmSDMA1_RLC1_RB_RPTR 0x3783 564 + #define mmSDMA1_RLC1_RB_WPTR 0x3784 565 + #define mmSDMA1_RLC1_RB_WPTR_POLL_CNTL 0x3785 566 + #define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI 0x3786 567 + #define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO 0x3787 568 + #define mmSDMA1_RLC1_RB_RPTR_ADDR_HI 0x3788 569 + #define mmSDMA1_RLC1_RB_RPTR_ADDR_LO 0x3789 570 + #define mmSDMA1_RLC1_IB_CNTL 0x378a 571 + #define mmSDMA1_RLC1_IB_RPTR 0x378b 572 + #define mmSDMA1_RLC1_IB_OFFSET 0x378c 573 + #define mmSDMA1_RLC1_IB_BASE_LO 0x378d 574 + #define mmSDMA1_RLC1_IB_BASE_HI 0x378e 575 + #define mmSDMA1_RLC1_IB_SIZE 0x378f 576 + #define mmSDMA1_RLC1_SKIP_CNTL 0x3790 577 + #define mmSDMA1_RLC1_CONTEXT_STATUS 0x3791 578 + #define mmSDMA1_RLC1_DOORBELL 0x3792 579 + #define mmSDMA1_RLC1_VIRTUAL_ADDR 0x37a7 580 + #define mmSDMA1_RLC1_APE1_CNTL 0x37a8 581 + #define mmSDMA1_RLC1_DOORBELL_LOG 0x37a9 582 + #define mmSDMA1_RLC1_WATERMARK 0x37aa 583 + #define mmSDMA1_RLC1_CSA_ADDR_LO 0x37ac 584 + #define mmSDMA1_RLC1_CSA_ADDR_HI 0x37ad 585 + #define mmSDMA1_RLC1_IB_SUB_REMAIN 0x37af 586 + #define mmSDMA1_RLC1_PREEMPT 0x37b0 587 + #define mmSDMA1_RLC1_DUMMY_REG 0x37b1 588 + #define mmSDMA1_RLC1_MIDCMD_DATA0 0x37c1 589 + #define mmSDMA1_RLC1_MIDCMD_DATA1 0x37c2 590 + #define mmSDMA1_RLC1_MIDCMD_DATA2 0x37c3 591 + #define mmSDMA1_RLC1_MIDCMD_DATA3 0x37c4 592 + #define mmSDMA1_RLC1_MIDCMD_DATA4 0x37c5 593 + #define mmSDMA1_RLC1_MIDCMD_DATA5 0x37c6 594 + #define mmSDMA1_RLC1_MIDCMD_CNTL 0x37c7 595 + #define mmHDP_HOST_PATH_CNTL 0xb00 596 + #define mmHDP_NONSURFACE_BASE 0xb01 597 + #define mmHDP_NONSURFACE_INFO 0xb02 598 + #define mmHDP_NONSURFACE_SIZE 0xb03 599 + #define mmHDP_NONSURF_FLAGS 0xbc9 600 + #define mmHDP_NONSURF_FLAGS_CLR 0xbca 601 + #define mmHDP_SW_SEMAPHORE 0xbcb 602 + #define mmHDP_DEBUG0 0xbcc 603 + #define mmHDP_DEBUG1 0xbcd 604 + #define mmHDP_LAST_SURFACE_HIT 0xbce 605 + #define mmHDP_TILING_CONFIG 0xbcf 606 + #define mmHDP_SC_MULTI_CHIP_CNTL 0xbd0 607 + #define mmHDP_OUTSTANDING_REQ 0xbd1 608 + #define mmHDP_ADDR_CONFIG 0xbd2 609 + #define mmHDP_MISC_CNTL 0xbd3 610 + #define mmHDP_MEM_POWER_LS 0xbd4 611 + #define mmHDP_NONSURFACE_PREFETCH 0xbd5 612 + #define mmHDP_MEMIO_CNTL 0xbf6 613 + #define mmHDP_MEMIO_ADDR 0xbf7 614 + #define mmHDP_MEMIO_STATUS 0xbf8 615 + #define mmHDP_MEMIO_WR_DATA 0xbf9 616 + #define mmHDP_MEMIO_RD_DATA 0xbfa 617 + #define mmHDP_VF_ENABLE 0xbfb 618 + #define mmHDP_XDP_DIRECT2HDP_FIRST 0xc00 619 + #define mmHDP_XDP_D2H_FLUSH 0xc01 620 + #define mmHDP_XDP_D2H_BAR_UPDATE 0xc02 621 + #define mmHDP_XDP_D2H_RSVD_3 0xc03 622 + #define mmHDP_XDP_D2H_RSVD_4 0xc04 623 + #define mmHDP_XDP_D2H_RSVD_5 0xc05 624 + #define mmHDP_XDP_D2H_RSVD_6 0xc06 625 + #define mmHDP_XDP_D2H_RSVD_7 0xc07 626 + #define mmHDP_XDP_D2H_RSVD_8 0xc08 627 + #define mmHDP_XDP_D2H_RSVD_9 0xc09 628 + #define mmHDP_XDP_D2H_RSVD_10 0xc0a 629 + #define mmHDP_XDP_D2H_RSVD_11 0xc0b 630 + #define mmHDP_XDP_D2H_RSVD_12 0xc0c 631 + #define mmHDP_XDP_D2H_RSVD_13 0xc0d 632 + #define mmHDP_XDP_D2H_RSVD_14 0xc0e 633 + #define mmHDP_XDP_D2H_RSVD_15 0xc0f 634 + #define mmHDP_XDP_D2H_RSVD_16 0xc10 635 + #define mmHDP_XDP_D2H_RSVD_17 0xc11 636 + #define mmHDP_XDP_D2H_RSVD_18 0xc12 637 + #define mmHDP_XDP_D2H_RSVD_19 0xc13 638 + #define mmHDP_XDP_D2H_RSVD_20 0xc14 639 + #define mmHDP_XDP_D2H_RSVD_21 0xc15 640 + #define mmHDP_XDP_D2H_RSVD_22 0xc16 641 + #define mmHDP_XDP_D2H_RSVD_23 0xc17 642 + #define mmHDP_XDP_D2H_RSVD_24 0xc18 643 + #define mmHDP_XDP_D2H_RSVD_25 0xc19 644 + #define mmHDP_XDP_D2H_RSVD_26 0xc1a 645 + #define mmHDP_XDP_D2H_RSVD_27 0xc1b 646 + #define mmHDP_XDP_D2H_RSVD_28 0xc1c 647 + #define mmHDP_XDP_D2H_RSVD_29 0xc1d 648 + #define mmHDP_XDP_D2H_RSVD_30 0xc1e 649 + #define mmHDP_XDP_D2H_RSVD_31 0xc1f 650 + #define mmHDP_XDP_D2H_RSVD_32 0xc20 651 + #define mmHDP_XDP_D2H_RSVD_33 0xc21 652 + #define mmHDP_XDP_D2H_RSVD_34 0xc22 653 + #define mmHDP_XDP_DIRECT2HDP_LAST 0xc23 654 + #define mmHDP_XDP_P2P_BAR_CFG 0xc24 655 + #define mmHDP_XDP_P2P_MBX_OFFSET 0xc25 656 + #define mmHDP_XDP_P2P_MBX_ADDR0 0xc26 657 + #define mmHDP_XDP_P2P_MBX_ADDR1 0xc27 658 + #define mmHDP_XDP_P2P_MBX_ADDR2 0xc28 659 + #define mmHDP_XDP_P2P_MBX_ADDR3 0xc29 660 + #define mmHDP_XDP_P2P_MBX_ADDR4 0xc2a 661 + #define mmHDP_XDP_P2P_MBX_ADDR5 0xc2b 662 + #define mmHDP_XDP_P2P_MBX_ADDR6 0xc2c 663 + #define mmHDP_XDP_HDP_MBX_MC_CFG 0xc2d 664 + #define mmHDP_XDP_HDP_MC_CFG 0xc2e 665 + #define mmHDP_XDP_HST_CFG 0xc2f 666 + #define mmHDP_XDP_SID_CFG 0xc30 667 + #define mmHDP_XDP_HDP_IPH_CFG 0xc31 668 + #define mmHDP_XDP_SRBM_CFG 0xc32 669 + #define mmHDP_XDP_CGTT_BLK_CTRL 0xc33 670 + #define mmHDP_XDP_P2P_BAR0 0xc34 671 + #define mmHDP_XDP_P2P_BAR1 0xc35 672 + #define mmHDP_XDP_P2P_BAR2 0xc36 673 + #define mmHDP_XDP_P2P_BAR3 0xc37 674 + #define mmHDP_XDP_P2P_BAR4 0xc38 675 + #define mmHDP_XDP_P2P_BAR5 0xc39 676 + #define mmHDP_XDP_P2P_BAR6 0xc3a 677 + #define mmHDP_XDP_P2P_BAR7 0xc3b 678 + #define mmHDP_XDP_FLUSH_ARMED_STS 0xc3c 679 + #define mmHDP_XDP_FLUSH_CNTR0_STS 0xc3d 680 + #define mmHDP_XDP_BUSY_STS 0xc3e 681 + #define mmHDP_XDP_STICKY 0xc3f 682 + #define mmHDP_XDP_CHKN 0xc40 683 + #define mmHDP_XDP_DBG_ADDR 0xc41 684 + #define mmHDP_XDP_DBG_DATA 0xc42 685 + #define mmHDP_XDP_DBG_MASK 0xc43 686 + #define mmHDP_XDP_BARS_ADDR_39_36 0xc44 687 + 688 + #endif /* OSS_3_0_D_H */
+1497
drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_enum.h
··· 1 + /* 2 + * OSS_3_0 Register documentation 3 + * 4 + * Copyright (C) 2014 Advanced Micro Devices, Inc. 5 + * 6 + * Permission is hereby granted, free of charge, to any person obtaining a 7 + * copy of this software and associated documentation files (the "Software"), 8 + * to deal in the Software without restriction, including without limitation 9 + * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 + * and/or sell copies of the Software, and to permit persons to whom the 11 + * Software is furnished to do so, subject to the following conditions: 12 + * 13 + * The above copyright notice and this permission notice shall be included 14 + * in all copies or substantial portions of the Software. 15 + * 16 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 20 + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21 + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22 + */ 23 + 24 + #ifndef OSS_3_0_ENUM_H 25 + #define OSS_3_0_ENUM_H 26 + 27 + typedef enum IH_CLIENT_ID { 28 + DC_IH_SRC_ID_START = 0x1, 29 + DC_IH_SRC_ID_END = 0x1f, 30 + VGA_IH_SRC_ID_START = 0x20, 31 + VGA_IH_SRC_ID_END = 0x27, 32 + CAP_IH_SRC_ID_START = 0x28, 33 + CAP_IH_SRC_ID_END = 0x2f, 34 + VIP_IH_SRC_ID_START = 0x30, 35 + VIP_IH_SRC_ID_END = 0x3f, 36 + ROM_IH_SRC_ID_START = 0x40, 37 + ROM_IH_SRC_ID_END = 0x5d, 38 + BIF_IH_SRC_ID_START = 0x5e, 39 + SAM_IH_SRC_ID_START = 0x5f, 40 + SRBM_IH_SRC_ID_START = 0x60, 41 + SRBM_IH_SRC_ID_END = 0x67, 42 + UVD_IH_SRC_ID_START = 0x72, 43 + UVD_IH_SRC_ID_END = 0x85, 44 + VMC_IH_SRC_ID_START = 0x86, 45 + VMC_IH_SRC_ID_END = 0x8f, 46 + RLC_IH_SRC_ID_START = 0x90, 47 + RLC_IH_SRC_ID_END = 0xf3, 48 + PDMA_IH_SRC_ID_START = 0xf4, 49 + PDMA_IH_SRC_ID_END = 0xf7, 50 + CG_IH_SRC_ID_START = 0xf8, 51 + CG_IH_SRC_ID_END = 0xff, 52 + } IH_CLIENT_ID; 53 + typedef enum IH_PERF_SEL { 54 + IH_PERF_SEL_CYCLE = 0x0, 55 + IH_PERF_SEL_IDLE = 0x1, 56 + IH_PERF_SEL_INPUT_IDLE = 0x2, 57 + IH_PERF_SEL_CLIENT0_IH_STALL = 0x3, 58 + IH_PERF_SEL_CLIENT1_IH_STALL = 0x4, 59 + IH_PERF_SEL_CLIENT2_IH_STALL = 0x5, 60 + IH_PERF_SEL_CLIENT3_IH_STALL = 0x6, 61 + IH_PERF_SEL_CLIENT4_IH_STALL = 0x7, 62 + IH_PERF_SEL_CLIENT5_IH_STALL = 0x8, 63 + IH_PERF_SEL_CLIENT6_IH_STALL = 0x9, 64 + IH_PERF_SEL_CLIENT7_IH_STALL = 0xa, 65 + IH_PERF_SEL_RB_IDLE = 0xb, 66 + IH_PERF_SEL_RB_FULL = 0xc, 67 + IH_PERF_SEL_RB_OVERFLOW = 0xd, 68 + IH_PERF_SEL_RB_WPTR_WRITEBACK = 0xe, 69 + IH_PERF_SEL_RB_WPTR_WRAP = 0xf, 70 + IH_PERF_SEL_RB_RPTR_WRAP = 0x10, 71 + IH_PERF_SEL_MC_WR_IDLE = 0x11, 72 + IH_PERF_SEL_MC_WR_COUNT = 0x12, 73 + IH_PERF_SEL_MC_WR_STALL = 0x13, 74 + IH_PERF_SEL_MC_WR_CLEAN_PENDING = 0x14, 75 + IH_PERF_SEL_MC_WR_CLEAN_STALL = 0x15, 76 + IH_PERF_SEL_BIF_RISING = 0x16, 77 + IH_PERF_SEL_BIF_FALLING = 0x17, 78 + IH_PERF_SEL_CLIENT8_IH_STALL = 0x18, 79 + IH_PERF_SEL_CLIENT9_IH_STALL = 0x19, 80 + IH_PERF_SEL_CLIENT10_IH_STALL = 0x1a, 81 + IH_PERF_SEL_CLIENT11_IH_STALL = 0x1b, 82 + IH_PERF_SEL_CLIENT12_IH_STALL = 0x1c, 83 + IH_PERF_SEL_CLIENT13_IH_STALL = 0x1d, 84 + IH_PERF_SEL_CLIENT14_IH_STALL = 0x1e, 85 + IH_PERF_SEL_CLIENT15_IH_STALL = 0x1f, 86 + IH_PERF_SEL_CLIENT16_IH_STALL = 0x20, 87 + IH_PERF_SEL_CLIENT17_IH_STALL = 0x21, 88 + IH_PERF_SEL_CLIENT18_IH_STALL = 0x22, 89 + IH_PERF_SEL_CLIENT19_IH_STALL = 0x23, 90 + IH_PERF_SEL_CLIENT20_IH_STALL = 0x24, 91 + IH_PERF_SEL_CLIENT21_IH_STALL = 0x25, 92 + IH_PERF_SEL_CLIENT22_IH_STALL = 0x26, 93 + IH_PERF_SEL_RB_FULL_VF0 = 0x27, 94 + IH_PERF_SEL_RB_FULL_VF1 = 0x28, 95 + IH_PERF_SEL_RB_FULL_VF2 = 0x29, 96 + IH_PERF_SEL_RB_FULL_VF3 = 0x2a, 97 + IH_PERF_SEL_RB_FULL_VF4 = 0x2b, 98 + IH_PERF_SEL_RB_FULL_VF5 = 0x2c, 99 + IH_PERF_SEL_RB_FULL_VF6 = 0x2d, 100 + IH_PERF_SEL_RB_FULL_VF7 = 0x2e, 101 + IH_PERF_SEL_RB_FULL_VF8 = 0x2f, 102 + IH_PERF_SEL_RB_FULL_VF9 = 0x30, 103 + IH_PERF_SEL_RB_FULL_VF10 = 0x31, 104 + IH_PERF_SEL_RB_FULL_VF11 = 0x32, 105 + IH_PERF_SEL_RB_FULL_VF12 = 0x33, 106 + IH_PERF_SEL_RB_FULL_VF13 = 0x34, 107 + IH_PERF_SEL_RB_FULL_VF14 = 0x35, 108 + IH_PERF_SEL_RB_FULL_VF15 = 0x36, 109 + IH_PERF_SEL_RB_OVERFLOW_VF0 = 0x37, 110 + IH_PERF_SEL_RB_OVERFLOW_VF1 = 0x38, 111 + IH_PERF_SEL_RB_OVERFLOW_VF2 = 0x39, 112 + IH_PERF_SEL_RB_OVERFLOW_VF3 = 0x3a, 113 + IH_PERF_SEL_RB_OVERFLOW_VF4 = 0x3b, 114 + IH_PERF_SEL_RB_OVERFLOW_VF5 = 0x3c, 115 + IH_PERF_SEL_RB_OVERFLOW_VF6 = 0x3d, 116 + IH_PERF_SEL_RB_OVERFLOW_VF7 = 0x3e, 117 + IH_PERF_SEL_RB_OVERFLOW_VF8 = 0x3f, 118 + IH_PERF_SEL_RB_OVERFLOW_VF9 = 0x40, 119 + IH_PERF_SEL_RB_OVERFLOW_VF10 = 0x41, 120 + IH_PERF_SEL_RB_OVERFLOW_VF11 = 0x42, 121 + IH_PERF_SEL_RB_OVERFLOW_VF12 = 0x43, 122 + IH_PERF_SEL_RB_OVERFLOW_VF13 = 0x44, 123 + IH_PERF_SEL_RB_OVERFLOW_VF14 = 0x45, 124 + IH_PERF_SEL_RB_OVERFLOW_VF15 = 0x46, 125 + IH_PERF_SEL_RB_WPTR_WRITEBACK_VF0 = 0x47, 126 + IH_PERF_SEL_RB_WPTR_WRITEBACK_VF1 = 0x48, 127 + IH_PERF_SEL_RB_WPTR_WRITEBACK_VF2 = 0x49, 128 + IH_PERF_SEL_RB_WPTR_WRITEBACK_VF3 = 0x4a, 129 + IH_PERF_SEL_RB_WPTR_WRITEBACK_VF4 = 0x4b, 130 + IH_PERF_SEL_RB_WPTR_WRITEBACK_VF5 = 0x4c, 131 + IH_PERF_SEL_RB_WPTR_WRITEBACK_VF6 = 0x4d, 132 + IH_PERF_SEL_RB_WPTR_WRITEBACK_VF7 = 0x4e, 133 + IH_PERF_SEL_RB_WPTR_WRITEBACK_VF8 = 0x4f, 134 + IH_PERF_SEL_RB_WPTR_WRITEBACK_VF9 = 0x50, 135 + IH_PERF_SEL_RB_WPTR_WRITEBACK_VF10 = 0x51, 136 + IH_PERF_SEL_RB_WPTR_WRITEBACK_VF11 = 0x52, 137 + IH_PERF_SEL_RB_WPTR_WRITEBACK_VF12 = 0x53, 138 + IH_PERF_SEL_RB_WPTR_WRITEBACK_VF13 = 0x54, 139 + IH_PERF_SEL_RB_WPTR_WRITEBACK_VF14 = 0x55, 140 + IH_PERF_SEL_RB_WPTR_WRITEBACK_VF15 = 0x56, 141 + IH_PERF_SEL_RB_WPTR_WRAP_VF0 = 0x57, 142 + IH_PERF_SEL_RB_WPTR_WRAP_VF1 = 0x58, 143 + IH_PERF_SEL_RB_WPTR_WRAP_VF2 = 0x59, 144 + IH_PERF_SEL_RB_WPTR_WRAP_VF3 = 0x5a, 145 + IH_PERF_SEL_RB_WPTR_WRAP_VF4 = 0x5b, 146 + IH_PERF_SEL_RB_WPTR_WRAP_VF5 = 0x5c, 147 + IH_PERF_SEL_RB_WPTR_WRAP_VF6 = 0x5d, 148 + IH_PERF_SEL_RB_WPTR_WRAP_VF7 = 0x5e, 149 + IH_PERF_SEL_RB_WPTR_WRAP_VF8 = 0x5f, 150 + IH_PERF_SEL_RB_WPTR_WRAP_VF9 = 0x60, 151 + IH_PERF_SEL_RB_WPTR_WRAP_VF10 = 0x61, 152 + IH_PERF_SEL_RB_WPTR_WRAP_VF11 = 0x62, 153 + IH_PERF_SEL_RB_WPTR_WRAP_VF12 = 0x63, 154 + IH_PERF_SEL_RB_WPTR_WRAP_VF13 = 0x64, 155 + IH_PERF_SEL_RB_WPTR_WRAP_VF14 = 0x65, 156 + IH_PERF_SEL_RB_WPTR_WRAP_VF15 = 0x66, 157 + IH_PERF_SEL_RB_RPTR_WRAP_VF0 = 0x67, 158 + IH_PERF_SEL_RB_RPTR_WRAP_VF1 = 0x68, 159 + IH_PERF_SEL_RB_RPTR_WRAP_VF2 = 0x69, 160 + IH_PERF_SEL_RB_RPTR_WRAP_VF3 = 0x6a, 161 + IH_PERF_SEL_RB_RPTR_WRAP_VF4 = 0x6b, 162 + IH_PERF_SEL_RB_RPTR_WRAP_VF5 = 0x6c, 163 + IH_PERF_SEL_RB_RPTR_WRAP_VF6 = 0x6d, 164 + IH_PERF_SEL_RB_RPTR_WRAP_VF7 = 0x6e, 165 + IH_PERF_SEL_RB_RPTR_WRAP_VF8 = 0x6f, 166 + IH_PERF_SEL_RB_RPTR_WRAP_VF9 = 0x70, 167 + IH_PERF_SEL_RB_RPTR_WRAP_VF10 = 0x71, 168 + IH_PERF_SEL_RB_RPTR_WRAP_VF11 = 0x72, 169 + IH_PERF_SEL_RB_RPTR_WRAP_VF12 = 0x73, 170 + IH_PERF_SEL_RB_RPTR_WRAP_VF13 = 0x74, 171 + IH_PERF_SEL_RB_RPTR_WRAP_VF14 = 0x75, 172 + IH_PERF_SEL_RB_RPTR_WRAP_VF15 = 0x76, 173 + IH_PERF_SEL_BIF_RISING_VF0 = 0x77, 174 + IH_PERF_SEL_BIF_RISING_VF1 = 0x78, 175 + IH_PERF_SEL_BIF_RISING_VF2 = 0x79, 176 + IH_PERF_SEL_BIF_RISING_VF3 = 0x7a, 177 + IH_PERF_SEL_BIF_RISING_VF4 = 0x7b, 178 + IH_PERF_SEL_BIF_RISING_VF5 = 0x7c, 179 + IH_PERF_SEL_BIF_RISING_VF6 = 0x7d, 180 + IH_PERF_SEL_BIF_RISING_VF7 = 0x7e, 181 + IH_PERF_SEL_BIF_RISING_VF8 = 0x7f, 182 + IH_PERF_SEL_BIF_RISING_VF9 = 0x80, 183 + IH_PERF_SEL_BIF_RISING_VF10 = 0x81, 184 + IH_PERF_SEL_BIF_RISING_VF11 = 0x82, 185 + IH_PERF_SEL_BIF_RISING_VF12 = 0x83, 186 + IH_PERF_SEL_BIF_RISING_VF13 = 0x84, 187 + IH_PERF_SEL_BIF_RISING_VF14 = 0x85, 188 + IH_PERF_SEL_BIF_RISING_VF15 = 0x86, 189 + IH_PERF_SEL_BIF_FALLING_VF0 = 0x87, 190 + IH_PERF_SEL_BIF_FALLING_VF1 = 0x88, 191 + IH_PERF_SEL_BIF_FALLING_VF2 = 0x89, 192 + IH_PERF_SEL_BIF_FALLING_VF3 = 0x8a, 193 + IH_PERF_SEL_BIF_FALLING_VF4 = 0x8b, 194 + IH_PERF_SEL_BIF_FALLING_VF5 = 0x8c, 195 + IH_PERF_SEL_BIF_FALLING_VF6 = 0x8d, 196 + IH_PERF_SEL_BIF_FALLING_VF7 = 0x8e, 197 + IH_PERF_SEL_BIF_FALLING_VF8 = 0x8f, 198 + IH_PERF_SEL_BIF_FALLING_VF9 = 0x90, 199 + IH_PERF_SEL_BIF_FALLING_VF10 = 0x91, 200 + IH_PERF_SEL_BIF_FALLING_VF11 = 0x92, 201 + IH_PERF_SEL_BIF_FALLING_VF12 = 0x93, 202 + IH_PERF_SEL_BIF_FALLING_VF13 = 0x94, 203 + IH_PERF_SEL_BIF_FALLING_VF14 = 0x95, 204 + IH_PERF_SEL_BIF_FALLING_VF15 = 0x96, 205 + } IH_PERF_SEL; 206 + typedef enum SRBM_PERFCOUNT1_SEL { 207 + SRBM_PERF_SEL_COUNT = 0x0, 208 + SRBM_PERF_SEL_BIF_BUSY = 0x1, 209 + SRBM_PERF_SEL_SDMA0_BUSY = 0x3, 210 + SRBM_PERF_SEL_IH_BUSY = 0x4, 211 + SRBM_PERF_SEL_MCB_BUSY = 0x5, 212 + SRBM_PERF_SEL_MCB_NON_DISPLAY_BUSY = 0x6, 213 + SRBM_PERF_SEL_MCC_BUSY = 0x7, 214 + SRBM_PERF_SEL_MCD_BUSY = 0x8, 215 + SRBM_PERF_SEL_CHUB_BUSY = 0x9, 216 + SRBM_PERF_SEL_SEM_BUSY = 0xa, 217 + SRBM_PERF_SEL_UVD_BUSY = 0xb, 218 + SRBM_PERF_SEL_VMC_BUSY = 0xc, 219 + SRBM_PERF_SEL_ODE_BUSY = 0xd, 220 + SRBM_PERF_SEL_SDMA1_BUSY = 0xe, 221 + SRBM_PERF_SEL_SAMMSP_BUSY = 0xf, 222 + SRBM_PERF_SEL_VCE0_BUSY = 0x10, 223 + SRBM_PERF_SEL_XDMA_BUSY = 0x11, 224 + SRBM_PERF_SEL_ACP_BUSY = 0x12, 225 + SRBM_PERF_SEL_SDMA2_BUSY = 0x13, 226 + SRBM_PERF_SEL_SDMA3_BUSY = 0x14, 227 + SRBM_PERF_SEL_SAMSCP_BUSY = 0x15, 228 + SRBM_PERF_SEL_VMC1_BUSY = 0x16, 229 + SRBM_PERF_SEL_ISP_BUSY = 0x17, 230 + SRBM_PERF_SEL_VCE1_BUSY = 0x18, 231 + SRBM_PERF_SEL_GCATCL2_BUSY = 0x19, 232 + SRBM_PERF_SEL_OSATCL2_BUSY = 0x1a, 233 + SRBM_PERF_SEL_VP8_BUSY = 0x1b, 234 + } SRBM_PERFCOUNT1_SEL; 235 + typedef enum SYS_GRBM_GFX_INDEX_SEL { 236 + GRBM_GFX_INDEX_BIF = 0x0, 237 + GRBM_GFX_INDEX_SDMA0 = 0x1, 238 + GRBM_GFX_INDEX_SDMA1 = 0x2, 239 + RESEVERED0 = 0x3, 240 + GRBM_GFX_INDEX_UVD = 0x4, 241 + GRBM_GFX_INDEX_VCE0 = 0x5, 242 + GRBM_GFX_INDEX_VCE1 = 0x6, 243 + GRBM_GFX_INDEX_ACP = 0x7, 244 + GRBM_GFX_INDEX_SMU = 0x8, 245 + GRBM_GFX_INDEX_SAMMSP = 0x9, 246 + GRBM_GFX_INDEX_SAMSCP = 0xa, 247 + GRBM_GFX_INDEX_ISP = 0xb, 248 + GRBM_GFX_INDEX_TST = 0xc, 249 + GRBM_GFX_INDEX_SDMA2 = 0xd, 250 + GRBM_GFX_INDEX_SDMA3 = 0xe, 251 + } SYS_GRBM_GFX_INDEX_SEL; 252 + typedef enum SRBM_GFX_CNTL_SEL { 253 + SRBM_GFX_CNTL_BIF = 0x0, 254 + SRBM_GFX_CNTL_SDMA0 = 0x1, 255 + SRBM_GFX_CNTL_SDMA1 = 0x2, 256 + SRBM_GFX_CNTL_GRBM = 0x3, 257 + SRBM_GFX_CNTL_UVD = 0x4, 258 + SRBM_GFX_CNTL_VCE0 = 0x5, 259 + SRBM_GFX_CNTL_VCE1 = 0x6, 260 + SRBM_GFX_CNTL_ACP = 0x7, 261 + SRBM_GFX_CNTL_SMU = 0x8, 262 + SRBM_GFX_CNTL_SAMMSP = 0x9, 263 + SRBM_GFX_CNTL_SAMSCP = 0xa, 264 + SRBM_GFX_CNTL_ISP = 0xb, 265 + SRBM_GFX_CNTL_TST = 0xc, 266 + SRBM_GFX_CNTL_SDMA2 = 0xd, 267 + SRBM_GFX_CNTL_SDMA3 = 0xe, 268 + } SRBM_GFX_CNTL_SEL; 269 + typedef enum SDMA_PERF_SEL { 270 + SDMA_PERF_SEL_CYCLE = 0x0, 271 + SDMA_PERF_SEL_IDLE = 0x1, 272 + SDMA_PERF_SEL_REG_IDLE = 0x2, 273 + SDMA_PERF_SEL_RB_EMPTY = 0x3, 274 + SDMA_PERF_SEL_RB_FULL = 0x4, 275 + SDMA_PERF_SEL_RB_WPTR_WRAP = 0x5, 276 + SDMA_PERF_SEL_RB_RPTR_WRAP = 0x6, 277 + SDMA_PERF_SEL_RB_WPTR_POLL_READ = 0x7, 278 + SDMA_PERF_SEL_RB_RPTR_WB = 0x8, 279 + SDMA_PERF_SEL_RB_CMD_IDLE = 0x9, 280 + SDMA_PERF_SEL_RB_CMD_FULL = 0xa, 281 + SDMA_PERF_SEL_IB_CMD_IDLE = 0xb, 282 + SDMA_PERF_SEL_IB_CMD_FULL = 0xc, 283 + SDMA_PERF_SEL_EX_IDLE = 0xd, 284 + SDMA_PERF_SEL_SRBM_REG_SEND = 0xe, 285 + SDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE = 0xf, 286 + SDMA_PERF_SEL_MC_WR_IDLE = 0x10, 287 + SDMA_PERF_SEL_MC_WR_COUNT = 0x11, 288 + SDMA_PERF_SEL_MC_RD_IDLE = 0x12, 289 + SDMA_PERF_SEL_MC_RD_COUNT = 0x13, 290 + SDMA_PERF_SEL_MC_RD_RET_STALL = 0x14, 291 + SDMA_PERF_SEL_MC_RD_NO_POLL_IDLE = 0x15, 292 + SDMA_PERF_SEL_SEM_IDLE = 0x18, 293 + SDMA_PERF_SEL_SEM_REQ_STALL = 0x19, 294 + SDMA_PERF_SEL_SEM_REQ_COUNT = 0x1a, 295 + SDMA_PERF_SEL_SEM_RESP_INCOMPLETE = 0x1b, 296 + SDMA_PERF_SEL_SEM_RESP_FAIL = 0x1c, 297 + SDMA_PERF_SEL_SEM_RESP_PASS = 0x1d, 298 + SDMA_PERF_SEL_INT_IDLE = 0x1e, 299 + SDMA_PERF_SEL_INT_REQ_STALL = 0x1f, 300 + SDMA_PERF_SEL_INT_REQ_COUNT = 0x20, 301 + SDMA_PERF_SEL_INT_RESP_ACCEPTED = 0x21, 302 + SDMA_PERF_SEL_INT_RESP_RETRY = 0x22, 303 + SDMA_PERF_SEL_NUM_PACKET = 0x23, 304 + SDMA_PERF_SEL_CE_WREQ_IDLE = 0x25, 305 + SDMA_PERF_SEL_CE_WR_IDLE = 0x26, 306 + SDMA_PERF_SEL_CE_SPLIT_IDLE = 0x27, 307 + SDMA_PERF_SEL_CE_RREQ_IDLE = 0x28, 308 + SDMA_PERF_SEL_CE_OUT_IDLE = 0x29, 309 + SDMA_PERF_SEL_CE_IN_IDLE = 0x2a, 310 + SDMA_PERF_SEL_CE_DST_IDLE = 0x2b, 311 + SDMA_PERF_SEL_CE_AFIFO_FULL = 0x2e, 312 + SDMA_PERF_SEL_CE_INFO_FULL = 0x31, 313 + SDMA_PERF_SEL_CE_INFO1_FULL = 0x32, 314 + SDMA_PERF_SEL_CE_RD_STALL = 0x33, 315 + SDMA_PERF_SEL_CE_WR_STALL = 0x34, 316 + SDMA_PERF_SEL_GFX_SELECT = 0x35, 317 + SDMA_PERF_SEL_RLC0_SELECT = 0x36, 318 + SDMA_PERF_SEL_RLC1_SELECT = 0x37, 319 + SDMA_PERF_SEL_CTX_CHANGE = 0x38, 320 + SDMA_PERF_SEL_CTX_CHANGE_EXPIRED = 0x39, 321 + SDMA_PERF_SEL_CTX_CHANGE_EXCEPTION = 0x3a, 322 + SDMA_PERF_SEL_DOORBELL = 0x3b, 323 + SDMA_PERF_SEL_RD_BA_RTR = 0x3c, 324 + SDMA_PERF_SEL_WR_BA_RTR = 0x3d, 325 + } SDMA_PERF_SEL; 326 + typedef enum SurfaceEndian { 327 + ENDIAN_NONE = 0x0, 328 + ENDIAN_8IN16 = 0x1, 329 + ENDIAN_8IN32 = 0x2, 330 + ENDIAN_8IN64 = 0x3, 331 + } SurfaceEndian; 332 + typedef enum ArrayMode { 333 + ARRAY_LINEAR_GENERAL = 0x0, 334 + ARRAY_LINEAR_ALIGNED = 0x1, 335 + ARRAY_1D_TILED_THIN1 = 0x2, 336 + ARRAY_1D_TILED_THICK = 0x3, 337 + ARRAY_2D_TILED_THIN1 = 0x4, 338 + ARRAY_PRT_TILED_THIN1 = 0x5, 339 + ARRAY_PRT_2D_TILED_THIN1 = 0x6, 340 + ARRAY_2D_TILED_THICK = 0x7, 341 + ARRAY_2D_TILED_XTHICK = 0x8, 342 + ARRAY_PRT_TILED_THICK = 0x9, 343 + ARRAY_PRT_2D_TILED_THICK = 0xa, 344 + ARRAY_PRT_3D_TILED_THIN1 = 0xb, 345 + ARRAY_3D_TILED_THIN1 = 0xc, 346 + ARRAY_3D_TILED_THICK = 0xd, 347 + ARRAY_3D_TILED_XTHICK = 0xe, 348 + ARRAY_PRT_3D_TILED_THICK = 0xf, 349 + } ArrayMode; 350 + typedef enum PipeTiling { 351 + CONFIG_1_PIPE = 0x0, 352 + CONFIG_2_PIPE = 0x1, 353 + CONFIG_4_PIPE = 0x2, 354 + CONFIG_8_PIPE = 0x3, 355 + } PipeTiling; 356 + typedef enum BankTiling { 357 + CONFIG_4_BANK = 0x0, 358 + CONFIG_8_BANK = 0x1, 359 + } BankTiling; 360 + typedef enum GroupInterleave { 361 + CONFIG_256B_GROUP = 0x0, 362 + CONFIG_512B_GROUP = 0x1, 363 + } GroupInterleave; 364 + typedef enum RowTiling { 365 + CONFIG_1KB_ROW = 0x0, 366 + CONFIG_2KB_ROW = 0x1, 367 + CONFIG_4KB_ROW = 0x2, 368 + CONFIG_8KB_ROW = 0x3, 369 + CONFIG_1KB_ROW_OPT = 0x4, 370 + CONFIG_2KB_ROW_OPT = 0x5, 371 + CONFIG_4KB_ROW_OPT = 0x6, 372 + CONFIG_8KB_ROW_OPT = 0x7, 373 + } RowTiling; 374 + typedef enum BankSwapBytes { 375 + CONFIG_128B_SWAPS = 0x0, 376 + CONFIG_256B_SWAPS = 0x1, 377 + CONFIG_512B_SWAPS = 0x2, 378 + CONFIG_1KB_SWAPS = 0x3, 379 + } BankSwapBytes; 380 + typedef enum SampleSplitBytes { 381 + CONFIG_1KB_SPLIT = 0x0, 382 + CONFIG_2KB_SPLIT = 0x1, 383 + CONFIG_4KB_SPLIT = 0x2, 384 + CONFIG_8KB_SPLIT = 0x3, 385 + } SampleSplitBytes; 386 + typedef enum NumPipes { 387 + ADDR_CONFIG_1_PIPE = 0x0, 388 + ADDR_CONFIG_2_PIPE = 0x1, 389 + ADDR_CONFIG_4_PIPE = 0x2, 390 + ADDR_CONFIG_8_PIPE = 0x3, 391 + } NumPipes; 392 + typedef enum PipeInterleaveSize { 393 + ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x0, 394 + ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x1, 395 + } PipeInterleaveSize; 396 + typedef enum BankInterleaveSize { 397 + ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x0, 398 + ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x1, 399 + ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2, 400 + ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x3, 401 + } BankInterleaveSize; 402 + typedef enum NumShaderEngines { 403 + ADDR_CONFIG_1_SHADER_ENGINE = 0x0, 404 + ADDR_CONFIG_2_SHADER_ENGINE = 0x1, 405 + } NumShaderEngines; 406 + typedef enum ShaderEngineTileSize { 407 + ADDR_CONFIG_SE_TILE_16 = 0x0, 408 + ADDR_CONFIG_SE_TILE_32 = 0x1, 409 + } ShaderEngineTileSize; 410 + typedef enum NumGPUs { 411 + ADDR_CONFIG_1_GPU = 0x0, 412 + ADDR_CONFIG_2_GPU = 0x1, 413 + ADDR_CONFIG_4_GPU = 0x2, 414 + } NumGPUs; 415 + typedef enum MultiGPUTileSize { 416 + ADDR_CONFIG_GPU_TILE_16 = 0x0, 417 + ADDR_CONFIG_GPU_TILE_32 = 0x1, 418 + ADDR_CONFIG_GPU_TILE_64 = 0x2, 419 + ADDR_CONFIG_GPU_TILE_128 = 0x3, 420 + } MultiGPUTileSize; 421 + typedef enum RowSize { 422 + ADDR_CONFIG_1KB_ROW = 0x0, 423 + ADDR_CONFIG_2KB_ROW = 0x1, 424 + ADDR_CONFIG_4KB_ROW = 0x2, 425 + } RowSize; 426 + typedef enum NumLowerPipes { 427 + ADDR_CONFIG_1_LOWER_PIPES = 0x0, 428 + ADDR_CONFIG_2_LOWER_PIPES = 0x1, 429 + } NumLowerPipes; 430 + typedef enum DebugBlockId { 431 + DBG_CLIENT_BLKID_RESERVED = 0x0, 432 + DBG_CLIENT_BLKID_dbg = 0x1, 433 + DBG_CLIENT_BLKID_scf2 = 0x2, 434 + DBG_CLIENT_BLKID_mcd5 = 0x3, 435 + DBG_CLIENT_BLKID_vmc = 0x4, 436 + DBG_CLIENT_BLKID_sx30 = 0x5, 437 + DBG_CLIENT_BLKID_mcd2 = 0x6, 438 + DBG_CLIENT_BLKID_bci1 = 0x7, 439 + DBG_CLIENT_BLKID_xdma_dbg_client_wrapper = 0x8, 440 + DBG_CLIENT_BLKID_mcc0 = 0x9, 441 + DBG_CLIENT_BLKID_uvdf_0 = 0xa, 442 + DBG_CLIENT_BLKID_uvdf_1 = 0xb, 443 + DBG_CLIENT_BLKID_uvdf_2 = 0xc, 444 + DBG_CLIENT_BLKID_uvdi_0 = 0xd, 445 + DBG_CLIENT_BLKID_bci0 = 0xe, 446 + DBG_CLIENT_BLKID_vcec0_0 = 0xf, 447 + DBG_CLIENT_BLKID_cb100 = 0x10, 448 + DBG_CLIENT_BLKID_cb001 = 0x11, 449 + DBG_CLIENT_BLKID_mcd4 = 0x12, 450 + DBG_CLIENT_BLKID_tmonw00 = 0x13, 451 + DBG_CLIENT_BLKID_cb101 = 0x14, 452 + DBG_CLIENT_BLKID_sx10 = 0x15, 453 + DBG_CLIENT_BLKID_cb301 = 0x16, 454 + DBG_CLIENT_BLKID_tmonw01 = 0x17, 455 + DBG_CLIENT_BLKID_vcea0_0 = 0x18, 456 + DBG_CLIENT_BLKID_vcea0_1 = 0x19, 457 + DBG_CLIENT_BLKID_vcea0_2 = 0x1a, 458 + DBG_CLIENT_BLKID_vcea0_3 = 0x1b, 459 + DBG_CLIENT_BLKID_scf1 = 0x1c, 460 + DBG_CLIENT_BLKID_sx20 = 0x1d, 461 + DBG_CLIENT_BLKID_spim1 = 0x1e, 462 + DBG_CLIENT_BLKID_pa10 = 0x1f, 463 + DBG_CLIENT_BLKID_pa00 = 0x20, 464 + DBG_CLIENT_BLKID_gmcon = 0x21, 465 + DBG_CLIENT_BLKID_mcb = 0x22, 466 + DBG_CLIENT_BLKID_vgt0 = 0x23, 467 + DBG_CLIENT_BLKID_pc0 = 0x24, 468 + DBG_CLIENT_BLKID_bci2 = 0x25, 469 + DBG_CLIENT_BLKID_uvdb_0 = 0x26, 470 + DBG_CLIENT_BLKID_spim3 = 0x27, 471 + DBG_CLIENT_BLKID_cpc_0 = 0x28, 472 + DBG_CLIENT_BLKID_cpc_1 = 0x29, 473 + DBG_CLIENT_BLKID_uvdm_0 = 0x2a, 474 + DBG_CLIENT_BLKID_uvdm_1 = 0x2b, 475 + DBG_CLIENT_BLKID_uvdm_2 = 0x2c, 476 + DBG_CLIENT_BLKID_uvdm_3 = 0x2d, 477 + DBG_CLIENT_BLKID_cb000 = 0x2e, 478 + DBG_CLIENT_BLKID_spim0 = 0x2f, 479 + DBG_CLIENT_BLKID_mcc2 = 0x30, 480 + DBG_CLIENT_BLKID_ds0 = 0x31, 481 + DBG_CLIENT_BLKID_srbm = 0x32, 482 + DBG_CLIENT_BLKID_ih = 0x33, 483 + DBG_CLIENT_BLKID_sem = 0x34, 484 + DBG_CLIENT_BLKID_sdma_0 = 0x35, 485 + DBG_CLIENT_BLKID_sdma_1 = 0x36, 486 + DBG_CLIENT_BLKID_hdp = 0x37, 487 + DBG_CLIENT_BLKID_acp_0 = 0x38, 488 + DBG_CLIENT_BLKID_acp_1 = 0x39, 489 + DBG_CLIENT_BLKID_cb200 = 0x3a, 490 + DBG_CLIENT_BLKID_scf3 = 0x3b, 491 + DBG_CLIENT_BLKID_vceb1_0 = 0x3c, 492 + DBG_CLIENT_BLKID_vcea1_0 = 0x3d, 493 + DBG_CLIENT_BLKID_vcea1_1 = 0x3e, 494 + DBG_CLIENT_BLKID_vcea1_2 = 0x3f, 495 + DBG_CLIENT_BLKID_vcea1_3 = 0x40, 496 + DBG_CLIENT_BLKID_bci3 = 0x41, 497 + DBG_CLIENT_BLKID_mcd0 = 0x42, 498 + DBG_CLIENT_BLKID_pa11 = 0x43, 499 + DBG_CLIENT_BLKID_pa01 = 0x44, 500 + DBG_CLIENT_BLKID_cb201 = 0x45, 501 + DBG_CLIENT_BLKID_spim2 = 0x46, 502 + DBG_CLIENT_BLKID_vgt2 = 0x47, 503 + DBG_CLIENT_BLKID_pc2 = 0x48, 504 + DBG_CLIENT_BLKID_smu_0 = 0x49, 505 + DBG_CLIENT_BLKID_smu_1 = 0x4a, 506 + DBG_CLIENT_BLKID_smu_2 = 0x4b, 507 + DBG_CLIENT_BLKID_cb1 = 0x4c, 508 + DBG_CLIENT_BLKID_ia0 = 0x4d, 509 + DBG_CLIENT_BLKID_wd = 0x4e, 510 + DBG_CLIENT_BLKID_ia1 = 0x4f, 511 + DBG_CLIENT_BLKID_vcec1_0 = 0x50, 512 + DBG_CLIENT_BLKID_scf0 = 0x51, 513 + DBG_CLIENT_BLKID_vgt1 = 0x52, 514 + DBG_CLIENT_BLKID_pc1 = 0x53, 515 + DBG_CLIENT_BLKID_cb0 = 0x54, 516 + DBG_CLIENT_BLKID_gdc_one_0 = 0x55, 517 + DBG_CLIENT_BLKID_gdc_one_1 = 0x56, 518 + DBG_CLIENT_BLKID_gdc_one_2 = 0x57, 519 + DBG_CLIENT_BLKID_gdc_one_3 = 0x58, 520 + DBG_CLIENT_BLKID_gdc_one_4 = 0x59, 521 + DBG_CLIENT_BLKID_gdc_one_5 = 0x5a, 522 + DBG_CLIENT_BLKID_gdc_one_6 = 0x5b, 523 + DBG_CLIENT_BLKID_gdc_one_7 = 0x5c, 524 + DBG_CLIENT_BLKID_gdc_one_8 = 0x5d, 525 + DBG_CLIENT_BLKID_gdc_one_9 = 0x5e, 526 + DBG_CLIENT_BLKID_gdc_one_10 = 0x5f, 527 + DBG_CLIENT_BLKID_gdc_one_11 = 0x60, 528 + DBG_CLIENT_BLKID_gdc_one_12 = 0x61, 529 + DBG_CLIENT_BLKID_gdc_one_13 = 0x62, 530 + DBG_CLIENT_BLKID_gdc_one_14 = 0x63, 531 + DBG_CLIENT_BLKID_gdc_one_15 = 0x64, 532 + DBG_CLIENT_BLKID_gdc_one_16 = 0x65, 533 + DBG_CLIENT_BLKID_gdc_one_17 = 0x66, 534 + DBG_CLIENT_BLKID_gdc_one_18 = 0x67, 535 + DBG_CLIENT_BLKID_gdc_one_19 = 0x68, 536 + DBG_CLIENT_BLKID_gdc_one_20 = 0x69, 537 + DBG_CLIENT_BLKID_gdc_one_21 = 0x6a, 538 + DBG_CLIENT_BLKID_gdc_one_22 = 0x6b, 539 + DBG_CLIENT_BLKID_gdc_one_23 = 0x6c, 540 + DBG_CLIENT_BLKID_gdc_one_24 = 0x6d, 541 + DBG_CLIENT_BLKID_gdc_one_25 = 0x6e, 542 + DBG_CLIENT_BLKID_gdc_one_26 = 0x6f, 543 + DBG_CLIENT_BLKID_gdc_one_27 = 0x70, 544 + DBG_CLIENT_BLKID_gdc_one_28 = 0x71, 545 + DBG_CLIENT_BLKID_gdc_one_29 = 0x72, 546 + DBG_CLIENT_BLKID_gdc_one_30 = 0x73, 547 + DBG_CLIENT_BLKID_gdc_one_31 = 0x74, 548 + DBG_CLIENT_BLKID_gdc_one_32 = 0x75, 549 + DBG_CLIENT_BLKID_gdc_one_33 = 0x76, 550 + DBG_CLIENT_BLKID_gdc_one_34 = 0x77, 551 + DBG_CLIENT_BLKID_gdc_one_35 = 0x78, 552 + DBG_CLIENT_BLKID_vceb0_0 = 0x79, 553 + DBG_CLIENT_BLKID_vgt3 = 0x7a, 554 + DBG_CLIENT_BLKID_pc3 = 0x7b, 555 + DBG_CLIENT_BLKID_mcd3 = 0x7c, 556 + DBG_CLIENT_BLKID_uvdu_0 = 0x7d, 557 + DBG_CLIENT_BLKID_uvdu_1 = 0x7e, 558 + DBG_CLIENT_BLKID_uvdu_2 = 0x7f, 559 + DBG_CLIENT_BLKID_uvdu_3 = 0x80, 560 + DBG_CLIENT_BLKID_uvdu_4 = 0x81, 561 + DBG_CLIENT_BLKID_uvdu_5 = 0x82, 562 + DBG_CLIENT_BLKID_uvdu_6 = 0x83, 563 + DBG_CLIENT_BLKID_cb300 = 0x84, 564 + DBG_CLIENT_BLKID_mcd1 = 0x85, 565 + DBG_CLIENT_BLKID_sx00 = 0x86, 566 + DBG_CLIENT_BLKID_uvdc_0 = 0x87, 567 + DBG_CLIENT_BLKID_uvdc_1 = 0x88, 568 + DBG_CLIENT_BLKID_mcc3 = 0x89, 569 + DBG_CLIENT_BLKID_cpg_0 = 0x8a, 570 + DBG_CLIENT_BLKID_cpg_1 = 0x8b, 571 + DBG_CLIENT_BLKID_gck = 0x8c, 572 + DBG_CLIENT_BLKID_mcc1 = 0x8d, 573 + DBG_CLIENT_BLKID_cpf_0 = 0x8e, 574 + DBG_CLIENT_BLKID_cpf_1 = 0x8f, 575 + DBG_CLIENT_BLKID_rlc = 0x90, 576 + DBG_CLIENT_BLKID_grbm = 0x91, 577 + DBG_CLIENT_BLKID_sammsp = 0x92, 578 + DBG_CLIENT_BLKID_dci_pg = 0x93, 579 + DBG_CLIENT_BLKID_dci_0 = 0x94, 580 + DBG_CLIENT_BLKID_dccg0_0 = 0x95, 581 + DBG_CLIENT_BLKID_dccg0_1 = 0x96, 582 + DBG_CLIENT_BLKID_dcfe01_0 = 0x97, 583 + DBG_CLIENT_BLKID_dcfe02_0 = 0x98, 584 + DBG_CLIENT_BLKID_dcfe03_0 = 0x99, 585 + DBG_CLIENT_BLKID_dcfe04_0 = 0x9a, 586 + DBG_CLIENT_BLKID_dcfe05_0 = 0x9b, 587 + DBG_CLIENT_BLKID_dcfe06_0 = 0x9c, 588 + DBG_CLIENT_BLKID_RESERVED_LAST = 0x9d, 589 + } DebugBlockId; 590 + typedef enum DebugBlockId_OLD { 591 + DBG_BLOCK_ID_RESERVED = 0x0, 592 + DBG_BLOCK_ID_DBG = 0x1, 593 + DBG_BLOCK_ID_VMC = 0x2, 594 + DBG_BLOCK_ID_PDMA = 0x3, 595 + DBG_BLOCK_ID_CG = 0x4, 596 + DBG_BLOCK_ID_SRBM = 0x5, 597 + DBG_BLOCK_ID_GRBM = 0x6, 598 + DBG_BLOCK_ID_RLC = 0x7, 599 + DBG_BLOCK_ID_CSC = 0x8, 600 + DBG_BLOCK_ID_SEM = 0x9, 601 + DBG_BLOCK_ID_IH = 0xa, 602 + DBG_BLOCK_ID_SC = 0xb, 603 + DBG_BLOCK_ID_SQ = 0xc, 604 + DBG_BLOCK_ID_AVP = 0xd, 605 + DBG_BLOCK_ID_GMCON = 0xe, 606 + DBG_BLOCK_ID_SMU = 0xf, 607 + DBG_BLOCK_ID_DMA0 = 0x10, 608 + DBG_BLOCK_ID_DMA1 = 0x11, 609 + DBG_BLOCK_ID_SPIM = 0x12, 610 + DBG_BLOCK_ID_GDS = 0x13, 611 + DBG_BLOCK_ID_SPIS = 0x14, 612 + DBG_BLOCK_ID_UNUSED0 = 0x15, 613 + DBG_BLOCK_ID_PA0 = 0x16, 614 + DBG_BLOCK_ID_PA1 = 0x17, 615 + DBG_BLOCK_ID_CP0 = 0x18, 616 + DBG_BLOCK_ID_CP1 = 0x19, 617 + DBG_BLOCK_ID_CP2 = 0x1a, 618 + DBG_BLOCK_ID_UNUSED1 = 0x1b, 619 + DBG_BLOCK_ID_UVDU = 0x1c, 620 + DBG_BLOCK_ID_UVDM = 0x1d, 621 + DBG_BLOCK_ID_VCE = 0x1e, 622 + DBG_BLOCK_ID_UNUSED2 = 0x1f, 623 + DBG_BLOCK_ID_VGT0 = 0x20, 624 + DBG_BLOCK_ID_VGT1 = 0x21, 625 + DBG_BLOCK_ID_IA = 0x22, 626 + DBG_BLOCK_ID_UNUSED3 = 0x23, 627 + DBG_BLOCK_ID_SCT0 = 0x24, 628 + DBG_BLOCK_ID_SCT1 = 0x25, 629 + DBG_BLOCK_ID_SPM0 = 0x26, 630 + DBG_BLOCK_ID_SPM1 = 0x27, 631 + DBG_BLOCK_ID_TCAA = 0x28, 632 + DBG_BLOCK_ID_TCAB = 0x29, 633 + DBG_BLOCK_ID_TCCA = 0x2a, 634 + DBG_BLOCK_ID_TCCB = 0x2b, 635 + DBG_BLOCK_ID_MCC0 = 0x2c, 636 + DBG_BLOCK_ID_MCC1 = 0x2d, 637 + DBG_BLOCK_ID_MCC2 = 0x2e, 638 + DBG_BLOCK_ID_MCC3 = 0x2f, 639 + DBG_BLOCK_ID_SX0 = 0x30, 640 + DBG_BLOCK_ID_SX1 = 0x31, 641 + DBG_BLOCK_ID_SX2 = 0x32, 642 + DBG_BLOCK_ID_SX3 = 0x33, 643 + DBG_BLOCK_ID_UNUSED4 = 0x34, 644 + DBG_BLOCK_ID_UNUSED5 = 0x35, 645 + DBG_BLOCK_ID_UNUSED6 = 0x36, 646 + DBG_BLOCK_ID_UNUSED7 = 0x37, 647 + DBG_BLOCK_ID_PC0 = 0x38, 648 + DBG_BLOCK_ID_PC1 = 0x39, 649 + DBG_BLOCK_ID_UNUSED8 = 0x3a, 650 + DBG_BLOCK_ID_UNUSED9 = 0x3b, 651 + DBG_BLOCK_ID_UNUSED10 = 0x3c, 652 + DBG_BLOCK_ID_UNUSED11 = 0x3d, 653 + DBG_BLOCK_ID_MCB = 0x3e, 654 + DBG_BLOCK_ID_UNUSED12 = 0x3f, 655 + DBG_BLOCK_ID_SCB0 = 0x40, 656 + DBG_BLOCK_ID_SCB1 = 0x41, 657 + DBG_BLOCK_ID_UNUSED13 = 0x42, 658 + DBG_BLOCK_ID_UNUSED14 = 0x43, 659 + DBG_BLOCK_ID_SCF0 = 0x44, 660 + DBG_BLOCK_ID_SCF1 = 0x45, 661 + DBG_BLOCK_ID_UNUSED15 = 0x46, 662 + DBG_BLOCK_ID_UNUSED16 = 0x47, 663 + DBG_BLOCK_ID_BCI0 = 0x48, 664 + DBG_BLOCK_ID_BCI1 = 0x49, 665 + DBG_BLOCK_ID_BCI2 = 0x4a, 666 + DBG_BLOCK_ID_BCI3 = 0x4b, 667 + DBG_BLOCK_ID_UNUSED17 = 0x4c, 668 + DBG_BLOCK_ID_UNUSED18 = 0x4d, 669 + DBG_BLOCK_ID_UNUSED19 = 0x4e, 670 + DBG_BLOCK_ID_UNUSED20 = 0x4f, 671 + DBG_BLOCK_ID_CB00 = 0x50, 672 + DBG_BLOCK_ID_CB01 = 0x51, 673 + DBG_BLOCK_ID_CB02 = 0x52, 674 + DBG_BLOCK_ID_CB03 = 0x53, 675 + DBG_BLOCK_ID_CB04 = 0x54, 676 + DBG_BLOCK_ID_UNUSED21 = 0x55, 677 + DBG_BLOCK_ID_UNUSED22 = 0x56, 678 + DBG_BLOCK_ID_UNUSED23 = 0x57, 679 + DBG_BLOCK_ID_CB10 = 0x58, 680 + DBG_BLOCK_ID_CB11 = 0x59, 681 + DBG_BLOCK_ID_CB12 = 0x5a, 682 + DBG_BLOCK_ID_CB13 = 0x5b, 683 + DBG_BLOCK_ID_CB14 = 0x5c, 684 + DBG_BLOCK_ID_UNUSED24 = 0x5d, 685 + DBG_BLOCK_ID_UNUSED25 = 0x5e, 686 + DBG_BLOCK_ID_UNUSED26 = 0x5f, 687 + DBG_BLOCK_ID_TCP0 = 0x60, 688 + DBG_BLOCK_ID_TCP1 = 0x61, 689 + DBG_BLOCK_ID_TCP2 = 0x62, 690 + DBG_BLOCK_ID_TCP3 = 0x63, 691 + DBG_BLOCK_ID_TCP4 = 0x64, 692 + DBG_BLOCK_ID_TCP5 = 0x65, 693 + DBG_BLOCK_ID_TCP6 = 0x66, 694 + DBG_BLOCK_ID_TCP7 = 0x67, 695 + DBG_BLOCK_ID_TCP8 = 0x68, 696 + DBG_BLOCK_ID_TCP9 = 0x69, 697 + DBG_BLOCK_ID_TCP10 = 0x6a, 698 + DBG_BLOCK_ID_TCP11 = 0x6b, 699 + DBG_BLOCK_ID_TCP12 = 0x6c, 700 + DBG_BLOCK_ID_TCP13 = 0x6d, 701 + DBG_BLOCK_ID_TCP14 = 0x6e, 702 + DBG_BLOCK_ID_TCP15 = 0x6f, 703 + DBG_BLOCK_ID_TCP16 = 0x70, 704 + DBG_BLOCK_ID_TCP17 = 0x71, 705 + DBG_BLOCK_ID_TCP18 = 0x72, 706 + DBG_BLOCK_ID_TCP19 = 0x73, 707 + DBG_BLOCK_ID_TCP20 = 0x74, 708 + DBG_BLOCK_ID_TCP21 = 0x75, 709 + DBG_BLOCK_ID_TCP22 = 0x76, 710 + DBG_BLOCK_ID_TCP23 = 0x77, 711 + DBG_BLOCK_ID_TCP_RESERVED0 = 0x78, 712 + DBG_BLOCK_ID_TCP_RESERVED1 = 0x79, 713 + DBG_BLOCK_ID_TCP_RESERVED2 = 0x7a, 714 + DBG_BLOCK_ID_TCP_RESERVED3 = 0x7b, 715 + DBG_BLOCK_ID_TCP_RESERVED4 = 0x7c, 716 + DBG_BLOCK_ID_TCP_RESERVED5 = 0x7d, 717 + DBG_BLOCK_ID_TCP_RESERVED6 = 0x7e, 718 + DBG_BLOCK_ID_TCP_RESERVED7 = 0x7f, 719 + DBG_BLOCK_ID_DB00 = 0x80, 720 + DBG_BLOCK_ID_DB01 = 0x81, 721 + DBG_BLOCK_ID_DB02 = 0x82, 722 + DBG_BLOCK_ID_DB03 = 0x83, 723 + DBG_BLOCK_ID_DB04 = 0x84, 724 + DBG_BLOCK_ID_UNUSED27 = 0x85, 725 + DBG_BLOCK_ID_UNUSED28 = 0x86, 726 + DBG_BLOCK_ID_UNUSED29 = 0x87, 727 + DBG_BLOCK_ID_DB10 = 0x88, 728 + DBG_BLOCK_ID_DB11 = 0x89, 729 + DBG_BLOCK_ID_DB12 = 0x8a, 730 + DBG_BLOCK_ID_DB13 = 0x8b, 731 + DBG_BLOCK_ID_DB14 = 0x8c, 732 + DBG_BLOCK_ID_UNUSED30 = 0x8d, 733 + DBG_BLOCK_ID_UNUSED31 = 0x8e, 734 + DBG_BLOCK_ID_UNUSED32 = 0x8f, 735 + DBG_BLOCK_ID_TCC0 = 0x90, 736 + DBG_BLOCK_ID_TCC1 = 0x91, 737 + DBG_BLOCK_ID_TCC2 = 0x92, 738 + DBG_BLOCK_ID_TCC3 = 0x93, 739 + DBG_BLOCK_ID_TCC4 = 0x94, 740 + DBG_BLOCK_ID_TCC5 = 0x95, 741 + DBG_BLOCK_ID_TCC6 = 0x96, 742 + DBG_BLOCK_ID_TCC7 = 0x97, 743 + DBG_BLOCK_ID_SPS00 = 0x98, 744 + DBG_BLOCK_ID_SPS01 = 0x99, 745 + DBG_BLOCK_ID_SPS02 = 0x9a, 746 + DBG_BLOCK_ID_SPS10 = 0x9b, 747 + DBG_BLOCK_ID_SPS11 = 0x9c, 748 + DBG_BLOCK_ID_SPS12 = 0x9d, 749 + DBG_BLOCK_ID_UNUSED33 = 0x9e, 750 + DBG_BLOCK_ID_UNUSED34 = 0x9f, 751 + DBG_BLOCK_ID_TA00 = 0xa0, 752 + DBG_BLOCK_ID_TA01 = 0xa1, 753 + DBG_BLOCK_ID_TA02 = 0xa2, 754 + DBG_BLOCK_ID_TA03 = 0xa3, 755 + DBG_BLOCK_ID_TA04 = 0xa4, 756 + DBG_BLOCK_ID_TA05 = 0xa5, 757 + DBG_BLOCK_ID_TA06 = 0xa6, 758 + DBG_BLOCK_ID_TA07 = 0xa7, 759 + DBG_BLOCK_ID_TA08 = 0xa8, 760 + DBG_BLOCK_ID_TA09 = 0xa9, 761 + DBG_BLOCK_ID_TA0A = 0xaa, 762 + DBG_BLOCK_ID_TA0B = 0xab, 763 + DBG_BLOCK_ID_UNUSED35 = 0xac, 764 + DBG_BLOCK_ID_UNUSED36 = 0xad, 765 + DBG_BLOCK_ID_UNUSED37 = 0xae, 766 + DBG_BLOCK_ID_UNUSED38 = 0xaf, 767 + DBG_BLOCK_ID_TA10 = 0xb0, 768 + DBG_BLOCK_ID_TA11 = 0xb1, 769 + DBG_BLOCK_ID_TA12 = 0xb2, 770 + DBG_BLOCK_ID_TA13 = 0xb3, 771 + DBG_BLOCK_ID_TA14 = 0xb4, 772 + DBG_BLOCK_ID_TA15 = 0xb5, 773 + DBG_BLOCK_ID_TA16 = 0xb6, 774 + DBG_BLOCK_ID_TA17 = 0xb7, 775 + DBG_BLOCK_ID_TA18 = 0xb8, 776 + DBG_BLOCK_ID_TA19 = 0xb9, 777 + DBG_BLOCK_ID_TA1A = 0xba, 778 + DBG_BLOCK_ID_TA1B = 0xbb, 779 + DBG_BLOCK_ID_UNUSED39 = 0xbc, 780 + DBG_BLOCK_ID_UNUSED40 = 0xbd, 781 + DBG_BLOCK_ID_UNUSED41 = 0xbe, 782 + DBG_BLOCK_ID_UNUSED42 = 0xbf, 783 + DBG_BLOCK_ID_TD00 = 0xc0, 784 + DBG_BLOCK_ID_TD01 = 0xc1, 785 + DBG_BLOCK_ID_TD02 = 0xc2, 786 + DBG_BLOCK_ID_TD03 = 0xc3, 787 + DBG_BLOCK_ID_TD04 = 0xc4, 788 + DBG_BLOCK_ID_TD05 = 0xc5, 789 + DBG_BLOCK_ID_TD06 = 0xc6, 790 + DBG_BLOCK_ID_TD07 = 0xc7, 791 + DBG_BLOCK_ID_TD08 = 0xc8, 792 + DBG_BLOCK_ID_TD09 = 0xc9, 793 + DBG_BLOCK_ID_TD0A = 0xca, 794 + DBG_BLOCK_ID_TD0B = 0xcb, 795 + DBG_BLOCK_ID_UNUSED43 = 0xcc, 796 + DBG_BLOCK_ID_UNUSED44 = 0xcd, 797 + DBG_BLOCK_ID_UNUSED45 = 0xce, 798 + DBG_BLOCK_ID_UNUSED46 = 0xcf, 799 + DBG_BLOCK_ID_TD10 = 0xd0, 800 + DBG_BLOCK_ID_TD11 = 0xd1, 801 + DBG_BLOCK_ID_TD12 = 0xd2, 802 + DBG_BLOCK_ID_TD13 = 0xd3, 803 + DBG_BLOCK_ID_TD14 = 0xd4, 804 + DBG_BLOCK_ID_TD15 = 0xd5, 805 + DBG_BLOCK_ID_TD16 = 0xd6, 806 + DBG_BLOCK_ID_TD17 = 0xd7, 807 + DBG_BLOCK_ID_TD18 = 0xd8, 808 + DBG_BLOCK_ID_TD19 = 0xd9, 809 + DBG_BLOCK_ID_TD1A = 0xda, 810 + DBG_BLOCK_ID_TD1B = 0xdb, 811 + DBG_BLOCK_ID_UNUSED47 = 0xdc, 812 + DBG_BLOCK_ID_UNUSED48 = 0xdd, 813 + DBG_BLOCK_ID_UNUSED49 = 0xde, 814 + DBG_BLOCK_ID_UNUSED50 = 0xdf, 815 + DBG_BLOCK_ID_MCD0 = 0xe0, 816 + DBG_BLOCK_ID_MCD1 = 0xe1, 817 + DBG_BLOCK_ID_MCD2 = 0xe2, 818 + DBG_BLOCK_ID_MCD3 = 0xe3, 819 + DBG_BLOCK_ID_MCD4 = 0xe4, 820 + DBG_BLOCK_ID_MCD5 = 0xe5, 821 + DBG_BLOCK_ID_UNUSED51 = 0xe6, 822 + DBG_BLOCK_ID_UNUSED52 = 0xe7, 823 + } DebugBlockId_OLD; 824 + typedef enum DebugBlockId_BY2 { 825 + DBG_BLOCK_ID_RESERVED_BY2 = 0x0, 826 + DBG_BLOCK_ID_VMC_BY2 = 0x1, 827 + DBG_BLOCK_ID_CG_BY2 = 0x2, 828 + DBG_BLOCK_ID_GRBM_BY2 = 0x3, 829 + DBG_BLOCK_ID_CSC_BY2 = 0x4, 830 + DBG_BLOCK_ID_IH_BY2 = 0x5, 831 + DBG_BLOCK_ID_SQ_BY2 = 0x6, 832 + DBG_BLOCK_ID_GMCON_BY2 = 0x7, 833 + DBG_BLOCK_ID_DMA0_BY2 = 0x8, 834 + DBG_BLOCK_ID_SPIM_BY2 = 0x9, 835 + DBG_BLOCK_ID_SPIS_BY2 = 0xa, 836 + DBG_BLOCK_ID_PA0_BY2 = 0xb, 837 + DBG_BLOCK_ID_CP0_BY2 = 0xc, 838 + DBG_BLOCK_ID_CP2_BY2 = 0xd, 839 + DBG_BLOCK_ID_UVDU_BY2 = 0xe, 840 + DBG_BLOCK_ID_VCE_BY2 = 0xf, 841 + DBG_BLOCK_ID_VGT0_BY2 = 0x10, 842 + DBG_BLOCK_ID_IA_BY2 = 0x11, 843 + DBG_BLOCK_ID_SCT0_BY2 = 0x12, 844 + DBG_BLOCK_ID_SPM0_BY2 = 0x13, 845 + DBG_BLOCK_ID_TCAA_BY2 = 0x14, 846 + DBG_BLOCK_ID_TCCA_BY2 = 0x15, 847 + DBG_BLOCK_ID_MCC0_BY2 = 0x16, 848 + DBG_BLOCK_ID_MCC2_BY2 = 0x17, 849 + DBG_BLOCK_ID_SX0_BY2 = 0x18, 850 + DBG_BLOCK_ID_SX2_BY2 = 0x19, 851 + DBG_BLOCK_ID_UNUSED4_BY2 = 0x1a, 852 + DBG_BLOCK_ID_UNUSED6_BY2 = 0x1b, 853 + DBG_BLOCK_ID_PC0_BY2 = 0x1c, 854 + DBG_BLOCK_ID_UNUSED8_BY2 = 0x1d, 855 + DBG_BLOCK_ID_UNUSED10_BY2 = 0x1e, 856 + DBG_BLOCK_ID_MCB_BY2 = 0x1f, 857 + DBG_BLOCK_ID_SCB0_BY2 = 0x20, 858 + DBG_BLOCK_ID_UNUSED13_BY2 = 0x21, 859 + DBG_BLOCK_ID_SCF0_BY2 = 0x22, 860 + DBG_BLOCK_ID_UNUSED15_BY2 = 0x23, 861 + DBG_BLOCK_ID_BCI0_BY2 = 0x24, 862 + DBG_BLOCK_ID_BCI2_BY2 = 0x25, 863 + DBG_BLOCK_ID_UNUSED17_BY2 = 0x26, 864 + DBG_BLOCK_ID_UNUSED19_BY2 = 0x27, 865 + DBG_BLOCK_ID_CB00_BY2 = 0x28, 866 + DBG_BLOCK_ID_CB02_BY2 = 0x29, 867 + DBG_BLOCK_ID_CB04_BY2 = 0x2a, 868 + DBG_BLOCK_ID_UNUSED22_BY2 = 0x2b, 869 + DBG_BLOCK_ID_CB10_BY2 = 0x2c, 870 + DBG_BLOCK_ID_CB12_BY2 = 0x2d, 871 + DBG_BLOCK_ID_CB14_BY2 = 0x2e, 872 + DBG_BLOCK_ID_UNUSED25_BY2 = 0x2f, 873 + DBG_BLOCK_ID_TCP0_BY2 = 0x30, 874 + DBG_BLOCK_ID_TCP2_BY2 = 0x31, 875 + DBG_BLOCK_ID_TCP4_BY2 = 0x32, 876 + DBG_BLOCK_ID_TCP6_BY2 = 0x33, 877 + DBG_BLOCK_ID_TCP8_BY2 = 0x34, 878 + DBG_BLOCK_ID_TCP10_BY2 = 0x35, 879 + DBG_BLOCK_ID_TCP12_BY2 = 0x36, 880 + DBG_BLOCK_ID_TCP14_BY2 = 0x37, 881 + DBG_BLOCK_ID_TCP16_BY2 = 0x38, 882 + DBG_BLOCK_ID_TCP18_BY2 = 0x39, 883 + DBG_BLOCK_ID_TCP20_BY2 = 0x3a, 884 + DBG_BLOCK_ID_TCP22_BY2 = 0x3b, 885 + DBG_BLOCK_ID_TCP_RESERVED0_BY2 = 0x3c, 886 + DBG_BLOCK_ID_TCP_RESERVED2_BY2 = 0x3d, 887 + DBG_BLOCK_ID_TCP_RESERVED4_BY2 = 0x3e, 888 + DBG_BLOCK_ID_TCP_RESERVED6_BY2 = 0x3f, 889 + DBG_BLOCK_ID_DB00_BY2 = 0x40, 890 + DBG_BLOCK_ID_DB02_BY2 = 0x41, 891 + DBG_BLOCK_ID_DB04_BY2 = 0x42, 892 + DBG_BLOCK_ID_UNUSED28_BY2 = 0x43, 893 + DBG_BLOCK_ID_DB10_BY2 = 0x44, 894 + DBG_BLOCK_ID_DB12_BY2 = 0x45, 895 + DBG_BLOCK_ID_DB14_BY2 = 0x46, 896 + DBG_BLOCK_ID_UNUSED31_BY2 = 0x47, 897 + DBG_BLOCK_ID_TCC0_BY2 = 0x48, 898 + DBG_BLOCK_ID_TCC2_BY2 = 0x49, 899 + DBG_BLOCK_ID_TCC4_BY2 = 0x4a, 900 + DBG_BLOCK_ID_TCC6_BY2 = 0x4b, 901 + DBG_BLOCK_ID_SPS00_BY2 = 0x4c, 902 + DBG_BLOCK_ID_SPS02_BY2 = 0x4d, 903 + DBG_BLOCK_ID_SPS11_BY2 = 0x4e, 904 + DBG_BLOCK_ID_UNUSED33_BY2 = 0x4f, 905 + DBG_BLOCK_ID_TA00_BY2 = 0x50, 906 + DBG_BLOCK_ID_TA02_BY2 = 0x51, 907 + DBG_BLOCK_ID_TA04_BY2 = 0x52, 908 + DBG_BLOCK_ID_TA06_BY2 = 0x53, 909 + DBG_BLOCK_ID_TA08_BY2 = 0x54, 910 + DBG_BLOCK_ID_TA0A_BY2 = 0x55, 911 + DBG_BLOCK_ID_UNUSED35_BY2 = 0x56, 912 + DBG_BLOCK_ID_UNUSED37_BY2 = 0x57, 913 + DBG_BLOCK_ID_TA10_BY2 = 0x58, 914 + DBG_BLOCK_ID_TA12_BY2 = 0x59, 915 + DBG_BLOCK_ID_TA14_BY2 = 0x5a, 916 + DBG_BLOCK_ID_TA16_BY2 = 0x5b, 917 + DBG_BLOCK_ID_TA18_BY2 = 0x5c, 918 + DBG_BLOCK_ID_TA1A_BY2 = 0x5d, 919 + DBG_BLOCK_ID_UNUSED39_BY2 = 0x5e, 920 + DBG_BLOCK_ID_UNUSED41_BY2 = 0x5f, 921 + DBG_BLOCK_ID_TD00_BY2 = 0x60, 922 + DBG_BLOCK_ID_TD02_BY2 = 0x61, 923 + DBG_BLOCK_ID_TD04_BY2 = 0x62, 924 + DBG_BLOCK_ID_TD06_BY2 = 0x63, 925 + DBG_BLOCK_ID_TD08_BY2 = 0x64, 926 + DBG_BLOCK_ID_TD0A_BY2 = 0x65, 927 + DBG_BLOCK_ID_UNUSED43_BY2 = 0x66, 928 + DBG_BLOCK_ID_UNUSED45_BY2 = 0x67, 929 + DBG_BLOCK_ID_TD10_BY2 = 0x68, 930 + DBG_BLOCK_ID_TD12_BY2 = 0x69, 931 + DBG_BLOCK_ID_TD14_BY2 = 0x6a, 932 + DBG_BLOCK_ID_TD16_BY2 = 0x6b, 933 + DBG_BLOCK_ID_TD18_BY2 = 0x6c, 934 + DBG_BLOCK_ID_TD1A_BY2 = 0x6d, 935 + DBG_BLOCK_ID_UNUSED47_BY2 = 0x6e, 936 + DBG_BLOCK_ID_UNUSED49_BY2 = 0x6f, 937 + DBG_BLOCK_ID_MCD0_BY2 = 0x70, 938 + DBG_BLOCK_ID_MCD2_BY2 = 0x71, 939 + DBG_BLOCK_ID_MCD4_BY2 = 0x72, 940 + DBG_BLOCK_ID_UNUSED51_BY2 = 0x73, 941 + } DebugBlockId_BY2; 942 + typedef enum DebugBlockId_BY4 { 943 + DBG_BLOCK_ID_RESERVED_BY4 = 0x0, 944 + DBG_BLOCK_ID_CG_BY4 = 0x1, 945 + DBG_BLOCK_ID_CSC_BY4 = 0x2, 946 + DBG_BLOCK_ID_SQ_BY4 = 0x3, 947 + DBG_BLOCK_ID_DMA0_BY4 = 0x4, 948 + DBG_BLOCK_ID_SPIS_BY4 = 0x5, 949 + DBG_BLOCK_ID_CP0_BY4 = 0x6, 950 + DBG_BLOCK_ID_UVDU_BY4 = 0x7, 951 + DBG_BLOCK_ID_VGT0_BY4 = 0x8, 952 + DBG_BLOCK_ID_SCT0_BY4 = 0x9, 953 + DBG_BLOCK_ID_TCAA_BY4 = 0xa, 954 + DBG_BLOCK_ID_MCC0_BY4 = 0xb, 955 + DBG_BLOCK_ID_SX0_BY4 = 0xc, 956 + DBG_BLOCK_ID_UNUSED4_BY4 = 0xd, 957 + DBG_BLOCK_ID_PC0_BY4 = 0xe, 958 + DBG_BLOCK_ID_UNUSED10_BY4 = 0xf, 959 + DBG_BLOCK_ID_SCB0_BY4 = 0x10, 960 + DBG_BLOCK_ID_SCF0_BY4 = 0x11, 961 + DBG_BLOCK_ID_BCI0_BY4 = 0x12, 962 + DBG_BLOCK_ID_UNUSED17_BY4 = 0x13, 963 + DBG_BLOCK_ID_CB00_BY4 = 0x14, 964 + DBG_BLOCK_ID_CB04_BY4 = 0x15, 965 + DBG_BLOCK_ID_CB10_BY4 = 0x16, 966 + DBG_BLOCK_ID_CB14_BY4 = 0x17, 967 + DBG_BLOCK_ID_TCP0_BY4 = 0x18, 968 + DBG_BLOCK_ID_TCP4_BY4 = 0x19, 969 + DBG_BLOCK_ID_TCP8_BY4 = 0x1a, 970 + DBG_BLOCK_ID_TCP12_BY4 = 0x1b, 971 + DBG_BLOCK_ID_TCP16_BY4 = 0x1c, 972 + DBG_BLOCK_ID_TCP20_BY4 = 0x1d, 973 + DBG_BLOCK_ID_TCP_RESERVED0_BY4 = 0x1e, 974 + DBG_BLOCK_ID_TCP_RESERVED4_BY4 = 0x1f, 975 + DBG_BLOCK_ID_DB_BY4 = 0x20, 976 + DBG_BLOCK_ID_DB04_BY4 = 0x21, 977 + DBG_BLOCK_ID_DB10_BY4 = 0x22, 978 + DBG_BLOCK_ID_DB14_BY4 = 0x23, 979 + DBG_BLOCK_ID_TCC0_BY4 = 0x24, 980 + DBG_BLOCK_ID_TCC4_BY4 = 0x25, 981 + DBG_BLOCK_ID_SPS00_BY4 = 0x26, 982 + DBG_BLOCK_ID_SPS11_BY4 = 0x27, 983 + DBG_BLOCK_ID_TA00_BY4 = 0x28, 984 + DBG_BLOCK_ID_TA04_BY4 = 0x29, 985 + DBG_BLOCK_ID_TA08_BY4 = 0x2a, 986 + DBG_BLOCK_ID_UNUSED35_BY4 = 0x2b, 987 + DBG_BLOCK_ID_TA10_BY4 = 0x2c, 988 + DBG_BLOCK_ID_TA14_BY4 = 0x2d, 989 + DBG_BLOCK_ID_TA18_BY4 = 0x2e, 990 + DBG_BLOCK_ID_UNUSED39_BY4 = 0x2f, 991 + DBG_BLOCK_ID_TD00_BY4 = 0x30, 992 + DBG_BLOCK_ID_TD04_BY4 = 0x31, 993 + DBG_BLOCK_ID_TD08_BY4 = 0x32, 994 + DBG_BLOCK_ID_UNUSED43_BY4 = 0x33, 995 + DBG_BLOCK_ID_TD10_BY4 = 0x34, 996 + DBG_BLOCK_ID_TD14_BY4 = 0x35, 997 + DBG_BLOCK_ID_TD18_BY4 = 0x36, 998 + DBG_BLOCK_ID_UNUSED47_BY4 = 0x37, 999 + DBG_BLOCK_ID_MCD0_BY4 = 0x38, 1000 + DBG_BLOCK_ID_MCD4_BY4 = 0x39, 1001 + } DebugBlockId_BY4; 1002 + typedef enum DebugBlockId_BY8 { 1003 + DBG_BLOCK_ID_RESERVED_BY8 = 0x0, 1004 + DBG_BLOCK_ID_CSC_BY8 = 0x1, 1005 + DBG_BLOCK_ID_DMA0_BY8 = 0x2, 1006 + DBG_BLOCK_ID_CP0_BY8 = 0x3, 1007 + DBG_BLOCK_ID_VGT0_BY8 = 0x4, 1008 + DBG_BLOCK_ID_TCAA_BY8 = 0x5, 1009 + DBG_BLOCK_ID_SX0_BY8 = 0x6, 1010 + DBG_BLOCK_ID_PC0_BY8 = 0x7, 1011 + DBG_BLOCK_ID_SCB0_BY8 = 0x8, 1012 + DBG_BLOCK_ID_BCI0_BY8 = 0x9, 1013 + DBG_BLOCK_ID_CB00_BY8 = 0xa, 1014 + DBG_BLOCK_ID_CB10_BY8 = 0xb, 1015 + DBG_BLOCK_ID_TCP0_BY8 = 0xc, 1016 + DBG_BLOCK_ID_TCP8_BY8 = 0xd, 1017 + DBG_BLOCK_ID_TCP16_BY8 = 0xe, 1018 + DBG_BLOCK_ID_TCP_RESERVED0_BY8 = 0xf, 1019 + DBG_BLOCK_ID_DB00_BY8 = 0x10, 1020 + DBG_BLOCK_ID_DB10_BY8 = 0x11, 1021 + DBG_BLOCK_ID_TCC0_BY8 = 0x12, 1022 + DBG_BLOCK_ID_SPS00_BY8 = 0x13, 1023 + DBG_BLOCK_ID_TA00_BY8 = 0x14, 1024 + DBG_BLOCK_ID_TA08_BY8 = 0x15, 1025 + DBG_BLOCK_ID_TA10_BY8 = 0x16, 1026 + DBG_BLOCK_ID_TA18_BY8 = 0x17, 1027 + DBG_BLOCK_ID_TD00_BY8 = 0x18, 1028 + DBG_BLOCK_ID_TD08_BY8 = 0x19, 1029 + DBG_BLOCK_ID_TD10_BY8 = 0x1a, 1030 + DBG_BLOCK_ID_TD18_BY8 = 0x1b, 1031 + DBG_BLOCK_ID_MCD0_BY8 = 0x1c, 1032 + } DebugBlockId_BY8; 1033 + typedef enum DebugBlockId_BY16 { 1034 + DBG_BLOCK_ID_RESERVED_BY16 = 0x0, 1035 + DBG_BLOCK_ID_DMA0_BY16 = 0x1, 1036 + DBG_BLOCK_ID_VGT0_BY16 = 0x2, 1037 + DBG_BLOCK_ID_SX0_BY16 = 0x3, 1038 + DBG_BLOCK_ID_SCB0_BY16 = 0x4, 1039 + DBG_BLOCK_ID_CB00_BY16 = 0x5, 1040 + DBG_BLOCK_ID_TCP0_BY16 = 0x6, 1041 + DBG_BLOCK_ID_TCP16_BY16 = 0x7, 1042 + DBG_BLOCK_ID_DB00_BY16 = 0x8, 1043 + DBG_BLOCK_ID_TCC0_BY16 = 0x9, 1044 + DBG_BLOCK_ID_TA00_BY16 = 0xa, 1045 + DBG_BLOCK_ID_TA10_BY16 = 0xb, 1046 + DBG_BLOCK_ID_TD00_BY16 = 0xc, 1047 + DBG_BLOCK_ID_TD10_BY16 = 0xd, 1048 + DBG_BLOCK_ID_MCD0_BY16 = 0xe, 1049 + } DebugBlockId_BY16; 1050 + typedef enum ColorTransform { 1051 + DCC_CT_AUTO = 0x0, 1052 + DCC_CT_NONE = 0x1, 1053 + ABGR_TO_A_BG_G_RB = 0x2, 1054 + BGRA_TO_BG_G_RB_A = 0x3, 1055 + } ColorTransform; 1056 + typedef enum CompareRef { 1057 + REF_NEVER = 0x0, 1058 + REF_LESS = 0x1, 1059 + REF_EQUAL = 0x2, 1060 + REF_LEQUAL = 0x3, 1061 + REF_GREATER = 0x4, 1062 + REF_NOTEQUAL = 0x5, 1063 + REF_GEQUAL = 0x6, 1064 + REF_ALWAYS = 0x7, 1065 + } CompareRef; 1066 + typedef enum ReadSize { 1067 + READ_256_BITS = 0x0, 1068 + READ_512_BITS = 0x1, 1069 + } ReadSize; 1070 + typedef enum DepthFormat { 1071 + DEPTH_INVALID = 0x0, 1072 + DEPTH_16 = 0x1, 1073 + DEPTH_X8_24 = 0x2, 1074 + DEPTH_8_24 = 0x3, 1075 + DEPTH_X8_24_FLOAT = 0x4, 1076 + DEPTH_8_24_FLOAT = 0x5, 1077 + DEPTH_32_FLOAT = 0x6, 1078 + DEPTH_X24_8_32_FLOAT = 0x7, 1079 + } DepthFormat; 1080 + typedef enum ZFormat { 1081 + Z_INVALID = 0x0, 1082 + Z_16 = 0x1, 1083 + Z_24 = 0x2, 1084 + Z_32_FLOAT = 0x3, 1085 + } ZFormat; 1086 + typedef enum StencilFormat { 1087 + STENCIL_INVALID = 0x0, 1088 + STENCIL_8 = 0x1, 1089 + } StencilFormat; 1090 + typedef enum CmaskMode { 1091 + CMASK_CLEAR_NONE = 0x0, 1092 + CMASK_CLEAR_ONE = 0x1, 1093 + CMASK_CLEAR_ALL = 0x2, 1094 + CMASK_ANY_EXPANDED = 0x3, 1095 + CMASK_ALPHA0_FRAG1 = 0x4, 1096 + CMASK_ALPHA0_FRAG2 = 0x5, 1097 + CMASK_ALPHA0_FRAG4 = 0x6, 1098 + CMASK_ALPHA0_FRAGS = 0x7, 1099 + CMASK_ALPHA1_FRAG1 = 0x8, 1100 + CMASK_ALPHA1_FRAG2 = 0x9, 1101 + CMASK_ALPHA1_FRAG4 = 0xa, 1102 + CMASK_ALPHA1_FRAGS = 0xb, 1103 + CMASK_ALPHAX_FRAG1 = 0xc, 1104 + CMASK_ALPHAX_FRAG2 = 0xd, 1105 + CMASK_ALPHAX_FRAG4 = 0xe, 1106 + CMASK_ALPHAX_FRAGS = 0xf, 1107 + } CmaskMode; 1108 + typedef enum QuadExportFormat { 1109 + EXPORT_UNUSED = 0x0, 1110 + EXPORT_32_R = 0x1, 1111 + EXPORT_32_GR = 0x2, 1112 + EXPORT_32_AR = 0x3, 1113 + EXPORT_FP16_ABGR = 0x4, 1114 + EXPORT_UNSIGNED16_ABGR = 0x5, 1115 + EXPORT_SIGNED16_ABGR = 0x6, 1116 + EXPORT_32_ABGR = 0x7, 1117 + } QuadExportFormat; 1118 + typedef enum QuadExportFormatOld { 1119 + EXPORT_4P_32BPC_ABGR = 0x0, 1120 + EXPORT_4P_16BPC_ABGR = 0x1, 1121 + EXPORT_4P_32BPC_GR = 0x2, 1122 + EXPORT_4P_32BPC_AR = 0x3, 1123 + EXPORT_2P_32BPC_ABGR = 0x4, 1124 + EXPORT_8P_32BPC_R = 0x5, 1125 + } QuadExportFormatOld; 1126 + typedef enum ColorFormat { 1127 + COLOR_INVALID = 0x0, 1128 + COLOR_8 = 0x1, 1129 + COLOR_16 = 0x2, 1130 + COLOR_8_8 = 0x3, 1131 + COLOR_32 = 0x4, 1132 + COLOR_16_16 = 0x5, 1133 + COLOR_10_11_11 = 0x6, 1134 + COLOR_11_11_10 = 0x7, 1135 + COLOR_10_10_10_2 = 0x8, 1136 + COLOR_2_10_10_10 = 0x9, 1137 + COLOR_8_8_8_8 = 0xa, 1138 + COLOR_32_32 = 0xb, 1139 + COLOR_16_16_16_16 = 0xc, 1140 + COLOR_RESERVED_13 = 0xd, 1141 + COLOR_32_32_32_32 = 0xe, 1142 + COLOR_RESERVED_15 = 0xf, 1143 + COLOR_5_6_5 = 0x10, 1144 + COLOR_1_5_5_5 = 0x11, 1145 + COLOR_5_5_5_1 = 0x12, 1146 + COLOR_4_4_4_4 = 0x13, 1147 + COLOR_8_24 = 0x14, 1148 + COLOR_24_8 = 0x15, 1149 + COLOR_X24_8_32_FLOAT = 0x16, 1150 + COLOR_RESERVED_23 = 0x17, 1151 + } ColorFormat; 1152 + typedef enum SurfaceFormat { 1153 + FMT_INVALID = 0x0, 1154 + FMT_8 = 0x1, 1155 + FMT_16 = 0x2, 1156 + FMT_8_8 = 0x3, 1157 + FMT_32 = 0x4, 1158 + FMT_16_16 = 0x5, 1159 + FMT_10_11_11 = 0x6, 1160 + FMT_11_11_10 = 0x7, 1161 + FMT_10_10_10_2 = 0x8, 1162 + FMT_2_10_10_10 = 0x9, 1163 + FMT_8_8_8_8 = 0xa, 1164 + FMT_32_32 = 0xb, 1165 + FMT_16_16_16_16 = 0xc, 1166 + FMT_32_32_32 = 0xd, 1167 + FMT_32_32_32_32 = 0xe, 1168 + FMT_RESERVED_4 = 0xf, 1169 + FMT_5_6_5 = 0x10, 1170 + FMT_1_5_5_5 = 0x11, 1171 + FMT_5_5_5_1 = 0x12, 1172 + FMT_4_4_4_4 = 0x13, 1173 + FMT_8_24 = 0x14, 1174 + FMT_24_8 = 0x15, 1175 + FMT_X24_8_32_FLOAT = 0x16, 1176 + FMT_RESERVED_33 = 0x17, 1177 + FMT_11_11_10_FLOAT = 0x18, 1178 + FMT_16_FLOAT = 0x19, 1179 + FMT_32_FLOAT = 0x1a, 1180 + FMT_16_16_FLOAT = 0x1b, 1181 + FMT_8_24_FLOAT = 0x1c, 1182 + FMT_24_8_FLOAT = 0x1d, 1183 + FMT_32_32_FLOAT = 0x1e, 1184 + FMT_10_11_11_FLOAT = 0x1f, 1185 + FMT_16_16_16_16_FLOAT = 0x20, 1186 + FMT_3_3_2 = 0x21, 1187 + FMT_6_5_5 = 0x22, 1188 + FMT_32_32_32_32_FLOAT = 0x23, 1189 + FMT_RESERVED_36 = 0x24, 1190 + FMT_1 = 0x25, 1191 + FMT_1_REVERSED = 0x26, 1192 + FMT_GB_GR = 0x27, 1193 + FMT_BG_RG = 0x28, 1194 + FMT_32_AS_8 = 0x29, 1195 + FMT_32_AS_8_8 = 0x2a, 1196 + FMT_5_9_9_9_SHAREDEXP = 0x2b, 1197 + FMT_8_8_8 = 0x2c, 1198 + FMT_16_16_16 = 0x2d, 1199 + FMT_16_16_16_FLOAT = 0x2e, 1200 + FMT_4_4 = 0x2f, 1201 + FMT_32_32_32_FLOAT = 0x30, 1202 + FMT_BC1 = 0x31, 1203 + FMT_BC2 = 0x32, 1204 + FMT_BC3 = 0x33, 1205 + FMT_BC4 = 0x34, 1206 + FMT_BC5 = 0x35, 1207 + FMT_BC6 = 0x36, 1208 + FMT_BC7 = 0x37, 1209 + FMT_32_AS_32_32_32_32 = 0x38, 1210 + FMT_APC3 = 0x39, 1211 + FMT_APC4 = 0x3a, 1212 + FMT_APC5 = 0x3b, 1213 + FMT_APC6 = 0x3c, 1214 + FMT_APC7 = 0x3d, 1215 + FMT_CTX1 = 0x3e, 1216 + FMT_RESERVED_63 = 0x3f, 1217 + } SurfaceFormat; 1218 + typedef enum BUF_DATA_FORMAT { 1219 + BUF_DATA_FORMAT_INVALID = 0x0, 1220 + BUF_DATA_FORMAT_8 = 0x1, 1221 + BUF_DATA_FORMAT_16 = 0x2, 1222 + BUF_DATA_FORMAT_8_8 = 0x3, 1223 + BUF_DATA_FORMAT_32 = 0x4, 1224 + BUF_DATA_FORMAT_16_16 = 0x5, 1225 + BUF_DATA_FORMAT_10_11_11 = 0x6, 1226 + BUF_DATA_FORMAT_11_11_10 = 0x7, 1227 + BUF_DATA_FORMAT_10_10_10_2 = 0x8, 1228 + BUF_DATA_FORMAT_2_10_10_10 = 0x9, 1229 + BUF_DATA_FORMAT_8_8_8_8 = 0xa, 1230 + BUF_DATA_FORMAT_32_32 = 0xb, 1231 + BUF_DATA_FORMAT_16_16_16_16 = 0xc, 1232 + BUF_DATA_FORMAT_32_32_32 = 0xd, 1233 + BUF_DATA_FORMAT_32_32_32_32 = 0xe, 1234 + BUF_DATA_FORMAT_RESERVED_15 = 0xf, 1235 + } BUF_DATA_FORMAT; 1236 + typedef enum IMG_DATA_FORMAT { 1237 + IMG_DATA_FORMAT_INVALID = 0x0, 1238 + IMG_DATA_FORMAT_8 = 0x1, 1239 + IMG_DATA_FORMAT_16 = 0x2, 1240 + IMG_DATA_FORMAT_8_8 = 0x3, 1241 + IMG_DATA_FORMAT_32 = 0x4, 1242 + IMG_DATA_FORMAT_16_16 = 0x5, 1243 + IMG_DATA_FORMAT_10_11_11 = 0x6, 1244 + IMG_DATA_FORMAT_11_11_10 = 0x7, 1245 + IMG_DATA_FORMAT_10_10_10_2 = 0x8, 1246 + IMG_DATA_FORMAT_2_10_10_10 = 0x9, 1247 + IMG_DATA_FORMAT_8_8_8_8 = 0xa, 1248 + IMG_DATA_FORMAT_32_32 = 0xb, 1249 + IMG_DATA_FORMAT_16_16_16_16 = 0xc, 1250 + IMG_DATA_FORMAT_32_32_32 = 0xd, 1251 + IMG_DATA_FORMAT_32_32_32_32 = 0xe, 1252 + IMG_DATA_FORMAT_RESERVED_15 = 0xf, 1253 + IMG_DATA_FORMAT_5_6_5 = 0x10, 1254 + IMG_DATA_FORMAT_1_5_5_5 = 0x11, 1255 + IMG_DATA_FORMAT_5_5_5_1 = 0x12, 1256 + IMG_DATA_FORMAT_4_4_4_4 = 0x13, 1257 + IMG_DATA_FORMAT_8_24 = 0x14, 1258 + IMG_DATA_FORMAT_24_8 = 0x15, 1259 + IMG_DATA_FORMAT_X24_8_32 = 0x16, 1260 + IMG_DATA_FORMAT_RESERVED_23 = 0x17, 1261 + IMG_DATA_FORMAT_RESERVED_24 = 0x18, 1262 + IMG_DATA_FORMAT_RESERVED_25 = 0x19, 1263 + IMG_DATA_FORMAT_RESERVED_26 = 0x1a, 1264 + IMG_DATA_FORMAT_RESERVED_27 = 0x1b, 1265 + IMG_DATA_FORMAT_RESERVED_28 = 0x1c, 1266 + IMG_DATA_FORMAT_RESERVED_29 = 0x1d, 1267 + IMG_DATA_FORMAT_RESERVED_30 = 0x1e, 1268 + IMG_DATA_FORMAT_RESERVED_31 = 0x1f, 1269 + IMG_DATA_FORMAT_GB_GR = 0x20, 1270 + IMG_DATA_FORMAT_BG_RG = 0x21, 1271 + IMG_DATA_FORMAT_5_9_9_9 = 0x22, 1272 + IMG_DATA_FORMAT_BC1 = 0x23, 1273 + IMG_DATA_FORMAT_BC2 = 0x24, 1274 + IMG_DATA_FORMAT_BC3 = 0x25, 1275 + IMG_DATA_FORMAT_BC4 = 0x26, 1276 + IMG_DATA_FORMAT_BC5 = 0x27, 1277 + IMG_DATA_FORMAT_BC6 = 0x28, 1278 + IMG_DATA_FORMAT_BC7 = 0x29, 1279 + IMG_DATA_FORMAT_RESERVED_42 = 0x2a, 1280 + IMG_DATA_FORMAT_RESERVED_43 = 0x2b, 1281 + IMG_DATA_FORMAT_FMASK8_S2_F1 = 0x2c, 1282 + IMG_DATA_FORMAT_FMASK8_S4_F1 = 0x2d, 1283 + IMG_DATA_FORMAT_FMASK8_S8_F1 = 0x2e, 1284 + IMG_DATA_FORMAT_FMASK8_S2_F2 = 0x2f, 1285 + IMG_DATA_FORMAT_FMASK8_S4_F2 = 0x30, 1286 + IMG_DATA_FORMAT_FMASK8_S4_F4 = 0x31, 1287 + IMG_DATA_FORMAT_FMASK16_S16_F1 = 0x32, 1288 + IMG_DATA_FORMAT_FMASK16_S8_F2 = 0x33, 1289 + IMG_DATA_FORMAT_FMASK32_S16_F2 = 0x34, 1290 + IMG_DATA_FORMAT_FMASK32_S8_F4 = 0x35, 1291 + IMG_DATA_FORMAT_FMASK32_S8_F8 = 0x36, 1292 + IMG_DATA_FORMAT_FMASK64_S16_F4 = 0x37, 1293 + IMG_DATA_FORMAT_FMASK64_S16_F8 = 0x38, 1294 + IMG_DATA_FORMAT_4_4 = 0x39, 1295 + IMG_DATA_FORMAT_6_5_5 = 0x3a, 1296 + IMG_DATA_FORMAT_1 = 0x3b, 1297 + IMG_DATA_FORMAT_1_REVERSED = 0x3c, 1298 + IMG_DATA_FORMAT_32_AS_8 = 0x3d, 1299 + IMG_DATA_FORMAT_32_AS_8_8 = 0x3e, 1300 + IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x3f, 1301 + } IMG_DATA_FORMAT; 1302 + typedef enum BUF_NUM_FORMAT { 1303 + BUF_NUM_FORMAT_UNORM = 0x0, 1304 + BUF_NUM_FORMAT_SNORM = 0x1, 1305 + BUF_NUM_FORMAT_USCALED = 0x2, 1306 + BUF_NUM_FORMAT_SSCALED = 0x3, 1307 + BUF_NUM_FORMAT_UINT = 0x4, 1308 + BUF_NUM_FORMAT_SINT = 0x5, 1309 + BUF_NUM_FORMAT_RESERVED_6 = 0x6, 1310 + BUF_NUM_FORMAT_FLOAT = 0x7, 1311 + } BUF_NUM_FORMAT; 1312 + typedef enum IMG_NUM_FORMAT { 1313 + IMG_NUM_FORMAT_UNORM = 0x0, 1314 + IMG_NUM_FORMAT_SNORM = 0x1, 1315 + IMG_NUM_FORMAT_USCALED = 0x2, 1316 + IMG_NUM_FORMAT_SSCALED = 0x3, 1317 + IMG_NUM_FORMAT_UINT = 0x4, 1318 + IMG_NUM_FORMAT_SINT = 0x5, 1319 + IMG_NUM_FORMAT_RESERVED_6 = 0x6, 1320 + IMG_NUM_FORMAT_FLOAT = 0x7, 1321 + IMG_NUM_FORMAT_RESERVED_8 = 0x8, 1322 + IMG_NUM_FORMAT_SRGB = 0x9, 1323 + IMG_NUM_FORMAT_RESERVED_10 = 0xa, 1324 + IMG_NUM_FORMAT_RESERVED_11 = 0xb, 1325 + IMG_NUM_FORMAT_RESERVED_12 = 0xc, 1326 + IMG_NUM_FORMAT_RESERVED_13 = 0xd, 1327 + IMG_NUM_FORMAT_RESERVED_14 = 0xe, 1328 + IMG_NUM_FORMAT_RESERVED_15 = 0xf, 1329 + } IMG_NUM_FORMAT; 1330 + typedef enum TileType { 1331 + ARRAY_COLOR_TILE = 0x0, 1332 + ARRAY_DEPTH_TILE = 0x1, 1333 + } TileType; 1334 + typedef enum NonDispTilingOrder { 1335 + ADDR_SURF_MICRO_TILING_DISPLAY = 0x0, 1336 + ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1, 1337 + } NonDispTilingOrder; 1338 + typedef enum MicroTileMode { 1339 + ADDR_SURF_DISPLAY_MICRO_TILING = 0x0, 1340 + ADDR_SURF_THIN_MICRO_TILING = 0x1, 1341 + ADDR_SURF_DEPTH_MICRO_TILING = 0x2, 1342 + ADDR_SURF_ROTATED_MICRO_TILING = 0x3, 1343 + ADDR_SURF_THICK_MICRO_TILING = 0x4, 1344 + } MicroTileMode; 1345 + typedef enum TileSplit { 1346 + ADDR_SURF_TILE_SPLIT_64B = 0x0, 1347 + ADDR_SURF_TILE_SPLIT_128B = 0x1, 1348 + ADDR_SURF_TILE_SPLIT_256B = 0x2, 1349 + ADDR_SURF_TILE_SPLIT_512B = 0x3, 1350 + ADDR_SURF_TILE_SPLIT_1KB = 0x4, 1351 + ADDR_SURF_TILE_SPLIT_2KB = 0x5, 1352 + ADDR_SURF_TILE_SPLIT_4KB = 0x6, 1353 + } TileSplit; 1354 + typedef enum SampleSplit { 1355 + ADDR_SURF_SAMPLE_SPLIT_1 = 0x0, 1356 + ADDR_SURF_SAMPLE_SPLIT_2 = 0x1, 1357 + ADDR_SURF_SAMPLE_SPLIT_4 = 0x2, 1358 + ADDR_SURF_SAMPLE_SPLIT_8 = 0x3, 1359 + } SampleSplit; 1360 + typedef enum PipeConfig { 1361 + ADDR_SURF_P2 = 0x0, 1362 + ADDR_SURF_P2_RESERVED0 = 0x1, 1363 + ADDR_SURF_P2_RESERVED1 = 0x2, 1364 + ADDR_SURF_P2_RESERVED2 = 0x3, 1365 + ADDR_SURF_P4_8x16 = 0x4, 1366 + ADDR_SURF_P4_16x16 = 0x5, 1367 + ADDR_SURF_P4_16x32 = 0x6, 1368 + ADDR_SURF_P4_32x32 = 0x7, 1369 + ADDR_SURF_P8_16x16_8x16 = 0x8, 1370 + ADDR_SURF_P8_16x32_8x16 = 0x9, 1371 + ADDR_SURF_P8_32x32_8x16 = 0xa, 1372 + ADDR_SURF_P8_16x32_16x16 = 0xb, 1373 + ADDR_SURF_P8_32x32_16x16 = 0xc, 1374 + ADDR_SURF_P8_32x32_16x32 = 0xd, 1375 + ADDR_SURF_P8_32x64_32x32 = 0xe, 1376 + ADDR_SURF_P8_RESERVED0 = 0xf, 1377 + ADDR_SURF_P16_32x32_8x16 = 0x10, 1378 + ADDR_SURF_P16_32x32_16x16 = 0x11, 1379 + } PipeConfig; 1380 + typedef enum NumBanks { 1381 + ADDR_SURF_2_BANK = 0x0, 1382 + ADDR_SURF_4_BANK = 0x1, 1383 + ADDR_SURF_8_BANK = 0x2, 1384 + ADDR_SURF_16_BANK = 0x3, 1385 + } NumBanks; 1386 + typedef enum BankWidth { 1387 + ADDR_SURF_BANK_WIDTH_1 = 0x0, 1388 + ADDR_SURF_BANK_WIDTH_2 = 0x1, 1389 + ADDR_SURF_BANK_WIDTH_4 = 0x2, 1390 + ADDR_SURF_BANK_WIDTH_8 = 0x3, 1391 + } BankWidth; 1392 + typedef enum BankHeight { 1393 + ADDR_SURF_BANK_HEIGHT_1 = 0x0, 1394 + ADDR_SURF_BANK_HEIGHT_2 = 0x1, 1395 + ADDR_SURF_BANK_HEIGHT_4 = 0x2, 1396 + ADDR_SURF_BANK_HEIGHT_8 = 0x3, 1397 + } BankHeight; 1398 + typedef enum BankWidthHeight { 1399 + ADDR_SURF_BANK_WH_1 = 0x0, 1400 + ADDR_SURF_BANK_WH_2 = 0x1, 1401 + ADDR_SURF_BANK_WH_4 = 0x2, 1402 + ADDR_SURF_BANK_WH_8 = 0x3, 1403 + } BankWidthHeight; 1404 + typedef enum MacroTileAspect { 1405 + ADDR_SURF_MACRO_ASPECT_1 = 0x0, 1406 + ADDR_SURF_MACRO_ASPECT_2 = 0x1, 1407 + ADDR_SURF_MACRO_ASPECT_4 = 0x2, 1408 + ADDR_SURF_MACRO_ASPECT_8 = 0x3, 1409 + } MacroTileAspect; 1410 + typedef enum GATCL1RequestType { 1411 + GATCL1_TYPE_NORMAL = 0x0, 1412 + GATCL1_TYPE_SHOOTDOWN = 0x1, 1413 + GATCL1_TYPE_BYPASS = 0x2, 1414 + } GATCL1RequestType; 1415 + typedef enum TCC_CACHE_POLICIES { 1416 + TCC_CACHE_POLICY_LRU = 0x0, 1417 + TCC_CACHE_POLICY_STREAM = 0x1, 1418 + } TCC_CACHE_POLICIES; 1419 + typedef enum MTYPE { 1420 + MTYPE_NC_NV = 0x0, 1421 + MTYPE_NC = 0x1, 1422 + MTYPE_CC = 0x2, 1423 + MTYPE_UC = 0x3, 1424 + } MTYPE; 1425 + typedef enum PERFMON_COUNTER_MODE { 1426 + PERFMON_COUNTER_MODE_ACCUM = 0x0, 1427 + PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x1, 1428 + PERFMON_COUNTER_MODE_MAX = 0x2, 1429 + PERFMON_COUNTER_MODE_DIRTY = 0x3, 1430 + PERFMON_COUNTER_MODE_SAMPLE = 0x4, 1431 + PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x5, 1432 + PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x6, 1433 + PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x7, 1434 + PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x8, 1435 + PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x9, 1436 + PERFMON_COUNTER_MODE_RESERVED = 0xf, 1437 + } PERFMON_COUNTER_MODE; 1438 + typedef enum PERFMON_SPM_MODE { 1439 + PERFMON_SPM_MODE_OFF = 0x0, 1440 + PERFMON_SPM_MODE_16BIT_CLAMP = 0x1, 1441 + PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2, 1442 + PERFMON_SPM_MODE_32BIT_CLAMP = 0x3, 1443 + PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x4, 1444 + PERFMON_SPM_MODE_RESERVED_5 = 0x5, 1445 + PERFMON_SPM_MODE_RESERVED_6 = 0x6, 1446 + PERFMON_SPM_MODE_RESERVED_7 = 0x7, 1447 + PERFMON_SPM_MODE_TEST_MODE_0 = 0x8, 1448 + PERFMON_SPM_MODE_TEST_MODE_1 = 0x9, 1449 + PERFMON_SPM_MODE_TEST_MODE_2 = 0xa, 1450 + } PERFMON_SPM_MODE; 1451 + typedef enum SurfaceTiling { 1452 + ARRAY_LINEAR = 0x0, 1453 + ARRAY_TILED = 0x1, 1454 + } SurfaceTiling; 1455 + typedef enum SurfaceArray { 1456 + ARRAY_1D = 0x0, 1457 + ARRAY_2D = 0x1, 1458 + ARRAY_3D = 0x2, 1459 + ARRAY_3D_SLICE = 0x3, 1460 + } SurfaceArray; 1461 + typedef enum ColorArray { 1462 + ARRAY_2D_ALT_COLOR = 0x0, 1463 + ARRAY_2D_COLOR = 0x1, 1464 + ARRAY_3D_SLICE_COLOR = 0x3, 1465 + } ColorArray; 1466 + typedef enum DepthArray { 1467 + ARRAY_2D_ALT_DEPTH = 0x0, 1468 + ARRAY_2D_DEPTH = 0x1, 1469 + } DepthArray; 1470 + typedef enum ENUM_NUM_SIMD_PER_CU { 1471 + NUM_SIMD_PER_CU = 0x4, 1472 + } ENUM_NUM_SIMD_PER_CU; 1473 + typedef enum MEM_PWR_FORCE_CTRL { 1474 + NO_FORCE_REQUEST = 0x0, 1475 + FORCE_LIGHT_SLEEP_REQUEST = 0x1, 1476 + FORCE_DEEP_SLEEP_REQUEST = 0x2, 1477 + FORCE_SHUT_DOWN_REQUEST = 0x3, 1478 + } MEM_PWR_FORCE_CTRL; 1479 + typedef enum MEM_PWR_FORCE_CTRL2 { 1480 + NO_FORCE_REQ = 0x0, 1481 + FORCE_LIGHT_SLEEP_REQ = 0x1, 1482 + } MEM_PWR_FORCE_CTRL2; 1483 + typedef enum MEM_PWR_DIS_CTRL { 1484 + ENABLE_MEM_PWR_CTRL = 0x0, 1485 + DISABLE_MEM_PWR_CTRL = 0x1, 1486 + } MEM_PWR_DIS_CTRL; 1487 + typedef enum MEM_PWR_SEL_CTRL { 1488 + DYNAMIC_SHUT_DOWN_ENABLE = 0x0, 1489 + DYNAMIC_DEEP_SLEEP_ENABLE = 0x1, 1490 + DYNAMIC_LIGHT_SLEEP_ENABLE = 0x2, 1491 + } MEM_PWR_SEL_CTRL; 1492 + typedef enum MEM_PWR_SEL_CTRL2 { 1493 + DYNAMIC_DEEP_SLEEP_EN = 0x0, 1494 + DYNAMIC_LIGHT_SLEEP_EN = 0x1, 1495 + } MEM_PWR_SEL_CTRL2; 1496 + 1497 + #endif /* OSS_3_0_ENUM_H */
+3660
drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h
··· 1 + /* 2 + * OSS_3_0 Register documentation 3 + * 4 + * Copyright (C) 2014 Advanced Micro Devices, Inc. 5 + * 6 + * Permission is hereby granted, free of charge, to any person obtaining a 7 + * copy of this software and associated documentation files (the "Software"), 8 + * to deal in the Software without restriction, including without limitation 9 + * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 + * and/or sell copies of the Software, and to permit persons to whom the 11 + * Software is furnished to do so, subject to the following conditions: 12 + * 13 + * The above copyright notice and this permission notice shall be included 14 + * in all copies or substantial portions of the Software. 15 + * 16 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 20 + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21 + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22 + */ 23 + 24 + #ifndef OSS_3_0_SH_MASK_H 25 + #define OSS_3_0_SH_MASK_H 26 + 27 + #define IH_VMID_0_LUT__PASID_MASK 0xffff 28 + #define IH_VMID_0_LUT__PASID__SHIFT 0x0 29 + #define IH_VMID_1_LUT__PASID_MASK 0xffff 30 + #define IH_VMID_1_LUT__PASID__SHIFT 0x0 31 + #define IH_VMID_2_LUT__PASID_MASK 0xffff 32 + #define IH_VMID_2_LUT__PASID__SHIFT 0x0 33 + #define IH_VMID_3_LUT__PASID_MASK 0xffff 34 + #define IH_VMID_3_LUT__PASID__SHIFT 0x0 35 + #define IH_VMID_4_LUT__PASID_MASK 0xffff 36 + #define IH_VMID_4_LUT__PASID__SHIFT 0x0 37 + #define IH_VMID_5_LUT__PASID_MASK 0xffff 38 + #define IH_VMID_5_LUT__PASID__SHIFT 0x0 39 + #define IH_VMID_6_LUT__PASID_MASK 0xffff 40 + #define IH_VMID_6_LUT__PASID__SHIFT 0x0 41 + #define IH_VMID_7_LUT__PASID_MASK 0xffff 42 + #define IH_VMID_7_LUT__PASID__SHIFT 0x0 43 + #define IH_VMID_8_LUT__PASID_MASK 0xffff 44 + #define IH_VMID_8_LUT__PASID__SHIFT 0x0 45 + #define IH_VMID_9_LUT__PASID_MASK 0xffff 46 + #define IH_VMID_9_LUT__PASID__SHIFT 0x0 47 + #define IH_VMID_10_LUT__PASID_MASK 0xffff 48 + #define IH_VMID_10_LUT__PASID__SHIFT 0x0 49 + #define IH_VMID_11_LUT__PASID_MASK 0xffff 50 + #define IH_VMID_11_LUT__PASID__SHIFT 0x0 51 + #define IH_VMID_12_LUT__PASID_MASK 0xffff 52 + #define IH_VMID_12_LUT__PASID__SHIFT 0x0 53 + #define IH_VMID_13_LUT__PASID_MASK 0xffff 54 + #define IH_VMID_13_LUT__PASID__SHIFT 0x0 55 + #define IH_VMID_14_LUT__PASID_MASK 0xffff 56 + #define IH_VMID_14_LUT__PASID__SHIFT 0x0 57 + #define IH_VMID_15_LUT__PASID_MASK 0xffff 58 + #define IH_VMID_15_LUT__PASID__SHIFT 0x0 59 + #define IH_RB_CNTL__RB_ENABLE_MASK 0x1 60 + #define IH_RB_CNTL__RB_ENABLE__SHIFT 0x0 61 + #define IH_RB_CNTL__RB_SIZE_MASK 0x3e 62 + #define IH_RB_CNTL__RB_SIZE__SHIFT 0x1 63 + #define IH_RB_CNTL__RB_GPU_TS_ENABLE_MASK 0x80 64 + #define IH_RB_CNTL__RB_GPU_TS_ENABLE__SHIFT 0x7 65 + #define IH_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK 0x100 66 + #define IH_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT 0x8 67 + #define IH_RB_CNTL__ENABLE_INTR_MASK 0x20000 68 + #define IH_RB_CNTL__ENABLE_INTR__SHIFT 0x11 69 + #define IH_RB_CNTL__MC_SWAP_MASK 0xc0000 70 + #define IH_RB_CNTL__MC_SWAP__SHIFT 0x12 71 + #define IH_RB_CNTL__RPTR_REARM_MASK 0x200000 72 + #define IH_RB_CNTL__RPTR_REARM__SHIFT 0x15 73 + #define IH_RB_CNTL__MC_VMID_MASK 0xf000000 74 + #define IH_RB_CNTL__MC_VMID__SHIFT 0x18 75 + #define IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK 0x80000000 76 + #define IH_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f 77 + #define IH_RB_BASE__ADDR_MASK 0xffffffff 78 + #define IH_RB_BASE__ADDR__SHIFT 0x0 79 + #define IH_RB_RPTR__OFFSET_MASK 0x3fffc 80 + #define IH_RB_RPTR__OFFSET__SHIFT 0x2 81 + #define IH_RB_WPTR__RB_OVERFLOW_MASK 0x1 82 + #define IH_RB_WPTR__RB_OVERFLOW__SHIFT 0x0 83 + #define IH_RB_WPTR__OFFSET_MASK 0x3fffc 84 + #define IH_RB_WPTR__OFFSET__SHIFT 0x2 85 + #define IH_RB_WPTR__RB_LEFT_NONE_MASK 0x40000 86 + #define IH_RB_WPTR__RB_LEFT_NONE__SHIFT 0x12 87 + #define IH_RB_WPTR__RB_MAY_OVERFLOW_MASK 0x80000 88 + #define IH_RB_WPTR__RB_MAY_OVERFLOW__SHIFT 0x13 89 + #define IH_RB_WPTR_ADDR_HI__ADDR_MASK 0xff 90 + #define IH_RB_WPTR_ADDR_HI__ADDR__SHIFT 0x0 91 + #define IH_RB_WPTR_ADDR_LO__ADDR_MASK 0xfffffffc 92 + #define IH_RB_WPTR_ADDR_LO__ADDR__SHIFT 0x2 93 + #define IH_CNTL__WPTR_WRITEBACK_TIMER_MASK 0x1f 94 + #define IH_CNTL__WPTR_WRITEBACK_TIMER__SHIFT 0x0 95 + #define IH_CNTL__CLIENT_FIFO_HIGHWATER_MASK 0x300 96 + #define IH_CNTL__CLIENT_FIFO_HIGHWATER__SHIFT 0x8 97 + #define IH_CNTL__MC_FIFO_HIGHWATER_MASK 0x7c00 98 + #define IH_CNTL__MC_FIFO_HIGHWATER__SHIFT 0xa 99 + #define IH_CNTL__MC_WRREQ_CREDIT_MASK 0xf8000 100 + #define IH_CNTL__MC_WRREQ_CREDIT__SHIFT 0xf 101 + #define IH_CNTL__MC_WR_CLEAN_CNT_MASK 0x1f00000 102 + #define IH_CNTL__MC_WR_CLEAN_CNT__SHIFT 0x14 103 + #define IH_LEVEL_STATUS__DC_STATUS_MASK 0x1 104 + #define IH_LEVEL_STATUS__DC_STATUS__SHIFT 0x0 105 + #define IH_LEVEL_STATUS__ROM_STATUS_MASK 0x4 106 + #define IH_LEVEL_STATUS__ROM_STATUS__SHIFT 0x2 107 + #define IH_LEVEL_STATUS__SRBM_STATUS_MASK 0x8 108 + #define IH_LEVEL_STATUS__SRBM_STATUS__SHIFT 0x3 109 + #define IH_LEVEL_STATUS__BIF_STATUS_MASK 0x10 110 + #define IH_LEVEL_STATUS__BIF_STATUS__SHIFT 0x4 111 + #define IH_LEVEL_STATUS__XDMA_STATUS_MASK 0x20 112 + #define IH_LEVEL_STATUS__XDMA_STATUS__SHIFT 0x5 113 + #define IH_STATUS__IDLE_MASK 0x1 114 + #define IH_STATUS__IDLE__SHIFT 0x0 115 + #define IH_STATUS__INPUT_IDLE_MASK 0x2 116 + #define IH_STATUS__INPUT_IDLE__SHIFT 0x1 117 + #define IH_STATUS__RB_IDLE_MASK 0x4 118 + #define IH_STATUS__RB_IDLE__SHIFT 0x2 119 + #define IH_STATUS__RB_FULL_MASK 0x8 120 + #define IH_STATUS__RB_FULL__SHIFT 0x3 121 + #define IH_STATUS__RB_FULL_DRAIN_MASK 0x10 122 + #define IH_STATUS__RB_FULL_DRAIN__SHIFT 0x4 123 + #define IH_STATUS__RB_OVERFLOW_MASK 0x20 124 + #define IH_STATUS__RB_OVERFLOW__SHIFT 0x5 125 + #define IH_STATUS__MC_WR_IDLE_MASK 0x40 126 + #define IH_STATUS__MC_WR_IDLE__SHIFT 0x6 127 + #define IH_STATUS__MC_WR_STALL_MASK 0x80 128 + #define IH_STATUS__MC_WR_STALL__SHIFT 0x7 129 + #define IH_STATUS__MC_WR_CLEAN_PENDING_MASK 0x100 130 + #define IH_STATUS__MC_WR_CLEAN_PENDING__SHIFT 0x8 131 + #define IH_STATUS__MC_WR_CLEAN_STALL_MASK 0x200 132 + #define IH_STATUS__MC_WR_CLEAN_STALL__SHIFT 0x9 133 + #define IH_STATUS__BIF_INTERRUPT_LINE_MASK 0x400 134 + #define IH_STATUS__BIF_INTERRUPT_LINE__SHIFT 0xa 135 + #define IH_STATUS__SWITCH_READY_MASK 0x800 136 + #define IH_STATUS__SWITCH_READY__SHIFT 0xb 137 + #define IH_PERFMON_CNTL__ENABLE0_MASK 0x1 138 + #define IH_PERFMON_CNTL__ENABLE0__SHIFT 0x0 139 + #define IH_PERFMON_CNTL__CLEAR0_MASK 0x2 140 + #define IH_PERFMON_CNTL__CLEAR0__SHIFT 0x1 141 + #define IH_PERFMON_CNTL__PERF_SEL0_MASK 0x3fc 142 + #define IH_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2 143 + #define IH_PERFMON_CNTL__ENABLE1_MASK 0x400 144 + #define IH_PERFMON_CNTL__ENABLE1__SHIFT 0xa 145 + #define IH_PERFMON_CNTL__CLEAR1_MASK 0x800 146 + #define IH_PERFMON_CNTL__CLEAR1__SHIFT 0xb 147 + #define IH_PERFMON_CNTL__PERF_SEL1_MASK 0xff000 148 + #define IH_PERFMON_CNTL__PERF_SEL1__SHIFT 0xc 149 + #define IH_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xffffffff 150 + #define IH_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0 151 + #define IH_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xffffffff 152 + #define IH_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0 153 + #define IH_DEBUG__RB_FULL_DRAIN_ENABLE_MASK 0x1 154 + #define IH_DEBUG__RB_FULL_DRAIN_ENABLE__SHIFT 0x0 155 + #define IH_DEBUG__WPTR_OVERFLOW_ENABLE_MASK 0x2 156 + #define IH_DEBUG__WPTR_OVERFLOW_ENABLE__SHIFT 0x1 157 + #define IH_DEBUG__MC_WR_FIFO_BLOCK_ENABLE_MASK 0x4 158 + #define IH_DEBUG__MC_WR_FIFO_BLOCK_ENABLE__SHIFT 0x2 159 + #define IH_DSM_MATCH_VALUE_BIT_31_0__VALUE_MASK 0xffffffff 160 + #define IH_DSM_MATCH_VALUE_BIT_31_0__VALUE__SHIFT 0x0 161 + #define IH_DSM_MATCH_VALUE_BIT_63_32__VALUE_MASK 0xffffffff 162 + #define IH_DSM_MATCH_VALUE_BIT_63_32__VALUE__SHIFT 0x0 163 + #define IH_DSM_MATCH_VALUE_BIT_95_64__VALUE_MASK 0xffffffff 164 + #define IH_DSM_MATCH_VALUE_BIT_95_64__VALUE__SHIFT 0x0 165 + #define IH_DSM_MATCH_FIELD_CONTROL__SRC_EN_MASK 0x1 166 + #define IH_DSM_MATCH_FIELD_CONTROL__SRC_EN__SHIFT 0x0 167 + #define IH_DSM_MATCH_FIELD_CONTROL__FCNID_EN_MASK 0x2 168 + #define IH_DSM_MATCH_FIELD_CONTROL__FCNID_EN__SHIFT 0x1 169 + #define IH_DSM_MATCH_FIELD_CONTROL__TIMESTAMP_EN_MASK 0x4 170 + #define IH_DSM_MATCH_FIELD_CONTROL__TIMESTAMP_EN__SHIFT 0x2 171 + #define IH_DSM_MATCH_FIELD_CONTROL__RINGID_EN_MASK 0x8 172 + #define IH_DSM_MATCH_FIELD_CONTROL__RINGID_EN__SHIFT 0x3 173 + #define IH_DSM_MATCH_FIELD_CONTROL__VMID_EN_MASK 0x10 174 + #define IH_DSM_MATCH_FIELD_CONTROL__VMID_EN__SHIFT 0x4 175 + #define IH_DSM_MATCH_FIELD_CONTROL__PASID_EN_MASK 0x20 176 + #define IH_DSM_MATCH_FIELD_CONTROL__PASID_EN__SHIFT 0x5 177 + #define IH_DSM_MATCH_DATA_CONTROL__VALUE_MASK 0xfffffff 178 + #define IH_DSM_MATCH_DATA_CONTROL__VALUE__SHIFT 0x0 179 + #define IH_DOORBELL_RPTR__OFFSET_MASK 0x1fffff 180 + #define IH_DOORBELL_RPTR__OFFSET__SHIFT 0x0 181 + #define IH_DOORBELL_RPTR__ENABLE_MASK 0x10000000 182 + #define IH_DOORBELL_RPTR__ENABLE__SHIFT 0x1c 183 + #define IH_DOORBELL_RPTR__CAPTURED_MASK 0x40000000 184 + #define IH_DOORBELL_RPTR__CAPTURED__SHIFT 0x1e 185 + #define IH_ACTIVE_FCN_ID__VF_ID_MASK 0xf 186 + #define IH_ACTIVE_FCN_ID__VF_ID__SHIFT 0x0 187 + #define IH_ACTIVE_FCN_ID__RESERVED_MASK 0x7ffffff0 188 + #define IH_ACTIVE_FCN_ID__RESERVED__SHIFT 0x4 189 + #define IH_ACTIVE_FCN_ID__PF_VF_MASK 0x80000000 190 + #define IH_ACTIVE_FCN_ID__PF_VF__SHIFT 0x1f 191 + #define IH_VF_RB_STATUS__RB_FULL_DRAIN_VF_MASK 0xffff 192 + #define IH_VF_RB_STATUS__RB_FULL_DRAIN_VF__SHIFT 0x0 193 + #define IH_VF_RB_STATUS__RB_OVERFLOW_VF_MASK 0xffff0000 194 + #define IH_VF_RB_STATUS__RB_OVERFLOW_VF__SHIFT 0x10 195 + #define IH_VF_ENABLE__VALUE_MASK 0x1 196 + #define IH_VF_ENABLE__VALUE__SHIFT 0x0 197 + #define IH_VIRT_RESET_REQ__VF_MASK 0xffff 198 + #define IH_VIRT_RESET_REQ__VF__SHIFT 0x0 199 + #define IH_VIRT_RESET_REQ__PF_MASK 0x80000000 200 + #define IH_VIRT_RESET_REQ__PF__SHIFT 0x1f 201 + #define IH_VF_RB_BIF_STATUS__RB_FULL_VF_MASK 0xffff 202 + #define IH_VF_RB_BIF_STATUS__RB_FULL_VF__SHIFT 0x0 203 + #define IH_VF_RB_BIF_STATUS__BIF_INTERRUPT_LINE_VF_MASK 0xffff0000 204 + #define IH_VF_RB_BIF_STATUS__BIF_INTERRUPT_LINE_VF__SHIFT 0x10 205 + #define IH_VERSION__VALUE_MASK 0xfff 206 + #define IH_VERSION__VALUE__SHIFT 0x0 207 + #define IH_LEVEL_INTR_MASK__MASK_MASK 0x1 208 + #define IH_LEVEL_INTR_MASK__MASK__SHIFT 0x0 209 + #define IH_RESET_INCOMPLETE_INT_CNTL__CG_MASK 0x1 210 + #define IH_RESET_INCOMPLETE_INT_CNTL__CG__SHIFT 0x0 211 + #define IH_RESET_INCOMPLETE_INT_CNTL__DC_MASK 0x2 212 + #define IH_RESET_INCOMPLETE_INT_CNTL__DC__SHIFT 0x1 213 + #define IH_RESET_INCOMPLETE_INT_CNTL__SAMMSP_MASK 0x8 214 + #define IH_RESET_INCOMPLETE_INT_CNTL__SAMMSP__SHIFT 0x3 215 + #define IH_RESET_INCOMPLETE_INT_CNTL__RLC_MASK 0x10 216 + #define IH_RESET_INCOMPLETE_INT_CNTL__RLC__SHIFT 0x4 217 + #define IH_RESET_INCOMPLETE_INT_CNTL__ROM_MASK 0x20 218 + #define IH_RESET_INCOMPLETE_INT_CNTL__ROM__SHIFT 0x5 219 + #define IH_RESET_INCOMPLETE_INT_CNTL__SRBM_MASK 0x40 220 + #define IH_RESET_INCOMPLETE_INT_CNTL__SRBM__SHIFT 0x6 221 + #define IH_RESET_INCOMPLETE_INT_CNTL__VMC_MASK 0x80 222 + #define IH_RESET_INCOMPLETE_INT_CNTL__VMC__SHIFT 0x7 223 + #define IH_RESET_INCOMPLETE_INT_CNTL__UVD_MASK 0x100 224 + #define IH_RESET_INCOMPLETE_INT_CNTL__UVD__SHIFT 0x8 225 + #define IH_RESET_INCOMPLETE_INT_CNTL__BIF_MASK 0x200 226 + #define IH_RESET_INCOMPLETE_INT_CNTL__BIF__SHIFT 0x9 227 + #define IH_RESET_INCOMPLETE_INT_CNTL__SDMA0_MASK 0x400 228 + #define IH_RESET_INCOMPLETE_INT_CNTL__SDMA0__SHIFT 0xa 229 + #define IH_RESET_INCOMPLETE_INT_CNTL__SDMA1_MASK 0x800 230 + #define IH_RESET_INCOMPLETE_INT_CNTL__SDMA1__SHIFT 0xb 231 + #define IH_RESET_INCOMPLETE_INT_CNTL__ISP_MASK 0x1000 232 + #define IH_RESET_INCOMPLETE_INT_CNTL__ISP__SHIFT 0xc 233 + #define IH_RESET_INCOMPLETE_INT_CNTL__VCE0_MASK 0x2000 234 + #define IH_RESET_INCOMPLETE_INT_CNTL__VCE0__SHIFT 0xd 235 + #define IH_RESET_INCOMPLETE_INT_CNTL__VCE1_MASK 0x4000 236 + #define IH_RESET_INCOMPLETE_INT_CNTL__VCE1__SHIFT 0xe 237 + #define IH_RESET_INCOMPLETE_INT_CNTL__ATC_MASK 0x8000 238 + #define IH_RESET_INCOMPLETE_INT_CNTL__ATC__SHIFT 0xf 239 + #define IH_RESET_INCOMPLETE_INT_CNTL__XDMA_MASK 0x10000 240 + #define IH_RESET_INCOMPLETE_INT_CNTL__XDMA__SHIFT 0x10 241 + #define IH_RESET_INCOMPLETE_INT_CNTL__ACP_MASK 0x20000 242 + #define IH_RESET_INCOMPLETE_INT_CNTL__ACP__SHIFT 0x11 243 + #define IH_RESET_INCOMPLETE_INT_CNTL__SH_MASK 0x40000 244 + #define IH_RESET_INCOMPLETE_INT_CNTL__SH__SHIFT 0x12 245 + #define IH_RESET_INCOMPLETE_INT_CNTL__SH1_MASK 0x80000 246 + #define IH_RESET_INCOMPLETE_INT_CNTL__SH1__SHIFT 0x13 247 + #define IH_RESET_INCOMPLETE_INT_CNTL__SH2_MASK 0x100000 248 + #define IH_RESET_INCOMPLETE_INT_CNTL__SH2__SHIFT 0x14 249 + #define IH_RESET_INCOMPLETE_INT_CNTL__SH3_MASK 0x200000 250 + #define IH_RESET_INCOMPLETE_INT_CNTL__SH3__SHIFT 0x15 251 + #define IH_RESET_INCOMPLETE_INT_CNTL__RESET_ENABLE_MASK 0x400000 252 + #define IH_RESET_INCOMPLETE_INT_CNTL__RESET_ENABLE__SHIFT 0x16 253 + #define IH_RESET_INCOMPLETE_INT_CNTL__INCOMPLETE_CNT_MASK 0xf000000 254 + #define IH_RESET_INCOMPLETE_INT_CNTL__INCOMPLETE_CNT__SHIFT 0x18 255 + #define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__CG_MASK 0x1 256 + #define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__CG__SHIFT 0x0 257 + #define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__DC_MASK 0x2 258 + #define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__DC__SHIFT 0x1 259 + #define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SAMMSP_MASK 0x8 260 + #define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SAMMSP__SHIFT 0x3 261 + #define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__RLC_MASK 0x10 262 + #define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__RLC__SHIFT 0x4 263 + #define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__ROM_MASK 0x20 264 + #define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__ROM__SHIFT 0x5 265 + #define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SRBM_MASK 0x40 266 + #define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SRBM__SHIFT 0x6 267 + #define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__VMC_MASK 0x80 268 + #define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__VMC__SHIFT 0x7 269 + #define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__UVD_MASK 0x100 270 + #define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__UVD__SHIFT 0x8 271 + #define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__BIF_MASK 0x200 272 + #define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__BIF__SHIFT 0x9 273 + #define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SDMA0_MASK 0x400 274 + #define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SDMA0__SHIFT 0xa 275 + #define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SDMA1_MASK 0x800 276 + #define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SDMA1__SHIFT 0xb 277 + #define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__ISP_MASK 0x1000 278 + #define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__ISP__SHIFT 0xc 279 + #define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__VCE0_MASK 0x2000 280 + #define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__VCE0__SHIFT 0xd 281 + #define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__VCE1_MASK 0x4000 282 + #define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__VCE1__SHIFT 0xe 283 + #define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__ATC_MASK 0x8000 284 + #define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__ATC__SHIFT 0xf 285 + #define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__XDMA_MASK 0x10000 286 + #define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__XDMA__SHIFT 0x10 287 + #define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__ACP_MASK 0x20000 288 + #define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__ACP__SHIFT 0x11 289 + #define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SH_MASK 0x40000 290 + #define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SH__SHIFT 0x12 291 + #define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SH1_MASK 0x80000 292 + #define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SH1__SHIFT 0x13 293 + #define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SH2_MASK 0x100000 294 + #define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SH2__SHIFT 0x14 295 + #define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SH3_MASK 0x200000 296 + #define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SH3__SHIFT 0x15 297 + #define SEM_MCIF_CONFIG__MC_REQ_SWAP_MASK 0x3 298 + #define SEM_MCIF_CONFIG__MC_REQ_SWAP__SHIFT 0x0 299 + #define SEM_MCIF_CONFIG__MC_WRREQ_CREDIT_MASK 0xfc 300 + #define SEM_MCIF_CONFIG__MC_WRREQ_CREDIT__SHIFT 0x2 301 + #define SEM_MCIF_CONFIG__MC_RDREQ_CREDIT_MASK 0x3f00 302 + #define SEM_MCIF_CONFIG__MC_RDREQ_CREDIT__SHIFT 0x8 303 + #define SDMA_CONFIG__SDMA_RDREQ_URG_MASK 0xf00 304 + #define SDMA_CONFIG__SDMA_RDREQ_URG__SHIFT 0x8 305 + #define SDMA_CONFIG__SDMA_REQ_TRAN_MASK 0x10000 306 + #define SDMA_CONFIG__SDMA_REQ_TRAN__SHIFT 0x10 307 + #define SDMA1_CONFIG__SDMA_RDREQ_URG_MASK 0xf00 308 + #define SDMA1_CONFIG__SDMA_RDREQ_URG__SHIFT 0x8 309 + #define SDMA1_CONFIG__SDMA_REQ_TRAN_MASK 0x10000 310 + #define SDMA1_CONFIG__SDMA_REQ_TRAN__SHIFT 0x10 311 + #define UVD_CONFIG__UVD_RDREQ_URG_MASK 0xf00 312 + #define UVD_CONFIG__UVD_RDREQ_URG__SHIFT 0x8 313 + #define UVD_CONFIG__UVD_REQ_TRAN_MASK 0x10000 314 + #define UVD_CONFIG__UVD_REQ_TRAN__SHIFT 0x10 315 + #define VCE_CONFIG__VCE_RDREQ_URG_MASK 0xf00 316 + #define VCE_CONFIG__VCE_RDREQ_URG__SHIFT 0x8 317 + #define VCE_CONFIG__VCE_REQ_TRAN_MASK 0x10000 318 + #define VCE_CONFIG__VCE_REQ_TRAN__SHIFT 0x10 319 + #define SEM_VF_ENABLE__VALUE_MASK 0x1 320 + #define SEM_VF_ENABLE__VALUE__SHIFT 0x0 321 + #define CP_CONFIG__CP_RDREQ_URG_MASK 0xf00 322 + #define CP_CONFIG__CP_RDREQ_URG__SHIFT 0x8 323 + #define CP_CONFIG__CP_REQ_TRAN_MASK 0x10000 324 + #define CP_CONFIG__CP_REQ_TRAN__SHIFT 0x10 325 + #define SEM_ACTIVE_FCN_ID__VFID_MASK 0xf 326 + #define SEM_ACTIVE_FCN_ID__VFID__SHIFT 0x0 327 + #define SEM_ACTIVE_FCN_ID__VF_MASK 0x80000000 328 + #define SEM_ACTIVE_FCN_ID__VF__SHIFT 0x1f 329 + #define SEM_VIRT_RESET_REQ__VF_MASK 0xffff 330 + #define SEM_VIRT_RESET_REQ__VF__SHIFT 0x0 331 + #define SEM_VIRT_RESET_REQ__PF_MASK 0x80000000 332 + #define SEM_VIRT_RESET_REQ__PF__SHIFT 0x1f 333 + #define SEM_STATUS__SEM_IDLE_MASK 0x1 334 + #define SEM_STATUS__SEM_IDLE__SHIFT 0x0 335 + #define SEM_STATUS__SEM_INTERNAL_IDLE_MASK 0x2 336 + #define SEM_STATUS__SEM_INTERNAL_IDLE__SHIFT 0x1 337 + #define SEM_STATUS__MC_RDREQ_FIFO_FULL_MASK 0x4 338 + #define SEM_STATUS__MC_RDREQ_FIFO_FULL__SHIFT 0x2 339 + #define SEM_STATUS__MC_WRREQ_FIFO_FULL_MASK 0x8 340 + #define SEM_STATUS__MC_WRREQ_FIFO_FULL__SHIFT 0x3 341 + #define SEM_STATUS__WRITE1_FIFO_FULL_MASK 0x10 342 + #define SEM_STATUS__WRITE1_FIFO_FULL__SHIFT 0x4 343 + #define SEM_STATUS__CHECK0_FIFO_FULL_MASK 0x20 344 + #define SEM_STATUS__CHECK0_FIFO_FULL__SHIFT 0x5 345 + #define SEM_STATUS__MC_RDREQ_PENDING_MASK 0x40 346 + #define SEM_STATUS__MC_RDREQ_PENDING__SHIFT 0x6 347 + #define SEM_STATUS__MC_WRREQ_PENDING_MASK 0x80 348 + #define SEM_STATUS__MC_WRREQ_PENDING__SHIFT 0x7 349 + #define SEM_STATUS__SDMA0_MAILBOX_PENDING_MASK 0x100 350 + #define SEM_STATUS__SDMA0_MAILBOX_PENDING__SHIFT 0x8 351 + #define SEM_STATUS__SDMA1_MAILBOX_PENDING_MASK 0x200 352 + #define SEM_STATUS__SDMA1_MAILBOX_PENDING__SHIFT 0x9 353 + #define SEM_STATUS__UVD_MAILBOX_PENDING_MASK 0x400 354 + #define SEM_STATUS__UVD_MAILBOX_PENDING__SHIFT 0xa 355 + #define SEM_STATUS__VCE_MAILBOX_PENDING_MASK 0x800 356 + #define SEM_STATUS__VCE_MAILBOX_PENDING__SHIFT 0xb 357 + #define SEM_STATUS__CPG1_MAILBOX_PENDING_MASK 0x1000 358 + #define SEM_STATUS__CPG1_MAILBOX_PENDING__SHIFT 0xc 359 + #define SEM_STATUS__CPG2_MAILBOX_PENDING_MASK 0x2000 360 + #define SEM_STATUS__CPG2_MAILBOX_PENDING__SHIFT 0xd 361 + #define SEM_STATUS__VCE1_MAILBOX_PENDING_MASK 0x4000 362 + #define SEM_STATUS__VCE1_MAILBOX_PENDING__SHIFT 0xe 363 + #define SEM_STATUS__SWITCH_READY_MASK 0x80000000 364 + #define SEM_STATUS__SWITCH_READY__SHIFT 0x1f 365 + #define SEM_EDC_CONFIG__DIS_EDC_MASK 0x2 366 + #define SEM_EDC_CONFIG__DIS_EDC__SHIFT 0x1 367 + #define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT0_MASK 0x7 368 + #define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT0__SHIFT 0x0 369 + #define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT1_MASK 0x38 370 + #define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT1__SHIFT 0x3 371 + #define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT2_MASK 0x1c0 372 + #define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT2__SHIFT 0x6 373 + #define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT3_MASK 0xe00 374 + #define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT3__SHIFT 0x9 375 + #define SEM_MAILBOX_CLIENTCONFIG__SDMA_CLIENT0_MASK 0x7000 376 + #define SEM_MAILBOX_CLIENTCONFIG__SDMA_CLIENT0__SHIFT 0xc 377 + #define SEM_MAILBOX_CLIENTCONFIG__UVD_CLIENT0_MASK 0x38000 378 + #define SEM_MAILBOX_CLIENTCONFIG__UVD_CLIENT0__SHIFT 0xf 379 + #define SEM_MAILBOX_CLIENTCONFIG__SDMA1_CLIENT0_MASK 0x1c0000 380 + #define SEM_MAILBOX_CLIENTCONFIG__SDMA1_CLIENT0__SHIFT 0x12 381 + #define SEM_MAILBOX_CLIENTCONFIG__VCE_CLIENT0_MASK 0xe00000 382 + #define SEM_MAILBOX_CLIENTCONFIG__VCE_CLIENT0__SHIFT 0x15 383 + #define SEM_MAILBOX__SIDEPORT_MASK 0xff 384 + #define SEM_MAILBOX__SIDEPORT__SHIFT 0x0 385 + #define SEM_MAILBOX__HOSTPORT_MASK 0xff00 386 + #define SEM_MAILBOX__HOSTPORT__SHIFT 0x8 387 + #define SEM_MAILBOX__SIDEPORT_EXTRA_MASK 0xff0000 388 + #define SEM_MAILBOX__SIDEPORT_EXTRA__SHIFT 0x10 389 + #define SEM_MAILBOX__HOSTPORT_EXTRA_MASK 0xff000000 390 + #define SEM_MAILBOX__HOSTPORT_EXTRA__SHIFT 0x18 391 + #define SEM_MAILBOX_CONTROL__SIDEPORT_ENABLE_MASK 0xff 392 + #define SEM_MAILBOX_CONTROL__SIDEPORT_ENABLE__SHIFT 0x0 393 + #define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE_MASK 0xff00 394 + #define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE__SHIFT 0x8 395 + #define SEM_MAILBOX_CONTROL__SIDEPORT_ENABLE_EXTRA_MASK 0xff0000 396 + #define SEM_MAILBOX_CONTROL__SIDEPORT_ENABLE_EXTRA__SHIFT 0x10 397 + #define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE_EXTRA_MASK 0xff000000 398 + #define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE_EXTRA__SHIFT 0x18 399 + #define SEM_CHICKEN_BITS__VMID_PIPELINE_EN_MASK 0x1 400 + #define SEM_CHICKEN_BITS__VMID_PIPELINE_EN__SHIFT 0x0 401 + #define SEM_CHICKEN_BITS__ENTRY_PIPELINE_EN_MASK 0x2 402 + #define SEM_CHICKEN_BITS__ENTRY_PIPELINE_EN__SHIFT 0x1 403 + #define SEM_CHICKEN_BITS__CHECK_COUNTER_EN_MASK 0x4 404 + #define SEM_CHICKEN_BITS__CHECK_COUNTER_EN__SHIFT 0x2 405 + #define SEM_CHICKEN_BITS__ECC_BEHAVIOR_MASK 0x18 406 + #define SEM_CHICKEN_BITS__ECC_BEHAVIOR__SHIFT 0x3 407 + #define SEM_CHICKEN_BITS__IDLE_COUNTER_INDEX_MASK 0xf00 408 + #define SEM_CHICKEN_BITS__IDLE_COUNTER_INDEX__SHIFT 0x8 409 + #define SEM_MAILBOX_CLIENTCONFIG_EXTRA__VCE1_CLIENT0_MASK 0x1f 410 + #define SEM_MAILBOX_CLIENTCONFIG_EXTRA__VCE1_CLIENT0__SHIFT 0x0 411 + #define SRBM_CNTL__PWR_REQUEST_HALT_MASK 0x10000 412 + #define SRBM_CNTL__PWR_REQUEST_HALT__SHIFT 0x10 413 + #define SRBM_CNTL__COMBINE_SYSTEM_MC_MASK 0x20000 414 + #define SRBM_CNTL__COMBINE_SYSTEM_MC__SHIFT 0x11 415 + #define SRBM_CNTL__REPORT_LAST_RDERR_MASK 0x40000 416 + #define SRBM_CNTL__REPORT_LAST_RDERR__SHIFT 0x12 417 + #define SRBM_GFX_CNTL__PIPEID_MASK 0x3 418 + #define SRBM_GFX_CNTL__PIPEID__SHIFT 0x0 419 + #define SRBM_GFX_CNTL__MEID_MASK 0xc 420 + #define SRBM_GFX_CNTL__MEID__SHIFT 0x2 421 + #define SRBM_GFX_CNTL__VMID_MASK 0xf0 422 + #define SRBM_GFX_CNTL__VMID__SHIFT 0x4 423 + #define SRBM_GFX_CNTL__QUEUEID_MASK 0x700 424 + #define SRBM_GFX_CNTL__QUEUEID__SHIFT 0x8 425 + #define SRBM_READ_CNTL__READ_TIMEOUT_MASK 0xffffff 426 + #define SRBM_READ_CNTL__READ_TIMEOUT__SHIFT 0x0 427 + #define SRBM_STATUS2__SDMA_RQ_PENDING_MASK 0x1 428 + #define SRBM_STATUS2__SDMA_RQ_PENDING__SHIFT 0x0 429 + #define SRBM_STATUS2__TST_RQ_PENDING_MASK 0x2 430 + #define SRBM_STATUS2__TST_RQ_PENDING__SHIFT 0x1 431 + #define SRBM_STATUS2__SDMA1_RQ_PENDING_MASK 0x4 432 + #define SRBM_STATUS2__SDMA1_RQ_PENDING__SHIFT 0x2 433 + #define SRBM_STATUS2__VCE0_RQ_PENDING_MASK 0x8 434 + #define SRBM_STATUS2__VCE0_RQ_PENDING__SHIFT 0x3 435 + #define SRBM_STATUS2__VP8_BUSY_MASK 0x10 436 + #define SRBM_STATUS2__VP8_BUSY__SHIFT 0x4 437 + #define SRBM_STATUS2__SDMA_BUSY_MASK 0x20 438 + #define SRBM_STATUS2__SDMA_BUSY__SHIFT 0x5 439 + #define SRBM_STATUS2__SDMA1_BUSY_MASK 0x40 440 + #define SRBM_STATUS2__SDMA1_BUSY__SHIFT 0x6 441 + #define SRBM_STATUS2__VCE0_BUSY_MASK 0x80 442 + #define SRBM_STATUS2__VCE0_BUSY__SHIFT 0x7 443 + #define SRBM_STATUS2__XDMA_BUSY_MASK 0x100 444 + #define SRBM_STATUS2__XDMA_BUSY__SHIFT 0x8 445 + #define SRBM_STATUS2__CHUB_BUSY_MASK 0x200 446 + #define SRBM_STATUS2__CHUB_BUSY__SHIFT 0x9 447 + #define SRBM_STATUS2__SDMA2_BUSY_MASK 0x400 448 + #define SRBM_STATUS2__SDMA2_BUSY__SHIFT 0xa 449 + #define SRBM_STATUS2__SDMA3_BUSY_MASK 0x800 450 + #define SRBM_STATUS2__SDMA3_BUSY__SHIFT 0xb 451 + #define SRBM_STATUS2__SAMSCP_BUSY_MASK 0x1000 452 + #define SRBM_STATUS2__SAMSCP_BUSY__SHIFT 0xc 453 + #define SRBM_STATUS2__ISP_BUSY_MASK 0x2000 454 + #define SRBM_STATUS2__ISP_BUSY__SHIFT 0xd 455 + #define SRBM_STATUS2__VCE1_BUSY_MASK 0x4000 456 + #define SRBM_STATUS2__VCE1_BUSY__SHIFT 0xe 457 + #define SRBM_STATUS2__ODE_BUSY_MASK 0x8000 458 + #define SRBM_STATUS2__ODE_BUSY__SHIFT 0xf 459 + #define SRBM_STATUS2__SDMA2_RQ_PENDING_MASK 0x10000 460 + #define SRBM_STATUS2__SDMA2_RQ_PENDING__SHIFT 0x10 461 + #define SRBM_STATUS2__SDMA3_RQ_PENDING_MASK 0x20000 462 + #define SRBM_STATUS2__SDMA3_RQ_PENDING__SHIFT 0x11 463 + #define SRBM_STATUS2__SAMSCP_RQ_PENDING_MASK 0x40000 464 + #define SRBM_STATUS2__SAMSCP_RQ_PENDING__SHIFT 0x12 465 + #define SRBM_STATUS2__ISP_RQ_PENDING_MASK 0x80000 466 + #define SRBM_STATUS2__ISP_RQ_PENDING__SHIFT 0x13 467 + #define SRBM_STATUS2__VCE1_RQ_PENDING_MASK 0x100000 468 + #define SRBM_STATUS2__VCE1_RQ_PENDING__SHIFT 0x14 469 + #define SRBM_STATUS__UVD_RQ_PENDING_MASK 0x2 470 + #define SRBM_STATUS__UVD_RQ_PENDING__SHIFT 0x1 471 + #define SRBM_STATUS__SAMMSP_RQ_PENDING_MASK 0x4 472 + #define SRBM_STATUS__SAMMSP_RQ_PENDING__SHIFT 0x2 473 + #define SRBM_STATUS__ACP_RQ_PENDING_MASK 0x8 474 + #define SRBM_STATUS__ACP_RQ_PENDING__SHIFT 0x3 475 + #define SRBM_STATUS__SMU_RQ_PENDING_MASK 0x10 476 + #define SRBM_STATUS__SMU_RQ_PENDING__SHIFT 0x4 477 + #define SRBM_STATUS__GRBM_RQ_PENDING_MASK 0x20 478 + #define SRBM_STATUS__GRBM_RQ_PENDING__SHIFT 0x5 479 + #define SRBM_STATUS__HI_RQ_PENDING_MASK 0x40 480 + #define SRBM_STATUS__HI_RQ_PENDING__SHIFT 0x6 481 + #define SRBM_STATUS__VMC_BUSY_MASK 0x100 482 + #define SRBM_STATUS__VMC_BUSY__SHIFT 0x8 483 + #define SRBM_STATUS__MCB_BUSY_MASK 0x200 484 + #define SRBM_STATUS__MCB_BUSY__SHIFT 0x9 485 + #define SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK 0x400 486 + #define SRBM_STATUS__MCB_NON_DISPLAY_BUSY__SHIFT 0xa 487 + #define SRBM_STATUS__MCC_BUSY_MASK 0x800 488 + #define SRBM_STATUS__MCC_BUSY__SHIFT 0xb 489 + #define SRBM_STATUS__MCD_BUSY_MASK 0x1000 490 + #define SRBM_STATUS__MCD_BUSY__SHIFT 0xc 491 + #define SRBM_STATUS__VMC1_BUSY_MASK 0x2000 492 + #define SRBM_STATUS__VMC1_BUSY__SHIFT 0xd 493 + #define SRBM_STATUS__SEM_BUSY_MASK 0x4000 494 + #define SRBM_STATUS__SEM_BUSY__SHIFT 0xe 495 + #define SRBM_STATUS__ACP_BUSY_MASK 0x10000 496 + #define SRBM_STATUS__ACP_BUSY__SHIFT 0x10 497 + #define SRBM_STATUS__IH_BUSY_MASK 0x20000 498 + #define SRBM_STATUS__IH_BUSY__SHIFT 0x11 499 + #define SRBM_STATUS__UVD_BUSY_MASK 0x80000 500 + #define SRBM_STATUS__UVD_BUSY__SHIFT 0x13 501 + #define SRBM_STATUS__SAMMSP_BUSY_MASK 0x100000 502 + #define SRBM_STATUS__SAMMSP_BUSY__SHIFT 0x14 503 + #define SRBM_STATUS__GCATCL2_BUSY_MASK 0x200000 504 + #define SRBM_STATUS__GCATCL2_BUSY__SHIFT 0x15 505 + #define SRBM_STATUS__OSATCL2_BUSY_MASK 0x400000 506 + #define SRBM_STATUS__OSATCL2_BUSY__SHIFT 0x16 507 + #define SRBM_STATUS__BIF_BUSY_MASK 0x20000000 508 + #define SRBM_STATUS__BIF_BUSY__SHIFT 0x1d 509 + #define SRBM_STATUS3__MCC0_BUSY_MASK 0x1 510 + #define SRBM_STATUS3__MCC0_BUSY__SHIFT 0x0 511 + #define SRBM_STATUS3__MCC1_BUSY_MASK 0x2 512 + #define SRBM_STATUS3__MCC1_BUSY__SHIFT 0x1 513 + #define SRBM_STATUS3__MCC2_BUSY_MASK 0x4 514 + #define SRBM_STATUS3__MCC2_BUSY__SHIFT 0x2 515 + #define SRBM_STATUS3__MCC3_BUSY_MASK 0x8 516 + #define SRBM_STATUS3__MCC3_BUSY__SHIFT 0x3 517 + #define SRBM_STATUS3__MCC4_BUSY_MASK 0x10 518 + #define SRBM_STATUS3__MCC4_BUSY__SHIFT 0x4 519 + #define SRBM_STATUS3__MCC5_BUSY_MASK 0x20 520 + #define SRBM_STATUS3__MCC5_BUSY__SHIFT 0x5 521 + #define SRBM_STATUS3__MCC6_BUSY_MASK 0x40 522 + #define SRBM_STATUS3__MCC6_BUSY__SHIFT 0x6 523 + #define SRBM_STATUS3__MCC7_BUSY_MASK 0x80 524 + #define SRBM_STATUS3__MCC7_BUSY__SHIFT 0x7 525 + #define SRBM_STATUS3__MCD0_BUSY_MASK 0x100 526 + #define SRBM_STATUS3__MCD0_BUSY__SHIFT 0x8 527 + #define SRBM_STATUS3__MCD1_BUSY_MASK 0x200 528 + #define SRBM_STATUS3__MCD1_BUSY__SHIFT 0x9 529 + #define SRBM_STATUS3__MCD2_BUSY_MASK 0x400 530 + #define SRBM_STATUS3__MCD2_BUSY__SHIFT 0xa 531 + #define SRBM_STATUS3__MCD3_BUSY_MASK 0x800 532 + #define SRBM_STATUS3__MCD3_BUSY__SHIFT 0xb 533 + #define SRBM_STATUS3__MCD4_BUSY_MASK 0x1000 534 + #define SRBM_STATUS3__MCD4_BUSY__SHIFT 0xc 535 + #define SRBM_STATUS3__MCD5_BUSY_MASK 0x2000 536 + #define SRBM_STATUS3__MCD5_BUSY__SHIFT 0xd 537 + #define SRBM_STATUS3__MCD6_BUSY_MASK 0x4000 538 + #define SRBM_STATUS3__MCD6_BUSY__SHIFT 0xe 539 + #define SRBM_STATUS3__MCD7_BUSY_MASK 0x8000 540 + #define SRBM_STATUS3__MCD7_BUSY__SHIFT 0xf 541 + #define SRBM_SOFT_RESET__SOFT_RESET_ATCL2_MASK 0x1 542 + #define SRBM_SOFT_RESET__SOFT_RESET_ATCL2__SHIFT 0x0 543 + #define SRBM_SOFT_RESET__SOFT_RESET_BIF_MASK 0x2 544 + #define SRBM_SOFT_RESET__SOFT_RESET_BIF__SHIFT 0x1 545 + #define SRBM_SOFT_RESET__SOFT_RESET_SDMA3_MASK 0x4 546 + #define SRBM_SOFT_RESET__SOFT_RESET_SDMA3__SHIFT 0x2 547 + #define SRBM_SOFT_RESET__SOFT_RESET_SDMA2_MASK 0x8 548 + #define SRBM_SOFT_RESET__SOFT_RESET_SDMA2__SHIFT 0x3 549 + #define SRBM_SOFT_RESET__SOFT_RESET_GIONB_MASK 0x10 550 + #define SRBM_SOFT_RESET__SOFT_RESET_GIONB__SHIFT 0x4 551 + #define SRBM_SOFT_RESET__SOFT_RESET_DC_MASK 0x20 552 + #define SRBM_SOFT_RESET__SOFT_RESET_DC__SHIFT 0x5 553 + #define SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK 0x40 554 + #define SRBM_SOFT_RESET__SOFT_RESET_SDMA1__SHIFT 0x6 555 + #define SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK 0x100 556 + #define SRBM_SOFT_RESET__SOFT_RESET_GRBM__SHIFT 0x8 557 + #define SRBM_SOFT_RESET__SOFT_RESET_HDP_MASK 0x200 558 + #define SRBM_SOFT_RESET__SOFT_RESET_HDP__SHIFT 0x9 559 + #define SRBM_SOFT_RESET__SOFT_RESET_IH_MASK 0x400 560 + #define SRBM_SOFT_RESET__SOFT_RESET_IH__SHIFT 0xa 561 + #define SRBM_SOFT_RESET__SOFT_RESET_MC_MASK 0x800 562 + #define SRBM_SOFT_RESET__SOFT_RESET_MC__SHIFT 0xb 563 + #define SRBM_SOFT_RESET__SOFT_RESET_CHUB_MASK 0x1000 564 + #define SRBM_SOFT_RESET__SOFT_RESET_CHUB__SHIFT 0xc 565 + #define SRBM_SOFT_RESET__SOFT_RESET_ESRAM_MASK 0x2000 566 + #define SRBM_SOFT_RESET__SOFT_RESET_ESRAM__SHIFT 0xd 567 + #define SRBM_SOFT_RESET__SOFT_RESET_ROM_MASK 0x4000 568 + #define SRBM_SOFT_RESET__SOFT_RESET_ROM__SHIFT 0xe 569 + #define SRBM_SOFT_RESET__SOFT_RESET_SEM_MASK 0x8000 570 + #define SRBM_SOFT_RESET__SOFT_RESET_SEM__SHIFT 0xf 571 + #define SRBM_SOFT_RESET__SOFT_RESET_SMU_MASK 0x10000 572 + #define SRBM_SOFT_RESET__SOFT_RESET_SMU__SHIFT 0x10 573 + #define SRBM_SOFT_RESET__SOFT_RESET_VMC_MASK 0x20000 574 + #define SRBM_SOFT_RESET__SOFT_RESET_VMC__SHIFT 0x11 575 + #define SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK 0x40000 576 + #define SRBM_SOFT_RESET__SOFT_RESET_UVD__SHIFT 0x12 577 + #define SRBM_SOFT_RESET__SOFT_RESET_VP8_MASK 0x80000 578 + #define SRBM_SOFT_RESET__SOFT_RESET_VP8__SHIFT 0x13 579 + #define SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK 0x100000 580 + #define SRBM_SOFT_RESET__SOFT_RESET_SDMA__SHIFT 0x14 581 + #define SRBM_SOFT_RESET__SOFT_RESET_TST_MASK 0x200000 582 + #define SRBM_SOFT_RESET__SOFT_RESET_TST__SHIFT 0x15 583 + #define SRBM_SOFT_RESET__SOFT_RESET_REGBB_MASK 0x400000 584 + #define SRBM_SOFT_RESET__SOFT_RESET_REGBB__SHIFT 0x16 585 + #define SRBM_SOFT_RESET__SOFT_RESET_ODE_MASK 0x800000 586 + #define SRBM_SOFT_RESET__SOFT_RESET_ODE__SHIFT 0x17 587 + #define SRBM_SOFT_RESET__SOFT_RESET_VCE0_MASK 0x1000000 588 + #define SRBM_SOFT_RESET__SOFT_RESET_VCE0__SHIFT 0x18 589 + #define SRBM_SOFT_RESET__SOFT_RESET_XDMA_MASK 0x2000000 590 + #define SRBM_SOFT_RESET__SOFT_RESET_XDMA__SHIFT 0x19 591 + #define SRBM_SOFT_RESET__SOFT_RESET_ACP_MASK 0x4000000 592 + #define SRBM_SOFT_RESET__SOFT_RESET_ACP__SHIFT 0x1a 593 + #define SRBM_SOFT_RESET__SOFT_RESET_SAMMSP_MASK 0x8000000 594 + #define SRBM_SOFT_RESET__SOFT_RESET_SAMMSP__SHIFT 0x1b 595 + #define SRBM_SOFT_RESET__SOFT_RESET_SAMSCP_MASK 0x10000000 596 + #define SRBM_SOFT_RESET__SOFT_RESET_SAMSCP__SHIFT 0x1c 597 + #define SRBM_SOFT_RESET__SOFT_RESET_GRN_MASK 0x20000000 598 + #define SRBM_SOFT_RESET__SOFT_RESET_GRN__SHIFT 0x1d 599 + #define SRBM_SOFT_RESET__SOFT_RESET_ISP_MASK 0x40000000 600 + #define SRBM_SOFT_RESET__SOFT_RESET_ISP__SHIFT 0x1e 601 + #define SRBM_SOFT_RESET__SOFT_RESET_VCE1_MASK 0x80000000 602 + #define SRBM_SOFT_RESET__SOFT_RESET_VCE1__SHIFT 0x1f 603 + #define SRBM_DEBUG_CNTL__SRBM_DEBUG_INDEX_MASK 0x3f 604 + #define SRBM_DEBUG_CNTL__SRBM_DEBUG_INDEX__SHIFT 0x0 605 + #define SRBM_DEBUG_DATA__DATA_MASK 0xffffffff 606 + #define SRBM_DEBUG_DATA__DATA__SHIFT 0x0 607 + #define SRBM_CHIP_REVISION__CHIP_REVISION_MASK 0xff 608 + #define SRBM_CHIP_REVISION__CHIP_REVISION__SHIFT 0x0 609 + #define SRBM_CREDIT_RECOVER_CNTL__CREDIT_RECOVER_TIME_MASK 0xfff 610 + #define SRBM_CREDIT_RECOVER_CNTL__CREDIT_RECOVER_TIME__SHIFT 0x0 611 + #define SRBM_CREDIT_RECOVER_CNTL__CREDIT_RECOVER_ENABLE_MASK 0x80000000 612 + #define SRBM_CREDIT_RECOVER_CNTL__CREDIT_RECOVER_ENABLE__SHIFT 0x1f 613 + #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_BIF_MASK 0x1 614 + #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_BIF__SHIFT 0x0 615 + #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_SMU_MASK 0x2 616 + #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_SMU__SHIFT 0x1 617 + #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_DC_MASK 0x4 618 + #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_DC__SHIFT 0x2 619 + #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_GIONB_MASK 0x8 620 + #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_GIONB__SHIFT 0x3 621 + #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_ACP_MASK 0x10 622 + #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_ACP__SHIFT 0x4 623 + #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_XDMA_MASK 0x20 624 + #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_XDMA__SHIFT 0x5 625 + #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_ODE_MASK 0x40 626 + #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_ODE__SHIFT 0x6 627 + #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_REGBB_MASK 0x80 628 + #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_REGBB__SHIFT 0x7 629 + #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_VP8_MASK 0x100 630 + #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_VP8__SHIFT 0x8 631 + #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_GRBM_MASK 0x200 632 + #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_GRBM__SHIFT 0x9 633 + #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_UVD_MASK 0x400 634 + #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_UVD__SHIFT 0xa 635 + #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_VCE0_MASK 0x800 636 + #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_VCE0__SHIFT 0xb 637 + #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_VCE1_MASK 0x1000 638 + #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_VCE1__SHIFT 0xc 639 + #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_ISP_MASK 0x2000 640 + #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_ISP__SHIFT 0xd 641 + #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_SAM_MASK 0x4000 642 + #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_SAM__SHIFT 0xe 643 + #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCB_MASK 0x8000 644 + #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCB__SHIFT 0xf 645 + #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCC0_MASK 0x10000 646 + #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCC0__SHIFT 0x10 647 + #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCC1_MASK 0x20000 648 + #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCC1__SHIFT 0x11 649 + #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCC2_MASK 0x40000 650 + #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCC2__SHIFT 0x12 651 + #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCC3_MASK 0x80000 652 + #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCC3__SHIFT 0x13 653 + #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCC4_MASK 0x100000 654 + #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCC4__SHIFT 0x14 655 + #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCC5_MASK 0x200000 656 + #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCC5__SHIFT 0x15 657 + #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCC6_MASK 0x400000 658 + #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCC6__SHIFT 0x16 659 + #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCC7_MASK 0x800000 660 + #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCC7__SHIFT 0x17 661 + #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCD0_MASK 0x1000000 662 + #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCD0__SHIFT 0x18 663 + #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCD1_MASK 0x2000000 664 + #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCD1__SHIFT 0x19 665 + #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCD2_MASK 0x4000000 666 + #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCD2__SHIFT 0x1a 667 + #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCD3_MASK 0x8000000 668 + #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCD3__SHIFT 0x1b 669 + #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCD4_MASK 0x10000000 670 + #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCD4__SHIFT 0x1c 671 + #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCD5_MASK 0x20000000 672 + #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCD5__SHIFT 0x1d 673 + #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCD6_MASK 0x40000000 674 + #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCD6__SHIFT 0x1e 675 + #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCD7_MASK 0x80000000 676 + #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCD7__SHIFT 0x1f 677 + #define SRBM_CREDIT_RESET__CREDIT_RESET_BIF_MASK 0x1 678 + #define SRBM_CREDIT_RESET__CREDIT_RESET_BIF__SHIFT 0x0 679 + #define SRBM_CREDIT_RESET__CREDIT_RESET_SMU_MASK 0x2 680 + #define SRBM_CREDIT_RESET__CREDIT_RESET_SMU__SHIFT 0x1 681 + #define SRBM_CREDIT_RESET__CREDIT_RESET_DC_MASK 0x4 682 + #define SRBM_CREDIT_RESET__CREDIT_RESET_DC__SHIFT 0x2 683 + #define SRBM_CREDIT_RESET__CREDIT_RESET_GIONB_MASK 0x8 684 + #define SRBM_CREDIT_RESET__CREDIT_RESET_GIONB__SHIFT 0x3 685 + #define SRBM_CREDIT_RESET__CREDIT_RESET_ACP_MASK 0x10 686 + #define SRBM_CREDIT_RESET__CREDIT_RESET_ACP__SHIFT 0x4 687 + #define SRBM_CREDIT_RESET__CREDIT_RESET_XDMA_MASK 0x20 688 + #define SRBM_CREDIT_RESET__CREDIT_RESET_XDMA__SHIFT 0x5 689 + #define SRBM_CREDIT_RESET__CREDIT_RESET_ODE_MASK 0x40 690 + #define SRBM_CREDIT_RESET__CREDIT_RESET_ODE__SHIFT 0x6 691 + #define SRBM_CREDIT_RESET__CREDIT_RESET_REGBB_MASK 0x80 692 + #define SRBM_CREDIT_RESET__CREDIT_RESET_REGBB__SHIFT 0x7 693 + #define SRBM_CREDIT_RESET__CREDIT_RESET_VP8_MASK 0x100 694 + #define SRBM_CREDIT_RESET__CREDIT_RESET_VP8__SHIFT 0x8 695 + #define SRBM_CREDIT_RESET__CREDIT_RESET_GRBM_MASK 0x200 696 + #define SRBM_CREDIT_RESET__CREDIT_RESET_GRBM__SHIFT 0x9 697 + #define SRBM_CREDIT_RESET__CREDIT_RESET_UVD_MASK 0x400 698 + #define SRBM_CREDIT_RESET__CREDIT_RESET_UVD__SHIFT 0xa 699 + #define SRBM_CREDIT_RESET__CREDIT_RESET_VCE0_MASK 0x800 700 + #define SRBM_CREDIT_RESET__CREDIT_RESET_VCE0__SHIFT 0xb 701 + #define SRBM_CREDIT_RESET__CREDIT_RESET_VCE1_MASK 0x1000 702 + #define SRBM_CREDIT_RESET__CREDIT_RESET_VCE1__SHIFT 0xc 703 + #define SRBM_CREDIT_RESET__CREDIT_RESET_ISP_MASK 0x2000 704 + #define SRBM_CREDIT_RESET__CREDIT_RESET_ISP__SHIFT 0xd 705 + #define SRBM_CREDIT_RESET__CREDIT_RESET_SAM_MASK 0x4000 706 + #define SRBM_CREDIT_RESET__CREDIT_RESET_SAM__SHIFT 0xe 707 + #define SRBM_CREDIT_RESET__CREDIT_RESET_MCB_MASK 0x8000 708 + #define SRBM_CREDIT_RESET__CREDIT_RESET_MCB__SHIFT 0xf 709 + #define SRBM_CREDIT_RESET__CREDIT_RESET_MCC0_MASK 0x10000 710 + #define SRBM_CREDIT_RESET__CREDIT_RESET_MCC0__SHIFT 0x10 711 + #define SRBM_CREDIT_RESET__CREDIT_RESET_MCC1_MASK 0x20000 712 + #define SRBM_CREDIT_RESET__CREDIT_RESET_MCC1__SHIFT 0x11 713 + #define SRBM_CREDIT_RESET__CREDIT_RESET_MCC2_MASK 0x40000 714 + #define SRBM_CREDIT_RESET__CREDIT_RESET_MCC2__SHIFT 0x12 715 + #define SRBM_CREDIT_RESET__CREDIT_RESET_MCC3_MASK 0x80000 716 + #define SRBM_CREDIT_RESET__CREDIT_RESET_MCC3__SHIFT 0x13 717 + #define SRBM_CREDIT_RESET__CREDIT_RESET_MCC4_MASK 0x100000 718 + #define SRBM_CREDIT_RESET__CREDIT_RESET_MCC4__SHIFT 0x14 719 + #define SRBM_CREDIT_RESET__CREDIT_RESET_MCC5_MASK 0x200000 720 + #define SRBM_CREDIT_RESET__CREDIT_RESET_MCC5__SHIFT 0x15 721 + #define SRBM_CREDIT_RESET__CREDIT_RESET_MCC6_MASK 0x400000 722 + #define SRBM_CREDIT_RESET__CREDIT_RESET_MCC6__SHIFT 0x16 723 + #define SRBM_CREDIT_RESET__CREDIT_RESET_MCC7_MASK 0x800000 724 + #define SRBM_CREDIT_RESET__CREDIT_RESET_MCC7__SHIFT 0x17 725 + #define SRBM_CREDIT_RESET__CREDIT_RESET_MCD0_MASK 0x1000000 726 + #define SRBM_CREDIT_RESET__CREDIT_RESET_MCD0__SHIFT 0x18 727 + #define SRBM_CREDIT_RESET__CREDIT_RESET_MCD1_MASK 0x2000000 728 + #define SRBM_CREDIT_RESET__CREDIT_RESET_MCD1__SHIFT 0x19 729 + #define SRBM_CREDIT_RESET__CREDIT_RESET_MCD2_MASK 0x4000000 730 + #define SRBM_CREDIT_RESET__CREDIT_RESET_MCD2__SHIFT 0x1a 731 + #define SRBM_CREDIT_RESET__CREDIT_RESET_MCD3_MASK 0x8000000 732 + #define SRBM_CREDIT_RESET__CREDIT_RESET_MCD3__SHIFT 0x1b 733 + #define SRBM_CREDIT_RESET__CREDIT_RESET_MCD4_MASK 0x10000000 734 + #define SRBM_CREDIT_RESET__CREDIT_RESET_MCD4__SHIFT 0x1c 735 + #define SRBM_CREDIT_RESET__CREDIT_RESET_MCD5_MASK 0x20000000 736 + #define SRBM_CREDIT_RESET__CREDIT_RESET_MCD5__SHIFT 0x1d 737 + #define SRBM_CREDIT_RESET__CREDIT_RESET_MCD6_MASK 0x40000000 738 + #define SRBM_CREDIT_RESET__CREDIT_RESET_MCD6__SHIFT 0x1e 739 + #define SRBM_CREDIT_RESET__CREDIT_RESET_MCD7_MASK 0x80000000 740 + #define SRBM_CREDIT_RESET__CREDIT_RESET_MCD7__SHIFT 0x1f 741 + #define CC_SYS_RB_REDUNDANCY__FAILED_RB0_MASK 0xf00 742 + #define CC_SYS_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x8 743 + #define CC_SYS_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x1000 744 + #define CC_SYS_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0xc 745 + #define CC_SYS_RB_REDUNDANCY__FAILED_RB1_MASK 0xf0000 746 + #define CC_SYS_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x10 747 + #define CC_SYS_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x100000 748 + #define CC_SYS_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x14 749 + #define CC_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0xff0000 750 + #define CC_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10 751 + #define GC_USER_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0xff0000 752 + #define GC_USER_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10 753 + #define SRBM_MC_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf 754 + #define SRBM_MC_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0 755 + #define SRBM_MC_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00 756 + #define SRBM_MC_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8 757 + #define SRBM_SYS_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf 758 + #define SRBM_SYS_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0 759 + #define SRBM_SYS_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00 760 + #define SRBM_SYS_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8 761 + #define SRBM_VCE_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf 762 + #define SRBM_VCE_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0 763 + #define SRBM_VCE_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00 764 + #define SRBM_VCE_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8 765 + #define SRBM_UVD_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf 766 + #define SRBM_UVD_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0 767 + #define SRBM_UVD_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00 768 + #define SRBM_UVD_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8 769 + #define SRBM_SDMA_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf 770 + #define SRBM_SDMA_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0 771 + #define SRBM_SDMA_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00 772 + #define SRBM_SDMA_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8 773 + #define SRBM_SAM_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf 774 + #define SRBM_SAM_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0 775 + #define SRBM_SAM_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00 776 + #define SRBM_SAM_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8 777 + #define SRBM_ISP_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf 778 + #define SRBM_ISP_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0 779 + #define SRBM_ISP_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00 780 + #define SRBM_ISP_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8 781 + #define SRBM_VP8_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf 782 + #define SRBM_VP8_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0 783 + #define SRBM_VP8_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00 784 + #define SRBM_VP8_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8 785 + #define SRBM_DEBUG__IGNORE_RDY_MASK 0x1 786 + #define SRBM_DEBUG__IGNORE_RDY__SHIFT 0x0 787 + #define SRBM_DEBUG__DISABLE_READ_TIMEOUT_MASK 0x2 788 + #define SRBM_DEBUG__DISABLE_READ_TIMEOUT__SHIFT 0x1 789 + #define SRBM_DEBUG__SNAPSHOT_FREE_CNTRS_MASK 0x4 790 + #define SRBM_DEBUG__SNAPSHOT_FREE_CNTRS__SHIFT 0x2 791 + #define SRBM_DEBUG__SYS_CLOCK_DOMAIN_OVERRIDE_MASK 0x10 792 + #define SRBM_DEBUG__SYS_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x4 793 + #define SRBM_DEBUG__VCE_CLOCK_DOMAIN_OVERRIDE_MASK 0x20 794 + #define SRBM_DEBUG__VCE_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x5 795 + #define SRBM_DEBUG__UVD_CLOCK_DOMAIN_OVERRIDE_MASK 0x40 796 + #define SRBM_DEBUG__UVD_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x6 797 + #define SRBM_DEBUG__SDMA_CLOCK_DOMAIN_OVERRIDE_MASK 0x80 798 + #define SRBM_DEBUG__SDMA_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x7 799 + #define SRBM_DEBUG__MC_CLOCK_DOMAIN_OVERRIDE_MASK 0x100 800 + #define SRBM_DEBUG__MC_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x8 801 + #define SRBM_DEBUG__SAM_CLOCK_DOMAIN_OVERRIDE_MASK 0x200 802 + #define SRBM_DEBUG__SAM_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x9 803 + #define SRBM_DEBUG__ISP_CLOCK_DOMAIN_OVERRIDE_MASK 0x400 804 + #define SRBM_DEBUG__ISP_CLOCK_DOMAIN_OVERRIDE__SHIFT 0xa 805 + #define SRBM_DEBUG__VP8_CLOCK_DOMAIN_OVERRIDE_MASK 0x800 806 + #define SRBM_DEBUG__VP8_CLOCK_DOMAIN_OVERRIDE__SHIFT 0xb 807 + #define SRBM_DEBUG_SNAPSHOT__MCB_RDY_MASK 0x1 808 + #define SRBM_DEBUG_SNAPSHOT__MCB_RDY__SHIFT 0x0 809 + #define SRBM_DEBUG_SNAPSHOT__GIONB_RDY_MASK 0x2 810 + #define SRBM_DEBUG_SNAPSHOT__GIONB_RDY__SHIFT 0x1 811 + #define SRBM_DEBUG_SNAPSHOT__SMU_RDY_MASK 0x4 812 + #define SRBM_DEBUG_SNAPSHOT__SMU_RDY__SHIFT 0x2 813 + #define SRBM_DEBUG_SNAPSHOT__SAMMSP_RDY_MASK 0x8 814 + #define SRBM_DEBUG_SNAPSHOT__SAMMSP_RDY__SHIFT 0x3 815 + #define SRBM_DEBUG_SNAPSHOT__ACP_RDY_MASK 0x10 816 + #define SRBM_DEBUG_SNAPSHOT__ACP_RDY__SHIFT 0x4 817 + #define SRBM_DEBUG_SNAPSHOT__GRBM_RDY_MASK 0x20 818 + #define SRBM_DEBUG_SNAPSHOT__GRBM_RDY__SHIFT 0x5 819 + #define SRBM_DEBUG_SNAPSHOT__DC_RDY_MASK 0x40 820 + #define SRBM_DEBUG_SNAPSHOT__DC_RDY__SHIFT 0x6 821 + #define SRBM_DEBUG_SNAPSHOT__BIF_RDY_MASK 0x80 822 + #define SRBM_DEBUG_SNAPSHOT__BIF_RDY__SHIFT 0x7 823 + #define SRBM_DEBUG_SNAPSHOT__XDMA_RDY_MASK 0x100 824 + #define SRBM_DEBUG_SNAPSHOT__XDMA_RDY__SHIFT 0x8 825 + #define SRBM_DEBUG_SNAPSHOT__UVD_RDY_MASK 0x200 826 + #define SRBM_DEBUG_SNAPSHOT__UVD_RDY__SHIFT 0x9 827 + #define SRBM_DEBUG_SNAPSHOT__VP8_RDY_MASK 0x400 828 + #define SRBM_DEBUG_SNAPSHOT__VP8_RDY__SHIFT 0xa 829 + #define SRBM_DEBUG_SNAPSHOT__REGBB_RDY_MASK 0x800 830 + #define SRBM_DEBUG_SNAPSHOT__REGBB_RDY__SHIFT 0xb 831 + #define SRBM_DEBUG_SNAPSHOT__ODE_RDY_MASK 0x1000 832 + #define SRBM_DEBUG_SNAPSHOT__ODE_RDY__SHIFT 0xc 833 + #define SRBM_DEBUG_SNAPSHOT__MCD7_RDY_MASK 0x2000 834 + #define SRBM_DEBUG_SNAPSHOT__MCD7_RDY__SHIFT 0xd 835 + #define SRBM_DEBUG_SNAPSHOT__MCD6_RDY_MASK 0x4000 836 + #define SRBM_DEBUG_SNAPSHOT__MCD6_RDY__SHIFT 0xe 837 + #define SRBM_DEBUG_SNAPSHOT__MCD5_RDY_MASK 0x8000 838 + #define SRBM_DEBUG_SNAPSHOT__MCD5_RDY__SHIFT 0xf 839 + #define SRBM_DEBUG_SNAPSHOT__MCD4_RDY_MASK 0x10000 840 + #define SRBM_DEBUG_SNAPSHOT__MCD4_RDY__SHIFT 0x10 841 + #define SRBM_DEBUG_SNAPSHOT__MCD3_RDY_MASK 0x20000 842 + #define SRBM_DEBUG_SNAPSHOT__MCD3_RDY__SHIFT 0x11 843 + #define SRBM_DEBUG_SNAPSHOT__MCD2_RDY_MASK 0x40000 844 + #define SRBM_DEBUG_SNAPSHOT__MCD2_RDY__SHIFT 0x12 845 + #define SRBM_DEBUG_SNAPSHOT__MCD1_RDY_MASK 0x80000 846 + #define SRBM_DEBUG_SNAPSHOT__MCD1_RDY__SHIFT 0x13 847 + #define SRBM_DEBUG_SNAPSHOT__MCD0_RDY_MASK 0x100000 848 + #define SRBM_DEBUG_SNAPSHOT__MCD0_RDY__SHIFT 0x14 849 + #define SRBM_DEBUG_SNAPSHOT__MCC7_RDY_MASK 0x200000 850 + #define SRBM_DEBUG_SNAPSHOT__MCC7_RDY__SHIFT 0x15 851 + #define SRBM_DEBUG_SNAPSHOT__MCC6_RDY_MASK 0x400000 852 + #define SRBM_DEBUG_SNAPSHOT__MCC6_RDY__SHIFT 0x16 853 + #define SRBM_DEBUG_SNAPSHOT__MCC5_RDY_MASK 0x800000 854 + #define SRBM_DEBUG_SNAPSHOT__MCC5_RDY__SHIFT 0x17 855 + #define SRBM_DEBUG_SNAPSHOT__MCC4_RDY_MASK 0x1000000 856 + #define SRBM_DEBUG_SNAPSHOT__MCC4_RDY__SHIFT 0x18 857 + #define SRBM_DEBUG_SNAPSHOT__MCC3_RDY_MASK 0x2000000 858 + #define SRBM_DEBUG_SNAPSHOT__MCC3_RDY__SHIFT 0x19 859 + #define SRBM_DEBUG_SNAPSHOT__MCC2_RDY_MASK 0x4000000 860 + #define SRBM_DEBUG_SNAPSHOT__MCC2_RDY__SHIFT 0x1a 861 + #define SRBM_DEBUG_SNAPSHOT__MCC1_RDY_MASK 0x8000000 862 + #define SRBM_DEBUG_SNAPSHOT__MCC1_RDY__SHIFT 0x1b 863 + #define SRBM_DEBUG_SNAPSHOT__MCC0_RDY_MASK 0x10000000 864 + #define SRBM_DEBUG_SNAPSHOT__MCC0_RDY__SHIFT 0x1c 865 + #define SRBM_DEBUG_SNAPSHOT__VCE0_RDY_MASK 0x20000000 866 + #define SRBM_DEBUG_SNAPSHOT__VCE0_RDY__SHIFT 0x1d 867 + #define SRBM_DEBUG_SNAPSHOT__SAMSCP_RDY_MASK 0x40000000 868 + #define SRBM_DEBUG_SNAPSHOT__SAMSCP_RDY__SHIFT 0x1e 869 + #define SRBM_DEBUG_SNAPSHOT__ISP_RDY_MASK 0x80000000 870 + #define SRBM_DEBUG_SNAPSHOT__ISP_RDY__SHIFT 0x1f 871 + #define SRBM_DEBUG_SNAPSHOT2__VCE1_RDY_MASK 0x1 872 + #define SRBM_DEBUG_SNAPSHOT2__VCE1_RDY__SHIFT 0x0 873 + #define SRBM_READ_ERROR__READ_ADDRESS_MASK 0x3fffc 874 + #define SRBM_READ_ERROR__READ_ADDRESS__SHIFT 0x2 875 + #define SRBM_READ_ERROR__READ_REQUESTER_SDMA3_MASK 0x40000 876 + #define SRBM_READ_ERROR__READ_REQUESTER_SDMA3__SHIFT 0x12 877 + #define SRBM_READ_ERROR__READ_REQUESTER_SDMA2_MASK 0x80000 878 + #define SRBM_READ_ERROR__READ_REQUESTER_SDMA2__SHIFT 0x13 879 + #define SRBM_READ_ERROR__READ_REQUESTER_VCE0_MASK 0x100000 880 + #define SRBM_READ_ERROR__READ_REQUESTER_VCE0__SHIFT 0x14 881 + #define SRBM_READ_ERROR__READ_REQUESTER_SDMA1_MASK 0x200000 882 + #define SRBM_READ_ERROR__READ_REQUESTER_SDMA1__SHIFT 0x15 883 + #define SRBM_READ_ERROR__READ_REQUESTER_TST_MASK 0x400000 884 + #define SRBM_READ_ERROR__READ_REQUESTER_TST__SHIFT 0x16 885 + #define SRBM_READ_ERROR__READ_REQUESTER_SAMMSP_MASK 0x800000 886 + #define SRBM_READ_ERROR__READ_REQUESTER_SAMMSP__SHIFT 0x17 887 + #define SRBM_READ_ERROR__READ_REQUESTER_HI_MASK 0x1000000 888 + #define SRBM_READ_ERROR__READ_REQUESTER_HI__SHIFT 0x18 889 + #define SRBM_READ_ERROR__READ_REQUESTER_GRBM_MASK 0x2000000 890 + #define SRBM_READ_ERROR__READ_REQUESTER_GRBM__SHIFT 0x19 891 + #define SRBM_READ_ERROR__READ_REQUESTER_SMU_MASK 0x4000000 892 + #define SRBM_READ_ERROR__READ_REQUESTER_SMU__SHIFT 0x1a 893 + #define SRBM_READ_ERROR__READ_REQUESTER_SAMSCP_MASK 0x8000000 894 + #define SRBM_READ_ERROR__READ_REQUESTER_SAMSCP__SHIFT 0x1b 895 + #define SRBM_READ_ERROR__READ_REQUESTER_SDMA_MASK 0x10000000 896 + #define SRBM_READ_ERROR__READ_REQUESTER_SDMA__SHIFT 0x1c 897 + #define SRBM_READ_ERROR__READ_REQUESTER_UVD_MASK 0x20000000 898 + #define SRBM_READ_ERROR__READ_REQUESTER_UVD__SHIFT 0x1d 899 + #define SRBM_READ_ERROR__READ_ERROR_MASK 0x80000000 900 + #define SRBM_READ_ERROR__READ_ERROR__SHIFT 0x1f 901 + #define SRBM_READ_ERROR2__READ_REQUESTER_ACP_MASK 0x1 902 + #define SRBM_READ_ERROR2__READ_REQUESTER_ACP__SHIFT 0x0 903 + #define SRBM_READ_ERROR2__READ_REQUESTER_ISP_MASK 0x2 904 + #define SRBM_READ_ERROR2__READ_REQUESTER_ISP__SHIFT 0x1 905 + #define SRBM_READ_ERROR2__READ_REQUESTER_VCE1_MASK 0x4 906 + #define SRBM_READ_ERROR2__READ_REQUESTER_VCE1__SHIFT 0x2 907 + #define SRBM_READ_ERROR2__READ_VF_MASK 0x800000 908 + #define SRBM_READ_ERROR2__READ_VF__SHIFT 0x17 909 + #define SRBM_READ_ERROR2__READ_VFID_MASK 0xf000000 910 + #define SRBM_READ_ERROR2__READ_VFID__SHIFT 0x18 911 + #define SRBM_INT_CNTL__RDERR_INT_MASK_MASK 0x1 912 + #define SRBM_INT_CNTL__RDERR_INT_MASK__SHIFT 0x0 913 + #define SRBM_INT_CNTL__RAERR_INT_MASK_MASK 0x2 914 + #define SRBM_INT_CNTL__RAERR_INT_MASK__SHIFT 0x1 915 + #define SRBM_INT_STATUS__RDERR_INT_STAT_MASK 0x1 916 + #define SRBM_INT_STATUS__RDERR_INT_STAT__SHIFT 0x0 917 + #define SRBM_INT_STATUS__RAERR_INT_STAT_MASK 0x2 918 + #define SRBM_INT_STATUS__RAERR_INT_STAT__SHIFT 0x1 919 + #define SRBM_INT_ACK__RDERR_INT_ACK_MASK 0x1 920 + #define SRBM_INT_ACK__RDERR_INT_ACK__SHIFT 0x0 921 + #define SRBM_INT_ACK__RAERR_INT_ACK_MASK 0x2 922 + #define SRBM_INT_ACK__RAERR_INT_ACK__SHIFT 0x1 923 + #define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_BIF_MASK 0x1 924 + #define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_BIF__SHIFT 0x0 925 + #define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_ACP_MASK 0x2 926 + #define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_ACP__SHIFT 0x1 927 + #define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SAMSCP_MASK 0x4 928 + #define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SAMSCP__SHIFT 0x2 929 + #define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SAMMSP_MASK 0x8 930 + #define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SAMMSP__SHIFT 0x3 931 + #define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_TST_MASK 0x20 932 + #define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_TST__SHIFT 0x5 933 + #define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA3_MASK 0x40 934 + #define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA3__SHIFT 0x6 935 + #define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA2_MASK 0x80 936 + #define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA2__SHIFT 0x7 937 + #define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA1_MASK 0x100 938 + #define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA1__SHIFT 0x8 939 + #define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA0_MASK 0x200 940 + #define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA0__SHIFT 0x9 941 + #define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_UVD_MASK 0x400 942 + #define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_UVD__SHIFT 0xa 943 + #define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_VCE0_MASK 0x800 944 + #define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_VCE0__SHIFT 0xb 945 + #define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_GRBM_MASK 0x1000 946 + #define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_GRBM__SHIFT 0xc 947 + #define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SMU_MASK 0x2000 948 + #define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SMU__SHIFT 0xd 949 + #define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_PEER_MASK 0x4000 950 + #define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_PEER__SHIFT 0xe 951 + #define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_CPU_MASK 0x8000 952 + #define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_CPU__SHIFT 0xf 953 + #define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_ISP_MASK 0x10000 954 + #define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_ISP__SHIFT 0x10 955 + #define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_VCE1_MASK 0x20000 956 + #define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_VCE1__SHIFT 0x11 957 + #define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_RLCHYP_MASK 0x40000 958 + #define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_RLCHYP__SHIFT 0x12 959 + #define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SMUHYP_MASK 0x80000 960 + #define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SMUHYP__SHIFT 0x13 961 + #define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_BIFHYP_MASK 0x100000 962 + #define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_BIFHYP__SHIFT 0x14 963 + #define SRBM_FIREWALL_ERROR_SRC__RAERR_FIREWALL_VIOLATION_MASK 0x1000000 964 + #define SRBM_FIREWALL_ERROR_SRC__RAERR_FIREWALL_VIOLATION__SHIFT 0x18 965 + #define SRBM_FIREWALL_ERROR_SRC__RAERR_HAR_REGIONSIZE_OVERFLOW_MASK 0x2000000 966 + #define SRBM_FIREWALL_ERROR_SRC__RAERR_HAR_REGIONSIZE_OVERFLOW__SHIFT 0x19 967 + #define SRBM_FIREWALL_ERROR_SRC__RAERR_BIF_ADDR_OVERFLOW_MASK 0x4000000 968 + #define SRBM_FIREWALL_ERROR_SRC__RAERR_BIF_ADDR_OVERFLOW__SHIFT 0x1a 969 + #define SRBM_FIREWALL_ERROR_SRC__RAERR_P2SRP_REGIONSIZE_OVERFLOW_MASK 0x8000000 970 + #define SRBM_FIREWALL_ERROR_SRC__RAERR_P2SRP_REGIONSIZE_OVERFLOW__SHIFT 0x1b 971 + #define SRBM_FIREWALL_ERROR_SRC__RAERR_P2SRP_FIREWALL_VIOLATION_MASK 0x10000000 972 + #define SRBM_FIREWALL_ERROR_SRC__RAERR_P2SRP_FIREWALL_VIOLATION__SHIFT 0x1c 973 + #define SRBM_FIREWALL_ERROR_ADDR__ACCESS_ADDRESS_MASK 0x3fffc 974 + #define SRBM_FIREWALL_ERROR_ADDR__ACCESS_ADDRESS__SHIFT 0x2 975 + #define SRBM_FIREWALL_ERROR_ADDR__ACCESS_VF_MASK 0x80000 976 + #define SRBM_FIREWALL_ERROR_ADDR__ACCESS_VF__SHIFT 0x13 977 + #define SRBM_FIREWALL_ERROR_ADDR__ACCESS_VFID_MASK 0xf00000 978 + #define SRBM_FIREWALL_ERROR_ADDR__ACCESS_VFID__SHIFT 0x14 979 + #define SRBM_FIREWALL_ERROR_ADDR__FIREWALL_VIOLATION_MASK 0x80000000 980 + #define SRBM_FIREWALL_ERROR_ADDR__FIREWALL_VIOLATION__SHIFT 0x1f 981 + #define SRBM_DSM_TRIG_CNTL0__DSM_TRIG_ADDR_MASK 0xffff 982 + #define SRBM_DSM_TRIG_CNTL0__DSM_TRIG_ADDR__SHIFT 0x0 983 + #define SRBM_DSM_TRIG_CNTL0__DSM_TRIG_OP_MASK 0x10000 984 + #define SRBM_DSM_TRIG_CNTL0__DSM_TRIG_OP__SHIFT 0x10 985 + #define SRBM_DSM_TRIG_CNTL1__DSM_TRIG_WD_MASK 0xffffffff 986 + #define SRBM_DSM_TRIG_CNTL1__DSM_TRIG_WD__SHIFT 0x0 987 + #define SRBM_DSM_TRIG_MASK0__DSM_TRIG_ADDR_MASK_MASK 0xffff 988 + #define SRBM_DSM_TRIG_MASK0__DSM_TRIG_ADDR_MASK__SHIFT 0x0 989 + #define SRBM_DSM_TRIG_MASK0__DSM_TRIG_OP_MASK_MASK 0x10000 990 + #define SRBM_DSM_TRIG_MASK0__DSM_TRIG_OP_MASK__SHIFT 0x10 991 + #define SRBM_DSM_TRIG_MASK1__DSM_TRIG_WD_MASK_MASK 0xffffffff 992 + #define SRBM_DSM_TRIG_MASK1__DSM_TRIG_WD_MASK__SHIFT 0x0 993 + #define SRBM_PERFMON_CNTL__PERFMON_STATE_MASK 0xf 994 + #define SRBM_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 995 + #define SRBM_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK 0x300 996 + #define SRBM_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT 0x8 997 + #define SRBM_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x400 998 + #define SRBM_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa 999 + #define SRBM_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3f 1000 + #define SRBM_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 1001 + #define SRBM_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3f 1002 + #define SRBM_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 1003 + #define SRBM_PERFCOUNTER0_LO__PERF_COUNT0_LO_MASK 0xffffffff 1004 + #define SRBM_PERFCOUNTER0_LO__PERF_COUNT0_LO__SHIFT 0x0 1005 + #define SRBM_PERFCOUNTER0_HI__PERF_COUNT0_HI_MASK 0xffffffff 1006 + #define SRBM_PERFCOUNTER0_HI__PERF_COUNT0_HI__SHIFT 0x0 1007 + #define SRBM_PERFCOUNTER1_LO__PERF_COUNT1_LO_MASK 0xffffffff 1008 + #define SRBM_PERFCOUNTER1_LO__PERF_COUNT1_LO__SHIFT 0x0 1009 + #define SRBM_PERFCOUNTER1_HI__PERF_COUNT1_HI_MASK 0xffffffff 1010 + #define SRBM_PERFCOUNTER1_HI__PERF_COUNT1_HI__SHIFT 0x0 1011 + #define SRBM_CAM_INDEX__CAM_INDEX_MASK 0x3 1012 + #define SRBM_CAM_INDEX__CAM_INDEX__SHIFT 0x0 1013 + #define SRBM_CAM_DATA__CAM_ADDR_MASK 0xffff 1014 + #define SRBM_CAM_DATA__CAM_ADDR__SHIFT 0x0 1015 + #define SRBM_CAM_DATA__CAM_REMAPADDR_MASK 0xffff0000 1016 + #define SRBM_CAM_DATA__CAM_REMAPADDR__SHIFT 0x10 1017 + #define SRBM_MC_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff 1018 + #define SRBM_MC_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0 1019 + #define SRBM_MC_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000 1020 + #define SRBM_MC_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10 1021 + #define SRBM_MC_DOMAIN_ADDR1__ADDR_LO_MASK 0xffff 1022 + #define SRBM_MC_DOMAIN_ADDR1__ADDR_LO__SHIFT 0x0 1023 + #define SRBM_MC_DOMAIN_ADDR1__ADDR_HI_MASK 0xffff0000 1024 + #define SRBM_MC_DOMAIN_ADDR1__ADDR_HI__SHIFT 0x10 1025 + #define SRBM_MC_DOMAIN_ADDR2__ADDR_LO_MASK 0xffff 1026 + #define SRBM_MC_DOMAIN_ADDR2__ADDR_LO__SHIFT 0x0 1027 + #define SRBM_MC_DOMAIN_ADDR2__ADDR_HI_MASK 0xffff0000 1028 + #define SRBM_MC_DOMAIN_ADDR2__ADDR_HI__SHIFT 0x10 1029 + #define SRBM_MC_DOMAIN_ADDR3__ADDR_LO_MASK 0xffff 1030 + #define SRBM_MC_DOMAIN_ADDR3__ADDR_LO__SHIFT 0x0 1031 + #define SRBM_MC_DOMAIN_ADDR3__ADDR_HI_MASK 0xffff0000 1032 + #define SRBM_MC_DOMAIN_ADDR3__ADDR_HI__SHIFT 0x10 1033 + #define SRBM_MC_DOMAIN_ADDR4__ADDR_LO_MASK 0xffff 1034 + #define SRBM_MC_DOMAIN_ADDR4__ADDR_LO__SHIFT 0x0 1035 + #define SRBM_MC_DOMAIN_ADDR4__ADDR_HI_MASK 0xffff0000 1036 + #define SRBM_MC_DOMAIN_ADDR4__ADDR_HI__SHIFT 0x10 1037 + #define SRBM_MC_DOMAIN_ADDR5__ADDR_LO_MASK 0xffff 1038 + #define SRBM_MC_DOMAIN_ADDR5__ADDR_LO__SHIFT 0x0 1039 + #define SRBM_MC_DOMAIN_ADDR5__ADDR_HI_MASK 0xffff0000 1040 + #define SRBM_MC_DOMAIN_ADDR5__ADDR_HI__SHIFT 0x10 1041 + #define SRBM_MC_DOMAIN_ADDR6__ADDR_LO_MASK 0xffff 1042 + #define SRBM_MC_DOMAIN_ADDR6__ADDR_LO__SHIFT 0x0 1043 + #define SRBM_MC_DOMAIN_ADDR6__ADDR_HI_MASK 0xffff0000 1044 + #define SRBM_MC_DOMAIN_ADDR6__ADDR_HI__SHIFT 0x10 1045 + #define SRBM_SYS_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff 1046 + #define SRBM_SYS_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0 1047 + #define SRBM_SYS_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000 1048 + #define SRBM_SYS_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10 1049 + #define SRBM_SYS_DOMAIN_ADDR1__ADDR_LO_MASK 0xffff 1050 + #define SRBM_SYS_DOMAIN_ADDR1__ADDR_LO__SHIFT 0x0 1051 + #define SRBM_SYS_DOMAIN_ADDR1__ADDR_HI_MASK 0xffff0000 1052 + #define SRBM_SYS_DOMAIN_ADDR1__ADDR_HI__SHIFT 0x10 1053 + #define SRBM_SYS_DOMAIN_ADDR2__ADDR_LO_MASK 0xffff 1054 + #define SRBM_SYS_DOMAIN_ADDR2__ADDR_LO__SHIFT 0x0 1055 + #define SRBM_SYS_DOMAIN_ADDR2__ADDR_HI_MASK 0xffff0000 1056 + #define SRBM_SYS_DOMAIN_ADDR2__ADDR_HI__SHIFT 0x10 1057 + #define SRBM_SYS_DOMAIN_ADDR3__ADDR_LO_MASK 0xffff 1058 + #define SRBM_SYS_DOMAIN_ADDR3__ADDR_LO__SHIFT 0x0 1059 + #define SRBM_SYS_DOMAIN_ADDR3__ADDR_HI_MASK 0xffff0000 1060 + #define SRBM_SYS_DOMAIN_ADDR3__ADDR_HI__SHIFT 0x10 1061 + #define SRBM_SYS_DOMAIN_ADDR4__ADDR_LO_MASK 0xffff 1062 + #define SRBM_SYS_DOMAIN_ADDR4__ADDR_LO__SHIFT 0x0 1063 + #define SRBM_SYS_DOMAIN_ADDR4__ADDR_HI_MASK 0xffff0000 1064 + #define SRBM_SYS_DOMAIN_ADDR4__ADDR_HI__SHIFT 0x10 1065 + #define SRBM_SYS_DOMAIN_ADDR5__ADDR_LO_MASK 0xffff 1066 + #define SRBM_SYS_DOMAIN_ADDR5__ADDR_LO__SHIFT 0x0 1067 + #define SRBM_SYS_DOMAIN_ADDR5__ADDR_HI_MASK 0xffff0000 1068 + #define SRBM_SYS_DOMAIN_ADDR5__ADDR_HI__SHIFT 0x10 1069 + #define SRBM_SYS_DOMAIN_ADDR6__ADDR_LO_MASK 0xffff 1070 + #define SRBM_SYS_DOMAIN_ADDR6__ADDR_LO__SHIFT 0x0 1071 + #define SRBM_SYS_DOMAIN_ADDR6__ADDR_HI_MASK 0xffff0000 1072 + #define SRBM_SYS_DOMAIN_ADDR6__ADDR_HI__SHIFT 0x10 1073 + #define SRBM_SDMA_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff 1074 + #define SRBM_SDMA_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0 1075 + #define SRBM_SDMA_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000 1076 + #define SRBM_SDMA_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10 1077 + #define SRBM_SDMA_DOMAIN_ADDR1__ADDR_LO_MASK 0xffff 1078 + #define SRBM_SDMA_DOMAIN_ADDR1__ADDR_LO__SHIFT 0x0 1079 + #define SRBM_SDMA_DOMAIN_ADDR1__ADDR_HI_MASK 0xffff0000 1080 + #define SRBM_SDMA_DOMAIN_ADDR1__ADDR_HI__SHIFT 0x10 1081 + #define SRBM_SDMA_DOMAIN_ADDR2__ADDR_LO_MASK 0xffff 1082 + #define SRBM_SDMA_DOMAIN_ADDR2__ADDR_LO__SHIFT 0x0 1083 + #define SRBM_SDMA_DOMAIN_ADDR2__ADDR_HI_MASK 0xffff0000 1084 + #define SRBM_SDMA_DOMAIN_ADDR2__ADDR_HI__SHIFT 0x10 1085 + #define SRBM_SDMA_DOMAIN_ADDR3__ADDR_LO_MASK 0xffff 1086 + #define SRBM_SDMA_DOMAIN_ADDR3__ADDR_LO__SHIFT 0x0 1087 + #define SRBM_SDMA_DOMAIN_ADDR3__ADDR_HI_MASK 0xffff0000 1088 + #define SRBM_SDMA_DOMAIN_ADDR3__ADDR_HI__SHIFT 0x10 1089 + #define SRBM_UVD_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff 1090 + #define SRBM_UVD_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0 1091 + #define SRBM_UVD_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000 1092 + #define SRBM_UVD_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10 1093 + #define SRBM_UVD_DOMAIN_ADDR1__ADDR_LO_MASK 0xffff 1094 + #define SRBM_UVD_DOMAIN_ADDR1__ADDR_LO__SHIFT 0x0 1095 + #define SRBM_UVD_DOMAIN_ADDR1__ADDR_HI_MASK 0xffff0000 1096 + #define SRBM_UVD_DOMAIN_ADDR1__ADDR_HI__SHIFT 0x10 1097 + #define SRBM_UVD_DOMAIN_ADDR2__ADDR_LO_MASK 0xffff 1098 + #define SRBM_UVD_DOMAIN_ADDR2__ADDR_LO__SHIFT 0x0 1099 + #define SRBM_UVD_DOMAIN_ADDR2__ADDR_HI_MASK 0xffff0000 1100 + #define SRBM_UVD_DOMAIN_ADDR2__ADDR_HI__SHIFT 0x10 1101 + #define SRBM_VCE_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff 1102 + #define SRBM_VCE_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0 1103 + #define SRBM_VCE_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000 1104 + #define SRBM_VCE_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10 1105 + #define SRBM_VCE_DOMAIN_ADDR1__ADDR_LO_MASK 0xffff 1106 + #define SRBM_VCE_DOMAIN_ADDR1__ADDR_LO__SHIFT 0x0 1107 + #define SRBM_VCE_DOMAIN_ADDR1__ADDR_HI_MASK 0xffff0000 1108 + #define SRBM_VCE_DOMAIN_ADDR1__ADDR_HI__SHIFT 0x10 1109 + #define SRBM_VCE_DOMAIN_ADDR2__ADDR_LO_MASK 0xffff 1110 + #define SRBM_VCE_DOMAIN_ADDR2__ADDR_LO__SHIFT 0x0 1111 + #define SRBM_VCE_DOMAIN_ADDR2__ADDR_HI_MASK 0xffff0000 1112 + #define SRBM_VCE_DOMAIN_ADDR2__ADDR_HI__SHIFT 0x10 1113 + #define SRBM_SAM_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff 1114 + #define SRBM_SAM_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0 1115 + #define SRBM_SAM_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000 1116 + #define SRBM_SAM_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10 1117 + #define SRBM_SAM_DOMAIN_ADDR1__ADDR_LO_MASK 0xffff 1118 + #define SRBM_SAM_DOMAIN_ADDR1__ADDR_LO__SHIFT 0x0 1119 + #define SRBM_SAM_DOMAIN_ADDR1__ADDR_HI_MASK 0xffff0000 1120 + #define SRBM_SAM_DOMAIN_ADDR1__ADDR_HI__SHIFT 0x10 1121 + #define SRBM_SAM_DOMAIN_ADDR2__ADDR_LO_MASK 0xffff 1122 + #define SRBM_SAM_DOMAIN_ADDR2__ADDR_LO__SHIFT 0x0 1123 + #define SRBM_SAM_DOMAIN_ADDR2__ADDR_HI_MASK 0xffff0000 1124 + #define SRBM_SAM_DOMAIN_ADDR2__ADDR_HI__SHIFT 0x10 1125 + #define SRBM_ISP_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff 1126 + #define SRBM_ISP_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0 1127 + #define SRBM_ISP_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000 1128 + #define SRBM_ISP_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10 1129 + #define SRBM_ISP_DOMAIN_ADDR1__ADDR_LO_MASK 0xffff 1130 + #define SRBM_ISP_DOMAIN_ADDR1__ADDR_LO__SHIFT 0x0 1131 + #define SRBM_ISP_DOMAIN_ADDR1__ADDR_HI_MASK 0xffff0000 1132 + #define SRBM_ISP_DOMAIN_ADDR1__ADDR_HI__SHIFT 0x10 1133 + #define SRBM_ISP_DOMAIN_ADDR2__ADDR_LO_MASK 0xffff 1134 + #define SRBM_ISP_DOMAIN_ADDR2__ADDR_LO__SHIFT 0x0 1135 + #define SRBM_ISP_DOMAIN_ADDR2__ADDR_HI_MASK 0xffff0000 1136 + #define SRBM_ISP_DOMAIN_ADDR2__ADDR_HI__SHIFT 0x10 1137 + #define SRBM_VP8_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff 1138 + #define SRBM_VP8_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0 1139 + #define SRBM_VP8_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000 1140 + #define SRBM_VP8_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10 1141 + #define SYS_GRBM_GFX_INDEX_SELECT__SYS_GRBM_GFX_INDEX_SEL_MASK 0xf 1142 + #define SYS_GRBM_GFX_INDEX_SELECT__SYS_GRBM_GFX_INDEX_SEL__SHIFT 0x0 1143 + #define SYS_GRBM_GFX_INDEX_DATA__INSTANCE_INDEX_MASK 0xff 1144 + #define SYS_GRBM_GFX_INDEX_DATA__INSTANCE_INDEX__SHIFT 0x0 1145 + #define SYS_GRBM_GFX_INDEX_DATA__SH_INDEX_MASK 0xff00 1146 + #define SYS_GRBM_GFX_INDEX_DATA__SH_INDEX__SHIFT 0x8 1147 + #define SYS_GRBM_GFX_INDEX_DATA__SE_INDEX_MASK 0xff0000 1148 + #define SYS_GRBM_GFX_INDEX_DATA__SE_INDEX__SHIFT 0x10 1149 + #define SYS_GRBM_GFX_INDEX_DATA__SH_BROADCAST_WRITES_MASK 0x20000000 1150 + #define SYS_GRBM_GFX_INDEX_DATA__SH_BROADCAST_WRITES__SHIFT 0x1d 1151 + #define SYS_GRBM_GFX_INDEX_DATA__INSTANCE_BROADCAST_WRITES_MASK 0x40000000 1152 + #define SYS_GRBM_GFX_INDEX_DATA__INSTANCE_BROADCAST_WRITES__SHIFT 0x1e 1153 + #define SYS_GRBM_GFX_INDEX_DATA__SE_BROADCAST_WRITES_MASK 0x80000000 1154 + #define SYS_GRBM_GFX_INDEX_DATA__SE_BROADCAST_WRITES__SHIFT 0x1f 1155 + #define SRBM_GFX_CNTL_SELECT__SRBM_GFX_CNTL_SEL_MASK 0xf 1156 + #define SRBM_GFX_CNTL_SELECT__SRBM_GFX_CNTL_SEL__SHIFT 0x0 1157 + #define SRBM_GFX_CNTL_DATA__PIPEID_MASK 0x3 1158 + #define SRBM_GFX_CNTL_DATA__PIPEID__SHIFT 0x0 1159 + #define SRBM_GFX_CNTL_DATA__MEID_MASK 0xc 1160 + #define SRBM_GFX_CNTL_DATA__MEID__SHIFT 0x2 1161 + #define SRBM_GFX_CNTL_DATA__VMID_MASK 0xf0 1162 + #define SRBM_GFX_CNTL_DATA__VMID__SHIFT 0x4 1163 + #define SRBM_GFX_CNTL_DATA__QUEUEID_MASK 0x700 1164 + #define SRBM_GFX_CNTL_DATA__QUEUEID__SHIFT 0x8 1165 + #define SRBM_VF_ENABLE__VF_ENABLE_MASK 0x1 1166 + #define SRBM_VF_ENABLE__VF_ENABLE__SHIFT 0x0 1167 + #define SRBM_VIRT_CNTL__VF_WRITE_ENABLE_MASK 0x1 1168 + #define SRBM_VIRT_CNTL__VF_WRITE_ENABLE__SHIFT 0x0 1169 + #define SRBM_VIRT_RESET_REQ__VF_MASK 0xffff 1170 + #define SRBM_VIRT_RESET_REQ__VF__SHIFT 0x0 1171 + #define SRBM_VIRT_RESET_REQ__PF_MASK 0x80000000 1172 + #define SRBM_VIRT_RESET_REQ__PF__SHIFT 0x1f 1173 + #define CC_DRM_ID_STRAPS__DEVICE_ID_MASK 0xffff0 1174 + #define CC_DRM_ID_STRAPS__DEVICE_ID__SHIFT 0x4 1175 + #define CC_DRM_ID_STRAPS__MAJOR_REV_ID_MASK 0xf00000 1176 + #define CC_DRM_ID_STRAPS__MAJOR_REV_ID__SHIFT 0x14 1177 + #define CC_DRM_ID_STRAPS__MINOR_REV_ID_MASK 0xf000000 1178 + #define CC_DRM_ID_STRAPS__MINOR_REV_ID__SHIFT 0x18 1179 + #define CC_DRM_ID_STRAPS__ATI_REV_ID_MASK 0xf0000000 1180 + #define CC_DRM_ID_STRAPS__ATI_REV_ID__SHIFT 0x1c 1181 + #define DH_TEST__DH_TEST_MASK 0x1 1182 + #define DH_TEST__DH_TEST__SHIFT 0x0 1183 + #define KHFS0__RESERVED_MASK 0xffffffff 1184 + #define KHFS0__RESERVED__SHIFT 0x0 1185 + #define KHFS1__RESERVED_MASK 0xffffffff 1186 + #define KHFS1__RESERVED__SHIFT 0x0 1187 + #define KHFS2__RESERVED_MASK 0xffffffff 1188 + #define KHFS2__RESERVED__SHIFT 0x0 1189 + #define KHFS3__RESERVED_MASK 0xffffffff 1190 + #define KHFS3__RESERVED__SHIFT 0x0 1191 + #define KSESSION0__RESERVED_MASK 0xffffffff 1192 + #define KSESSION0__RESERVED__SHIFT 0x0 1193 + #define KSESSION1__RESERVED_MASK 0xffffffff 1194 + #define KSESSION1__RESERVED__SHIFT 0x0 1195 + #define KSESSION2__RESERVED_MASK 0xffffffff 1196 + #define KSESSION2__RESERVED__SHIFT 0x0 1197 + #define KSESSION3__RESERVED_MASK 0xffffffff 1198 + #define KSESSION3__RESERVED__SHIFT 0x0 1199 + #define KSIG0__RESERVED_MASK 0xffffffff 1200 + #define KSIG0__RESERVED__SHIFT 0x0 1201 + #define KSIG1__RESERVED_MASK 0xffffffff 1202 + #define KSIG1__RESERVED__SHIFT 0x0 1203 + #define KSIG2__RESERVED_MASK 0xffffffff 1204 + #define KSIG2__RESERVED__SHIFT 0x0 1205 + #define KSIG3__RESERVED_MASK 0xffffffff 1206 + #define KSIG3__RESERVED__SHIFT 0x0 1207 + #define EXP0__RESERVED_MASK 0xffffffff 1208 + #define EXP0__RESERVED__SHIFT 0x0 1209 + #define EXP1__RESERVED_MASK 0xffffffff 1210 + #define EXP1__RESERVED__SHIFT 0x0 1211 + #define EXP2__RESERVED_MASK 0xffffffff 1212 + #define EXP2__RESERVED__SHIFT 0x0 1213 + #define EXP3__RESERVED_MASK 0xffffffff 1214 + #define EXP3__RESERVED__SHIFT 0x0 1215 + #define EXP4__RESERVED_MASK 0xffffffff 1216 + #define EXP4__RESERVED__SHIFT 0x0 1217 + #define EXP5__RESERVED_MASK 0xffffffff 1218 + #define EXP5__RESERVED__SHIFT 0x0 1219 + #define EXP6__RESERVED_MASK 0xffffffff 1220 + #define EXP6__RESERVED__SHIFT 0x0 1221 + #define EXP7__RESERVED_MASK 0xffffffff 1222 + #define EXP7__RESERVED__SHIFT 0x0 1223 + #define LX0__RESERVED_MASK 0xffffffff 1224 + #define LX0__RESERVED__SHIFT 0x0 1225 + #define LX1__RESERVED_MASK 0xffffffff 1226 + #define LX1__RESERVED__SHIFT 0x0 1227 + #define LX2__RESERVED_MASK 0xffffffff 1228 + #define LX2__RESERVED__SHIFT 0x0 1229 + #define LX3__RESERVED_MASK 0xffffffff 1230 + #define LX3__RESERVED__SHIFT 0x0 1231 + #define CLIENT2_K0__RESERVED_MASK 0xffffffff 1232 + #define CLIENT2_K0__RESERVED__SHIFT 0x0 1233 + #define CLIENT2_K1__RESERVED_MASK 0xffffffff 1234 + #define CLIENT2_K1__RESERVED__SHIFT 0x0 1235 + #define CLIENT2_K2__RESERVED_MASK 0xffffffff 1236 + #define CLIENT2_K2__RESERVED__SHIFT 0x0 1237 + #define CLIENT2_K3__RESERVED_MASK 0xffffffff 1238 + #define CLIENT2_K3__RESERVED__SHIFT 0x0 1239 + #define CLIENT2_CK0__RESERVED_MASK 0xffffffff 1240 + #define CLIENT2_CK0__RESERVED__SHIFT 0x0 1241 + #define CLIENT2_CK1__RESERVED_MASK 0xffffffff 1242 + #define CLIENT2_CK1__RESERVED__SHIFT 0x0 1243 + #define CLIENT2_CK2__RESERVED_MASK 0xffffffff 1244 + #define CLIENT2_CK2__RESERVED__SHIFT 0x0 1245 + #define CLIENT2_CK3__RESERVED_MASK 0xffffffff 1246 + #define CLIENT2_CK3__RESERVED__SHIFT 0x0 1247 + #define CLIENT2_CD0__RESERVED_MASK 0xffffffff 1248 + #define CLIENT2_CD0__RESERVED__SHIFT 0x0 1249 + #define CLIENT2_CD1__RESERVED_MASK 0xffffffff 1250 + #define CLIENT2_CD1__RESERVED__SHIFT 0x0 1251 + #define CLIENT2_CD2__RESERVED_MASK 0xffffffff 1252 + #define CLIENT2_CD2__RESERVED__SHIFT 0x0 1253 + #define CLIENT2_CD3__RESERVED_MASK 0xffffffff 1254 + #define CLIENT2_CD3__RESERVED__SHIFT 0x0 1255 + #define CLIENT2_BM__RESERVED_MASK 0xffffffff 1256 + #define CLIENT2_BM__RESERVED__SHIFT 0x0 1257 + #define CLIENT2_OFFSET__RESERVED_MASK 0xffffffff 1258 + #define CLIENT2_OFFSET__RESERVED__SHIFT 0x0 1259 + #define CLIENT2_STATUS__RESERVED_MASK 0xffffffff 1260 + #define CLIENT2_STATUS__RESERVED__SHIFT 0x0 1261 + #define CLIENT0_K0__RESERVED_MASK 0xffffffff 1262 + #define CLIENT0_K0__RESERVED__SHIFT 0x0 1263 + #define CLIENT0_K1__RESERVED_MASK 0xffffffff 1264 + #define CLIENT0_K1__RESERVED__SHIFT 0x0 1265 + #define CLIENT0_K2__RESERVED_MASK 0xffffffff 1266 + #define CLIENT0_K2__RESERVED__SHIFT 0x0 1267 + #define CLIENT0_K3__RESERVED_MASK 0xffffffff 1268 + #define CLIENT0_K3__RESERVED__SHIFT 0x0 1269 + #define CLIENT0_CK0__RESERVED_MASK 0xffffffff 1270 + #define CLIENT0_CK0__RESERVED__SHIFT 0x0 1271 + #define CLIENT0_CK1__RESERVED_MASK 0xffffffff 1272 + #define CLIENT0_CK1__RESERVED__SHIFT 0x0 1273 + #define CLIENT0_CK2__RESERVED_MASK 0xffffffff 1274 + #define CLIENT0_CK2__RESERVED__SHIFT 0x0 1275 + #define CLIENT0_CK3__RESERVED_MASK 0xffffffff 1276 + #define CLIENT0_CK3__RESERVED__SHIFT 0x0 1277 + #define CLIENT0_CD0__RESERVED_MASK 0xffffffff 1278 + #define CLIENT0_CD0__RESERVED__SHIFT 0x0 1279 + #define CLIENT0_CD1__RESERVED_MASK 0xffffffff 1280 + #define CLIENT0_CD1__RESERVED__SHIFT 0x0 1281 + #define CLIENT0_CD2__RESERVED_MASK 0xffffffff 1282 + #define CLIENT0_CD2__RESERVED__SHIFT 0x0 1283 + #define CLIENT0_CD3__RESERVED_MASK 0xffffffff 1284 + #define CLIENT0_CD3__RESERVED__SHIFT 0x0 1285 + #define CLIENT0_BM__RESERVED_MASK 0xffffffff 1286 + #define CLIENT0_BM__RESERVED__SHIFT 0x0 1287 + #define CLIENT0_OFFSET__RESERVED_MASK 0xffffffff 1288 + #define CLIENT0_OFFSET__RESERVED__SHIFT 0x0 1289 + #define CLIENT0_STATUS__RESERVED_MASK 0xffffffff 1290 + #define CLIENT0_STATUS__RESERVED__SHIFT 0x0 1291 + #define CLIENT1_K0__RESERVED_MASK 0xffffffff 1292 + #define CLIENT1_K0__RESERVED__SHIFT 0x0 1293 + #define CLIENT1_K1__RESERVED_MASK 0xffffffff 1294 + #define CLIENT1_K1__RESERVED__SHIFT 0x0 1295 + #define CLIENT1_K2__RESERVED_MASK 0xffffffff 1296 + #define CLIENT1_K2__RESERVED__SHIFT 0x0 1297 + #define CLIENT1_K3__RESERVED_MASK 0xffffffff 1298 + #define CLIENT1_K3__RESERVED__SHIFT 0x0 1299 + #define CLIENT1_CK0__RESERVED_MASK 0xffffffff 1300 + #define CLIENT1_CK0__RESERVED__SHIFT 0x0 1301 + #define CLIENT1_CK1__RESERVED_MASK 0xffffffff 1302 + #define CLIENT1_CK1__RESERVED__SHIFT 0x0 1303 + #define CLIENT1_CK2__RESERVED_MASK 0xffffffff 1304 + #define CLIENT1_CK2__RESERVED__SHIFT 0x0 1305 + #define CLIENT1_CK3__RESERVED_MASK 0xffffffff 1306 + #define CLIENT1_CK3__RESERVED__SHIFT 0x0 1307 + #define CLIENT1_CD0__RESERVED_MASK 0xffffffff 1308 + #define CLIENT1_CD0__RESERVED__SHIFT 0x0 1309 + #define CLIENT1_CD1__RESERVED_MASK 0xffffffff 1310 + #define CLIENT1_CD1__RESERVED__SHIFT 0x0 1311 + #define CLIENT1_CD2__RESERVED_MASK 0xffffffff 1312 + #define CLIENT1_CD2__RESERVED__SHIFT 0x0 1313 + #define CLIENT1_CD3__RESERVED_MASK 0xffffffff 1314 + #define CLIENT1_CD3__RESERVED__SHIFT 0x0 1315 + #define CLIENT1_BM__RESERVED_MASK 0xffffffff 1316 + #define CLIENT1_BM__RESERVED__SHIFT 0x0 1317 + #define CLIENT1_OFFSET__RESERVED_MASK 0xffffffff 1318 + #define CLIENT1_OFFSET__RESERVED__SHIFT 0x0 1319 + #define CLIENT1_PORT_STATUS__RESERVED_MASK 0xffffffff 1320 + #define CLIENT1_PORT_STATUS__RESERVED__SHIFT 0x0 1321 + #define KEFUSE0__RESERVED_MASK 0xffffffff 1322 + #define KEFUSE0__RESERVED__SHIFT 0x0 1323 + #define KEFUSE1__RESERVED_MASK 0xffffffff 1324 + #define KEFUSE1__RESERVED__SHIFT 0x0 1325 + #define KEFUSE2__RESERVED_MASK 0xffffffff 1326 + #define KEFUSE2__RESERVED__SHIFT 0x0 1327 + #define KEFUSE3__RESERVED_MASK 0xffffffff 1328 + #define KEFUSE3__RESERVED__SHIFT 0x0 1329 + #define HFS_SEED0__RESERVED_MASK 0xffffffff 1330 + #define HFS_SEED0__RESERVED__SHIFT 0x0 1331 + #define HFS_SEED1__RESERVED_MASK 0xffffffff 1332 + #define HFS_SEED1__RESERVED__SHIFT 0x0 1333 + #define HFS_SEED2__RESERVED_MASK 0xffffffff 1334 + #define HFS_SEED2__RESERVED__SHIFT 0x0 1335 + #define HFS_SEED3__RESERVED_MASK 0xffffffff 1336 + #define HFS_SEED3__RESERVED__SHIFT 0x0 1337 + #define RINGOSC_MASK__MASK_MASK 0xffff 1338 + #define RINGOSC_MASK__MASK__SHIFT 0x0 1339 + #define CLIENT0_OFFSET_HI__RESERVED_MASK 0xffffffff 1340 + #define CLIENT0_OFFSET_HI__RESERVED__SHIFT 0x0 1341 + #define CLIENT1_OFFSET_HI__RESERVED_MASK 0xffffffff 1342 + #define CLIENT1_OFFSET_HI__RESERVED__SHIFT 0x0 1343 + #define CLIENT2_OFFSET_HI__RESERVED_MASK 0xffffffff 1344 + #define CLIENT2_OFFSET_HI__RESERVED__SHIFT 0x0 1345 + #define SPU_PORT_STATUS__RESERVED_MASK 0xffffffff 1346 + #define SPU_PORT_STATUS__RESERVED__SHIFT 0x0 1347 + #define CLIENT3_OFFSET_HI__RESERVED_MASK 0xffffffff 1348 + #define CLIENT3_OFFSET_HI__RESERVED__SHIFT 0x0 1349 + #define CLIENT3_K0__RESERVED_MASK 0xffffffff 1350 + #define CLIENT3_K0__RESERVED__SHIFT 0x0 1351 + #define CLIENT3_K1__RESERVED_MASK 0xffffffff 1352 + #define CLIENT3_K1__RESERVED__SHIFT 0x0 1353 + #define CLIENT3_K2__RESERVED_MASK 0xffffffff 1354 + #define CLIENT3_K2__RESERVED__SHIFT 0x0 1355 + #define CLIENT3_K3__RESERVED_MASK 0xffffffff 1356 + #define CLIENT3_K3__RESERVED__SHIFT 0x0 1357 + #define CLIENT3_CK0__RESERVED_MASK 0xffffffff 1358 + #define CLIENT3_CK0__RESERVED__SHIFT 0x0 1359 + #define CLIENT3_CK1__RESERVED_MASK 0xffffffff 1360 + #define CLIENT3_CK1__RESERVED__SHIFT 0x0 1361 + #define CLIENT3_CK2__RESERVED_MASK 0xffffffff 1362 + #define CLIENT3_CK2__RESERVED__SHIFT 0x0 1363 + #define CLIENT3_CK3__RESERVED_MASK 0xffffffff 1364 + #define CLIENT3_CK3__RESERVED__SHIFT 0x0 1365 + #define CLIENT3_CD0__RESERVED_MASK 0xffffffff 1366 + #define CLIENT3_CD0__RESERVED__SHIFT 0x0 1367 + #define CLIENT3_CD1__RESERVED_MASK 0xffffffff 1368 + #define CLIENT3_CD1__RESERVED__SHIFT 0x0 1369 + #define CLIENT3_CD2__RESERVED_MASK 0xffffffff 1370 + #define CLIENT3_CD2__RESERVED__SHIFT 0x0 1371 + #define CLIENT3_CD3__RESERVED_MASK 0xffffffff 1372 + #define CLIENT3_CD3__RESERVED__SHIFT 0x0 1373 + #define CLIENT3_BM__RESERVED_MASK 0xffffffff 1374 + #define CLIENT3_BM__RESERVED__SHIFT 0x0 1375 + #define CLIENT3_OFFSET__RESERVED_MASK 0xffffffff 1376 + #define CLIENT3_OFFSET__RESERVED__SHIFT 0x0 1377 + #define CLIENT3_STATUS__RESERVED_MASK 0xffffffff 1378 + #define CLIENT3_STATUS__RESERVED__SHIFT 0x0 1379 + #define CLIENT4_OFFSET_HI__RESERVED_MASK 0xffffffff 1380 + #define CLIENT4_OFFSET_HI__RESERVED__SHIFT 0x0 1381 + #define CLIENT4_K0__RESERVED_MASK 0xffffffff 1382 + #define CLIENT4_K0__RESERVED__SHIFT 0x0 1383 + #define CLIENT4_K1__RESERVED_MASK 0xffffffff 1384 + #define CLIENT4_K1__RESERVED__SHIFT 0x0 1385 + #define CLIENT4_K2__RESERVED_MASK 0xffffffff 1386 + #define CLIENT4_K2__RESERVED__SHIFT 0x0 1387 + #define CLIENT4_K3__RESERVED_MASK 0xffffffff 1388 + #define CLIENT4_K3__RESERVED__SHIFT 0x0 1389 + #define CLIENT4_CK0__RESERVED_MASK 0xffffffff 1390 + #define CLIENT4_CK0__RESERVED__SHIFT 0x0 1391 + #define CLIENT4_CK1__RESERVED_MASK 0xffffffff 1392 + #define CLIENT4_CK1__RESERVED__SHIFT 0x0 1393 + #define CLIENT4_CK2__RESERVED_MASK 0xffffffff 1394 + #define CLIENT4_CK2__RESERVED__SHIFT 0x0 1395 + #define CLIENT4_CK3__RESERVED_MASK 0xffffffff 1396 + #define CLIENT4_CK3__RESERVED__SHIFT 0x0 1397 + #define CLIENT4_CD0__RESERVED_MASK 0xffffffff 1398 + #define CLIENT4_CD0__RESERVED__SHIFT 0x0 1399 + #define CLIENT4_CD1__RESERVED_MASK 0xffffffff 1400 + #define CLIENT4_CD1__RESERVED__SHIFT 0x0 1401 + #define CLIENT4_CD2__RESERVED_MASK 0xffffffff 1402 + #define CLIENT4_CD2__RESERVED__SHIFT 0x0 1403 + #define CLIENT4_CD3__RESERVED_MASK 0xffffffff 1404 + #define CLIENT4_CD3__RESERVED__SHIFT 0x0 1405 + #define CLIENT4_BM__RESERVED_MASK 0xffffffff 1406 + #define CLIENT4_BM__RESERVED__SHIFT 0x0 1407 + #define CLIENT4_OFFSET__RESERVED_MASK 0xffffffff 1408 + #define CLIENT4_OFFSET__RESERVED__SHIFT 0x0 1409 + #define CLIENT4_STATUS__RESERVED_MASK 0xffffffff 1410 + #define CLIENT4_STATUS__RESERVED__SHIFT 0x0 1411 + #define DC_TEST_DEBUG_INDEX__DC_TEST_DEBUG_INDEX_MASK 0xff 1412 + #define DC_TEST_DEBUG_INDEX__DC_TEST_DEBUG_INDEX__SHIFT 0x0 1413 + #define DC_TEST_DEBUG_INDEX__DC_TEST_DEBUG_WRITE_EN_MASK 0x100 1414 + #define DC_TEST_DEBUG_INDEX__DC_TEST_DEBUG_WRITE_EN__SHIFT 0x8 1415 + #define DC_TEST_DEBUG_DATA__DC_TEST_DEBUG_DATA_MASK 0xffffffff 1416 + #define DC_TEST_DEBUG_DATA__DC_TEST_DEBUG_DATA__SHIFT 0x0 1417 + #define SDMA0_UCODE_ADDR__VALUE_MASK 0x1fff 1418 + #define SDMA0_UCODE_ADDR__VALUE__SHIFT 0x0 1419 + #define SDMA0_UCODE_DATA__VALUE_MASK 0xffffffff 1420 + #define SDMA0_UCODE_DATA__VALUE__SHIFT 0x0 1421 + #define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x100 1422 + #define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8 1423 + #define SDMA0_POWER_CNTL__MEM_POWER_LS_EN_MASK 0x200 1424 + #define SDMA0_POWER_CNTL__MEM_POWER_LS_EN__SHIFT 0x9 1425 + #define SDMA0_POWER_CNTL__MEM_POWER_DS_EN_MASK 0x400 1426 + #define SDMA0_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa 1427 + #define SDMA0_POWER_CNTL__MEM_POWER_SD_EN_MASK 0x800 1428 + #define SDMA0_POWER_CNTL__MEM_POWER_SD_EN__SHIFT 0xb 1429 + #define SDMA0_POWER_CNTL__MEM_POWER_DELAY_MASK 0x3ff000 1430 + #define SDMA0_POWER_CNTL__MEM_POWER_DELAY__SHIFT 0xc 1431 + #define SDMA0_CLK_CTRL__ON_DELAY_MASK 0xf 1432 + #define SDMA0_CLK_CTRL__ON_DELAY__SHIFT 0x0 1433 + #define SDMA0_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 1434 + #define SDMA0_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 1435 + #define SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 1436 + #define SDMA0_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 1437 + #define SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000 1438 + #define SDMA0_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 1439 + #define SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000 1440 + #define SDMA0_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a 1441 + #define SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 1442 + #define SDMA0_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b 1443 + #define SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000 1444 + #define SDMA0_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c 1445 + #define SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000 1446 + #define SDMA0_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d 1447 + #define SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000 1448 + #define SDMA0_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e 1449 + #define SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000 1450 + #define SDMA0_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f 1451 + #define SDMA0_CNTL__TRAP_ENABLE_MASK 0x1 1452 + #define SDMA0_CNTL__TRAP_ENABLE__SHIFT 0x0 1453 + #define SDMA0_CNTL__ATC_L1_ENABLE_MASK 0x2 1454 + #define SDMA0_CNTL__ATC_L1_ENABLE__SHIFT 0x1 1455 + #define SDMA0_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x4 1456 + #define SDMA0_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2 1457 + #define SDMA0_CNTL__DATA_SWAP_ENABLE_MASK 0x8 1458 + #define SDMA0_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3 1459 + #define SDMA0_CNTL__FENCE_SWAP_ENABLE_MASK 0x10 1460 + #define SDMA0_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4 1461 + #define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x20 1462 + #define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5 1463 + #define SDMA0_CNTL__MC_WRREQ_CREDIT_MASK 0x1f800 1464 + #define SDMA0_CNTL__MC_WRREQ_CREDIT__SHIFT 0xb 1465 + #define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x20000 1466 + #define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11 1467 + #define SDMA0_CNTL__AUTO_CTXSW_ENABLE_MASK 0x40000 1468 + #define SDMA0_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12 1469 + #define SDMA0_CNTL__MC_RDREQ_CREDIT_MASK 0xfc00000 1470 + #define SDMA0_CNTL__MC_RDREQ_CREDIT__SHIFT 0x16 1471 + #define SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000 1472 + #define SDMA0_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c 1473 + #define SDMA0_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000 1474 + #define SDMA0_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d 1475 + #define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000 1476 + #define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e 1477 + #define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x1 1478 + #define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0 1479 + #define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x2 1480 + #define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1 1481 + #define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x4 1482 + #define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2 1483 + #define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x10000 1484 + #define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10 1485 + #define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x100000 1486 + #define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14 1487 + #define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x800000 1488 + #define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17 1489 + #define SDMA0_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK 0xc000000 1490 + #define SDMA0_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT 0x1a 1491 + #define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK 0x30000000 1492 + #define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT 0x1c 1493 + #define SDMA0_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK 0xc0000000 1494 + #define SDMA0_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT 0x1e 1495 + #define SDMA0_TILING_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 1496 + #define SDMA0_TILING_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 1497 + #define SDMA0_HASH__CHANNEL_BITS_MASK 0x7 1498 + #define SDMA0_HASH__CHANNEL_BITS__SHIFT 0x0 1499 + #define SDMA0_HASH__BANK_BITS_MASK 0x70 1500 + #define SDMA0_HASH__BANK_BITS__SHIFT 0x4 1501 + #define SDMA0_HASH__CHANNEL_XOR_COUNT_MASK 0x700 1502 + #define SDMA0_HASH__CHANNEL_XOR_COUNT__SHIFT 0x8 1503 + #define SDMA0_HASH__BANK_XOR_COUNT_MASK 0x7000 1504 + #define SDMA0_HASH__BANK_XOR_COUNT__SHIFT 0xc 1505 + #define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xffffffff 1506 + #define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0 1507 + #define SDMA0_RB_RPTR_FETCH__OFFSET_MASK 0xfffffffc 1508 + #define SDMA0_RB_RPTR_FETCH__OFFSET__SHIFT 0x2 1509 + #define SDMA0_IB_OFFSET_FETCH__OFFSET_MASK 0x3ffffc 1510 + #define SDMA0_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2 1511 + #define SDMA0_PROGRAM__STREAM_MASK 0xffffffff 1512 + #define SDMA0_PROGRAM__STREAM__SHIFT 0x0 1513 + #define SDMA0_STATUS_REG__IDLE_MASK 0x1 1514 + #define SDMA0_STATUS_REG__IDLE__SHIFT 0x0 1515 + #define SDMA0_STATUS_REG__REG_IDLE_MASK 0x2 1516 + #define SDMA0_STATUS_REG__REG_IDLE__SHIFT 0x1 1517 + #define SDMA0_STATUS_REG__RB_EMPTY_MASK 0x4 1518 + #define SDMA0_STATUS_REG__RB_EMPTY__SHIFT 0x2 1519 + #define SDMA0_STATUS_REG__RB_FULL_MASK 0x8 1520 + #define SDMA0_STATUS_REG__RB_FULL__SHIFT 0x3 1521 + #define SDMA0_STATUS_REG__RB_CMD_IDLE_MASK 0x10 1522 + #define SDMA0_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4 1523 + #define SDMA0_STATUS_REG__RB_CMD_FULL_MASK 0x20 1524 + #define SDMA0_STATUS_REG__RB_CMD_FULL__SHIFT 0x5 1525 + #define SDMA0_STATUS_REG__IB_CMD_IDLE_MASK 0x40 1526 + #define SDMA0_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6 1527 + #define SDMA0_STATUS_REG__IB_CMD_FULL_MASK 0x80 1528 + #define SDMA0_STATUS_REG__IB_CMD_FULL__SHIFT 0x7 1529 + #define SDMA0_STATUS_REG__BLOCK_IDLE_MASK 0x100 1530 + #define SDMA0_STATUS_REG__BLOCK_IDLE__SHIFT 0x8 1531 + #define SDMA0_STATUS_REG__INSIDE_IB_MASK 0x200 1532 + #define SDMA0_STATUS_REG__INSIDE_IB__SHIFT 0x9 1533 + #define SDMA0_STATUS_REG__EX_IDLE_MASK 0x400 1534 + #define SDMA0_STATUS_REG__EX_IDLE__SHIFT 0xa 1535 + #define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x800 1536 + #define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb 1537 + #define SDMA0_STATUS_REG__PACKET_READY_MASK 0x1000 1538 + #define SDMA0_STATUS_REG__PACKET_READY__SHIFT 0xc 1539 + #define SDMA0_STATUS_REG__MC_WR_IDLE_MASK 0x2000 1540 + #define SDMA0_STATUS_REG__MC_WR_IDLE__SHIFT 0xd 1541 + #define SDMA0_STATUS_REG__SRBM_IDLE_MASK 0x4000 1542 + #define SDMA0_STATUS_REG__SRBM_IDLE__SHIFT 0xe 1543 + #define SDMA0_STATUS_REG__CONTEXT_EMPTY_MASK 0x8000 1544 + #define SDMA0_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf 1545 + #define SDMA0_STATUS_REG__DELTA_RPTR_FULL_MASK 0x10000 1546 + #define SDMA0_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10 1547 + #define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x20000 1548 + #define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11 1549 + #define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x40000 1550 + #define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12 1551 + #define SDMA0_STATUS_REG__MC_RD_IDLE_MASK 0x80000 1552 + #define SDMA0_STATUS_REG__MC_RD_IDLE__SHIFT 0x13 1553 + #define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x100000 1554 + #define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14 1555 + #define SDMA0_STATUS_REG__MC_RD_RET_STALL_MASK 0x200000 1556 + #define SDMA0_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15 1557 + #define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x400000 1558 + #define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16 1559 + #define SDMA0_STATUS_REG__PREV_CMD_IDLE_MASK 0x2000000 1560 + #define SDMA0_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19 1561 + #define SDMA0_STATUS_REG__SEM_IDLE_MASK 0x4000000 1562 + #define SDMA0_STATUS_REG__SEM_IDLE__SHIFT 0x1a 1563 + #define SDMA0_STATUS_REG__SEM_REQ_STALL_MASK 0x8000000 1564 + #define SDMA0_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b 1565 + #define SDMA0_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000 1566 + #define SDMA0_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c 1567 + #define SDMA0_STATUS_REG__INT_IDLE_MASK 0x40000000 1568 + #define SDMA0_STATUS_REG__INT_IDLE__SHIFT 0x1e 1569 + #define SDMA0_STATUS_REG__INT_REQ_STALL_MASK 0x80000000 1570 + #define SDMA0_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f 1571 + #define SDMA0_STATUS1_REG__CE_WREQ_IDLE_MASK 0x1 1572 + #define SDMA0_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0 1573 + #define SDMA0_STATUS1_REG__CE_WR_IDLE_MASK 0x2 1574 + #define SDMA0_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 1575 + #define SDMA0_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x4 1576 + #define SDMA0_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2 1577 + #define SDMA0_STATUS1_REG__CE_RREQ_IDLE_MASK 0x8 1578 + #define SDMA0_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3 1579 + #define SDMA0_STATUS1_REG__CE_OUT_IDLE_MASK 0x10 1580 + #define SDMA0_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4 1581 + #define SDMA0_STATUS1_REG__CE_IN_IDLE_MASK 0x20 1582 + #define SDMA0_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5 1583 + #define SDMA0_STATUS1_REG__CE_DST_IDLE_MASK 0x40 1584 + #define SDMA0_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6 1585 + #define SDMA0_STATUS1_REG__CE_CMD_IDLE_MASK 0x200 1586 + #define SDMA0_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9 1587 + #define SDMA0_STATUS1_REG__CE_AFIFO_FULL_MASK 0x400 1588 + #define SDMA0_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa 1589 + #define SDMA0_STATUS1_REG__CE_INFO_FULL_MASK 0x2000 1590 + #define SDMA0_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd 1591 + #define SDMA0_STATUS1_REG__CE_INFO1_FULL_MASK 0x4000 1592 + #define SDMA0_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe 1593 + #define SDMA0_STATUS1_REG__CE_RD_STALL_MASK 0x20000 1594 + #define SDMA0_STATUS1_REG__CE_RD_STALL__SHIFT 0x11 1595 + #define SDMA0_STATUS1_REG__CE_WR_STALL_MASK 0x40000 1596 + #define SDMA0_STATUS1_REG__CE_WR_STALL__SHIFT 0x12 1597 + #define SDMA0_RD_BURST_CNTL__RD_BURST_MASK 0x3 1598 + #define SDMA0_RD_BURST_CNTL__RD_BURST__SHIFT 0x0 1599 + #define SDMA0_PERFMON_CNTL__PERF_ENABLE0_MASK 0x1 1600 + #define SDMA0_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0 1601 + #define SDMA0_PERFMON_CNTL__PERF_CLEAR0_MASK 0x2 1602 + #define SDMA0_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1 1603 + #define SDMA0_PERFMON_CNTL__PERF_SEL0_MASK 0xfc 1604 + #define SDMA0_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2 1605 + #define SDMA0_PERFMON_CNTL__PERF_ENABLE1_MASK 0x100 1606 + #define SDMA0_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0x8 1607 + #define SDMA0_PERFMON_CNTL__PERF_CLEAR1_MASK 0x200 1608 + #define SDMA0_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0x9 1609 + #define SDMA0_PERFMON_CNTL__PERF_SEL1_MASK 0xfc00 1610 + #define SDMA0_PERFMON_CNTL__PERF_SEL1__SHIFT 0xa 1611 + #define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xffffffff 1612 + #define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0 1613 + #define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xffffffff 1614 + #define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0 1615 + #define SDMA0_F32_CNTL__HALT_MASK 0x1 1616 + #define SDMA0_F32_CNTL__HALT__SHIFT 0x0 1617 + #define SDMA0_F32_CNTL__STEP_MASK 0x2 1618 + #define SDMA0_F32_CNTL__STEP__SHIFT 0x1 1619 + #define SDMA0_F32_CNTL__DBG_SELECT_BITS_MASK 0xfc 1620 + #define SDMA0_F32_CNTL__DBG_SELECT_BITS__SHIFT 0x2 1621 + #define SDMA0_FREEZE__FREEZE_MASK 0x10 1622 + #define SDMA0_FREEZE__FREEZE__SHIFT 0x4 1623 + #define SDMA0_FREEZE__FROZEN_MASK 0x20 1624 + #define SDMA0_FREEZE__FROZEN__SHIFT 0x5 1625 + #define SDMA0_FREEZE__F32_FREEZE_MASK 0x40 1626 + #define SDMA0_FREEZE__F32_FREEZE__SHIFT 0x6 1627 + #define SDMA0_PHASE0_QUANTUM__UNIT_MASK 0xf 1628 + #define SDMA0_PHASE0_QUANTUM__UNIT__SHIFT 0x0 1629 + #define SDMA0_PHASE0_QUANTUM__VALUE_MASK 0xffff00 1630 + #define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT 0x8 1631 + #define SDMA0_PHASE0_QUANTUM__PREFER_MASK 0x40000000 1632 + #define SDMA0_PHASE0_QUANTUM__PREFER__SHIFT 0x1e 1633 + #define SDMA0_PHASE1_QUANTUM__UNIT_MASK 0xf 1634 + #define SDMA0_PHASE1_QUANTUM__UNIT__SHIFT 0x0 1635 + #define SDMA0_PHASE1_QUANTUM__VALUE_MASK 0xffff00 1636 + #define SDMA0_PHASE1_QUANTUM__VALUE__SHIFT 0x8 1637 + #define SDMA0_PHASE1_QUANTUM__PREFER_MASK 0x40000000 1638 + #define SDMA0_PHASE1_QUANTUM__PREFER__SHIFT 0x1e 1639 + #define SDMA_POWER_GATING__PG_CNTL_ENABLE_MASK 0x1 1640 + #define SDMA_POWER_GATING__PG_CNTL_ENABLE__SHIFT 0x0 1641 + #define SDMA_POWER_GATING__AUTOMATIC_STATUS_ENABLE_MASK 0x2 1642 + #define SDMA_POWER_GATING__AUTOMATIC_STATUS_ENABLE__SHIFT 0x1 1643 + #define SDMA_POWER_GATING__PG_STATE_VALID_MASK 0x4 1644 + #define SDMA_POWER_GATING__PG_STATE_VALID__SHIFT 0x2 1645 + #define SDMA_POWER_GATING__PG_CNTL_STATUS_MASK 0x30 1646 + #define SDMA_POWER_GATING__PG_CNTL_STATUS__SHIFT 0x4 1647 + #define SDMA_POWER_GATING__SDMA0_ON_CONDITION_MASK 0x40 1648 + #define SDMA_POWER_GATING__SDMA0_ON_CONDITION__SHIFT 0x6 1649 + #define SDMA_POWER_GATING__SDMA1_ON_CONDITION_MASK 0x80 1650 + #define SDMA_POWER_GATING__SDMA1_ON_CONDITION__SHIFT 0x7 1651 + #define SDMA_POWER_GATING__POWER_OFF_DELAY_MASK 0xfff00 1652 + #define SDMA_POWER_GATING__POWER_OFF_DELAY__SHIFT 0x8 1653 + #define SDMA_POWER_GATING__POWER_ON_DELAY_MASK 0xfff00000 1654 + #define SDMA_POWER_GATING__POWER_ON_DELAY__SHIFT 0x14 1655 + #define SDMA_PGFSM_CONFIG__FSM_ADDR_MASK 0xff 1656 + #define SDMA_PGFSM_CONFIG__FSM_ADDR__SHIFT 0x0 1657 + #define SDMA_PGFSM_CONFIG__POWER_DOWN_MASK 0x100 1658 + #define SDMA_PGFSM_CONFIG__POWER_DOWN__SHIFT 0x8 1659 + #define SDMA_PGFSM_CONFIG__POWER_UP_MASK 0x200 1660 + #define SDMA_PGFSM_CONFIG__POWER_UP__SHIFT 0x9 1661 + #define SDMA_PGFSM_CONFIG__P1_SELECT_MASK 0x400 1662 + #define SDMA_PGFSM_CONFIG__P1_SELECT__SHIFT 0xa 1663 + #define SDMA_PGFSM_CONFIG__P2_SELECT_MASK 0x800 1664 + #define SDMA_PGFSM_CONFIG__P2_SELECT__SHIFT 0xb 1665 + #define SDMA_PGFSM_CONFIG__WRITE_MASK 0x1000 1666 + #define SDMA_PGFSM_CONFIG__WRITE__SHIFT 0xc 1667 + #define SDMA_PGFSM_CONFIG__READ_MASK 0x2000 1668 + #define SDMA_PGFSM_CONFIG__READ__SHIFT 0xd 1669 + #define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE_MASK 0x8000000 1670 + #define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE__SHIFT 0x1b 1671 + #define SDMA_PGFSM_CONFIG__REG_ADDR_MASK 0xf0000000 1672 + #define SDMA_PGFSM_CONFIG__REG_ADDR__SHIFT 0x1c 1673 + #define SDMA_PGFSM_WRITE__VALUE_MASK 0xffffffff 1674 + #define SDMA_PGFSM_WRITE__VALUE__SHIFT 0x0 1675 + #define SDMA_PGFSM_READ__VALUE_MASK 0xffffff 1676 + #define SDMA_PGFSM_READ__VALUE__SHIFT 0x0 1677 + #define SDMA0_EDC_CONFIG__DIS_EDC_MASK 0x2 1678 + #define SDMA0_EDC_CONFIG__DIS_EDC__SHIFT 0x1 1679 + #define SDMA0_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x4 1680 + #define SDMA0_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2 1681 + #define SDMA0_VM_CNTL__CMD_MASK 0xf 1682 + #define SDMA0_VM_CNTL__CMD__SHIFT 0x0 1683 + #define SDMA0_VM_CTX_LO__ADDR_MASK 0xfffffffc 1684 + #define SDMA0_VM_CTX_LO__ADDR__SHIFT 0x2 1685 + #define SDMA0_VM_CTX_HI__ADDR_MASK 0xffffffff 1686 + #define SDMA0_VM_CTX_HI__ADDR__SHIFT 0x0 1687 + #define SDMA0_STATUS2_REG__ID_MASK 0x3 1688 + #define SDMA0_STATUS2_REG__ID__SHIFT 0x0 1689 + #define SDMA0_STATUS2_REG__F32_INSTR_PTR_MASK 0xffc 1690 + #define SDMA0_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x2 1691 + #define SDMA0_STATUS2_REG__CURRENT_FCN_IDLE_MASK 0xc000 1692 + #define SDMA0_STATUS2_REG__CURRENT_FCN_IDLE__SHIFT 0xe 1693 + #define SDMA0_STATUS2_REG__CMD_OP_MASK 0xffff0000 1694 + #define SDMA0_STATUS2_REG__CMD_OP__SHIFT 0x10 1695 + #define SDMA0_ACTIVE_FCN_ID__VFID_MASK 0xf 1696 + #define SDMA0_ACTIVE_FCN_ID__VFID__SHIFT 0x0 1697 + #define SDMA0_ACTIVE_FCN_ID__VF_MASK 0x80000000 1698 + #define SDMA0_ACTIVE_FCN_ID__VF__SHIFT 0x1f 1699 + #define SDMA0_VM_CTX_CNTL__PRIV_MASK 0x1 1700 + #define SDMA0_VM_CTX_CNTL__PRIV__SHIFT 0x0 1701 + #define SDMA0_VM_CTX_CNTL__VMID_MASK 0xf0 1702 + #define SDMA0_VM_CTX_CNTL__VMID__SHIFT 0x4 1703 + #define SDMA0_VIRT_RESET_REQ__VF_MASK 0xffff 1704 + #define SDMA0_VIRT_RESET_REQ__VF__SHIFT 0x0 1705 + #define SDMA0_VIRT_RESET_REQ__PF_MASK 0x80000000 1706 + #define SDMA0_VIRT_RESET_REQ__PF__SHIFT 0x1f 1707 + #define SDMA0_VF_ENABLE__VF_ENABLE_MASK 0x1 1708 + #define SDMA0_VF_ENABLE__VF_ENABLE__SHIFT 0x0 1709 + #define SDMA0_BA_THRESHOLD__READ_THRES_MASK 0x3ff 1710 + #define SDMA0_BA_THRESHOLD__READ_THRES__SHIFT 0x0 1711 + #define SDMA0_BA_THRESHOLD__WRITE_THRES_MASK 0x3ff0000 1712 + #define SDMA0_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10 1713 + #define SDMA0_ID__DEVICE_ID_MASK 0xff 1714 + #define SDMA0_ID__DEVICE_ID__SHIFT 0x0 1715 + #define SDMA0_VERSION__VALUE_MASK 0xffff 1716 + #define SDMA0_VERSION__VALUE__SHIFT 0x0 1717 + #define SDMA0_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7fffffff 1718 + #define SDMA0_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0 1719 + #define SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000 1720 + #define SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f 1721 + #define SDMA0_ATOMIC_PREOP_LO__DATA_MASK 0xffffffff 1722 + #define SDMA0_ATOMIC_PREOP_LO__DATA__SHIFT 0x0 1723 + #define SDMA0_ATOMIC_PREOP_HI__DATA_MASK 0xffffffff 1724 + #define SDMA0_ATOMIC_PREOP_HI__DATA__SHIFT 0x0 1725 + #define SDMA0_POWER_CNTL_IDLE__DELAY1_MASK 0xffff 1726 + #define SDMA0_POWER_CNTL_IDLE__DELAY1__SHIFT 0x0 1727 + #define SDMA0_POWER_CNTL_IDLE__DELAY2_MASK 0xffff0000 1728 + #define SDMA0_POWER_CNTL_IDLE__DELAY2__SHIFT 0x10 1729 + #define SDMA0_PERF_REG_TYPE0__SDMA0_PERFMON_CNTL_MASK 0x1 1730 + #define SDMA0_PERF_REG_TYPE0__SDMA0_PERFMON_CNTL__SHIFT 0x0 1731 + #define SDMA0_PERF_REG_TYPE0__SDMA0_PERFCOUNTER0_RESULT_MASK 0x2 1732 + #define SDMA0_PERF_REG_TYPE0__SDMA0_PERFCOUNTER0_RESULT__SHIFT 0x1 1733 + #define SDMA0_PERF_REG_TYPE0__SDMA0_PERFCOUNTER1_RESULT_MASK 0x4 1734 + #define SDMA0_PERF_REG_TYPE0__SDMA0_PERFCOUNTER1_RESULT__SHIFT 0x2 1735 + #define SDMA0_PERF_REG_TYPE0__RESERVED_31_3_MASK 0xfffffff8 1736 + #define SDMA0_PERF_REG_TYPE0__RESERVED_31_3__SHIFT 0x3 1737 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_CNTL_MASK 0x1 1738 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_CNTL__SHIFT 0x0 1739 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_MASK 0x2 1740 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE__SHIFT 0x1 1741 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_HI_MASK 0x4 1742 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_HI__SHIFT 0x2 1743 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_MASK 0x8 1744 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR__SHIFT 0x3 1745 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_MASK 0x10 1746 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR__SHIFT 0x4 1747 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_CNTL_MASK 0x20 1748 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_CNTL__SHIFT 0x5 1749 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_ADDR_HI_MASK 0x40 1750 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT 0x6 1751 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_ADDR_LO_MASK 0x80 1752 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT 0x7 1753 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_HI_MASK 0x100 1754 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_HI__SHIFT 0x8 1755 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_LO_MASK 0x200 1756 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_LO__SHIFT 0x9 1757 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_CNTL_MASK 0x400 1758 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_CNTL__SHIFT 0xa 1759 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_RPTR_MASK 0x800 1760 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_RPTR__SHIFT 0xb 1761 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_OFFSET_MASK 0x1000 1762 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_OFFSET__SHIFT 0xc 1763 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_LO_MASK 0x2000 1764 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_LO__SHIFT 0xd 1765 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_HI_MASK 0x4000 1766 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_HI__SHIFT 0xe 1767 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_SIZE_MASK 0x8000 1768 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_SIZE__SHIFT 0xf 1769 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_SKIP_CNTL_MASK 0x10000 1770 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_SKIP_CNTL__SHIFT 0x10 1771 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_STATUS_MASK 0x20000 1772 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_STATUS__SHIFT 0x11 1773 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DOORBELL_MASK 0x40000 1774 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DOORBELL__SHIFT 0x12 1775 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_CNTL_MASK 0x80000 1776 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_CNTL__SHIFT 0x13 1777 + #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_VIRTUAL_ADDR_MASK 0x80 1778 + #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_VIRTUAL_ADDR__SHIFT 0x7 1779 + #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_APE1_CNTL_MASK 0x100 1780 + #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_APE1_CNTL__SHIFT 0x8 1781 + #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_LOG_MASK 0x200 1782 + #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_LOG__SHIFT 0x9 1783 + #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_WATERMARK_MASK 0x400 1784 + #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_WATERMARK__SHIFT 0xa 1785 + #define SDMA0_CONTEXT_REG_TYPE1__VOID_REG1_MASK 0x800 1786 + #define SDMA0_CONTEXT_REG_TYPE1__VOID_REG1__SHIFT 0xb 1787 + #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_LO_MASK 0x1000 1788 + #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_LO__SHIFT 0xc 1789 + #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_HI_MASK 0x2000 1790 + #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_HI__SHIFT 0xd 1791 + #define SDMA0_CONTEXT_REG_TYPE1__VOID_REG2_MASK 0x4000 1792 + #define SDMA0_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT 0xe 1793 + #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_IB_SUB_REMAIN_MASK 0x8000 1794 + #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_IB_SUB_REMAIN__SHIFT 0xf 1795 + #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_PREEMPT_MASK 0x10000 1796 + #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_PREEMPT__SHIFT 0x10 1797 + #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DUMMY_REG_MASK 0x20000 1798 + #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DUMMY_REG__SHIFT 0x11 1799 + #define SDMA0_CONTEXT_REG_TYPE1__RESERVED_MASK 0xfffc0000 1800 + #define SDMA0_CONTEXT_REG_TYPE1__RESERVED__SHIFT 0x12 1801 + #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA0_MASK 0x1 1802 + #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA0__SHIFT 0x0 1803 + #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA1_MASK 0x2 1804 + #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA1__SHIFT 0x1 1805 + #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA2_MASK 0x4 1806 + #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA2__SHIFT 0x2 1807 + #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA3_MASK 0x8 1808 + #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA3__SHIFT 0x3 1809 + #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA4_MASK 0x10 1810 + #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA4__SHIFT 0x4 1811 + #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA5_MASK 0x20 1812 + #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA5__SHIFT 0x5 1813 + #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_CNTL_MASK 0x40 1814 + #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_CNTL__SHIFT 0x6 1815 + #define SDMA0_CONTEXT_REG_TYPE2__RESERVED_MASK 0xffffff80 1816 + #define SDMA0_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0x7 1817 + #define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR_MASK 0x1 1818 + #define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR__SHIFT 0x0 1819 + #define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA_MASK 0x2 1820 + #define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA__SHIFT 0x1 1821 + #define SDMA0_PUB_REG_TYPE0__SDMA0_POWER_CNTL_MASK 0x4 1822 + #define SDMA0_PUB_REG_TYPE0__SDMA0_POWER_CNTL__SHIFT 0x2 1823 + #define SDMA0_PUB_REG_TYPE0__SDMA0_CLK_CTRL_MASK 0x8 1824 + #define SDMA0_PUB_REG_TYPE0__SDMA0_CLK_CTRL__SHIFT 0x3 1825 + #define SDMA0_PUB_REG_TYPE0__SDMA0_CNTL_MASK 0x10 1826 + #define SDMA0_PUB_REG_TYPE0__SDMA0_CNTL__SHIFT 0x4 1827 + #define SDMA0_PUB_REG_TYPE0__SDMA0_CHICKEN_BITS_MASK 0x20 1828 + #define SDMA0_PUB_REG_TYPE0__SDMA0_CHICKEN_BITS__SHIFT 0x5 1829 + #define SDMA0_PUB_REG_TYPE0__SDMA0_TILING_CONFIG_MASK 0x40 1830 + #define SDMA0_PUB_REG_TYPE0__SDMA0_TILING_CONFIG__SHIFT 0x6 1831 + #define SDMA0_PUB_REG_TYPE0__SDMA0_HASH_MASK 0x80 1832 + #define SDMA0_PUB_REG_TYPE0__SDMA0_HASH__SHIFT 0x7 1833 + #define SDMA0_PUB_REG_TYPE0__SDMA0_SEM_WAIT_FAIL_TIMER_CNTL_MASK 0x200 1834 + #define SDMA0_PUB_REG_TYPE0__SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__SHIFT 0x9 1835 + #define SDMA0_PUB_REG_TYPE0__SDMA0_RB_RPTR_FETCH_MASK 0x400 1836 + #define SDMA0_PUB_REG_TYPE0__SDMA0_RB_RPTR_FETCH__SHIFT 0xa 1837 + #define SDMA0_PUB_REG_TYPE0__SDMA0_IB_OFFSET_FETCH_MASK 0x800 1838 + #define SDMA0_PUB_REG_TYPE0__SDMA0_IB_OFFSET_FETCH__SHIFT 0xb 1839 + #define SDMA0_PUB_REG_TYPE0__SDMA0_PROGRAM_MASK 0x1000 1840 + #define SDMA0_PUB_REG_TYPE0__SDMA0_PROGRAM__SHIFT 0xc 1841 + #define SDMA0_PUB_REG_TYPE0__SDMA0_STATUS_REG_MASK 0x2000 1842 + #define SDMA0_PUB_REG_TYPE0__SDMA0_STATUS_REG__SHIFT 0xd 1843 + #define SDMA0_PUB_REG_TYPE0__SDMA0_STATUS1_REG_MASK 0x4000 1844 + #define SDMA0_PUB_REG_TYPE0__SDMA0_STATUS1_REG__SHIFT 0xe 1845 + #define SDMA0_PUB_REG_TYPE0__SDMA0_RD_BURST_CNTL_MASK 0x8000 1846 + #define SDMA0_PUB_REG_TYPE0__SDMA0_RD_BURST_CNTL__SHIFT 0xf 1847 + #define SDMA0_PUB_REG_TYPE0__RESERVED_16_MASK 0x10000 1848 + #define SDMA0_PUB_REG_TYPE0__RESERVED_16__SHIFT 0x10 1849 + #define SDMA0_PUB_REG_TYPE0__RESERVED_17_MASK 0x20000 1850 + #define SDMA0_PUB_REG_TYPE0__RESERVED_17__SHIFT 0x11 1851 + #define SDMA0_PUB_REG_TYPE0__SDMA0_F32_CNTL_MASK 0x40000 1852 + #define SDMA0_PUB_REG_TYPE0__SDMA0_F32_CNTL__SHIFT 0x12 1853 + #define SDMA0_PUB_REG_TYPE0__SDMA0_FREEZE_MASK 0x80000 1854 + #define SDMA0_PUB_REG_TYPE0__SDMA0_FREEZE__SHIFT 0x13 1855 + #define SDMA0_PUB_REG_TYPE0__SDMA0_PHASE0_QUANTUM_MASK 0x100000 1856 + #define SDMA0_PUB_REG_TYPE0__SDMA0_PHASE0_QUANTUM__SHIFT 0x14 1857 + #define SDMA0_PUB_REG_TYPE0__SDMA0_PHASE1_QUANTUM_MASK 0x200000 1858 + #define SDMA0_PUB_REG_TYPE0__SDMA0_PHASE1_QUANTUM__SHIFT 0x15 1859 + #define SDMA0_PUB_REG_TYPE0__SDMA_POWER_GATING_MASK 0x400000 1860 + #define SDMA0_PUB_REG_TYPE0__SDMA_POWER_GATING__SHIFT 0x16 1861 + #define SDMA0_PUB_REG_TYPE0__SDMA_PGFSM_CONFIG_MASK 0x800000 1862 + #define SDMA0_PUB_REG_TYPE0__SDMA_PGFSM_CONFIG__SHIFT 0x17 1863 + #define SDMA0_PUB_REG_TYPE0__SDMA_PGFSM_WRITE_MASK 0x1000000 1864 + #define SDMA0_PUB_REG_TYPE0__SDMA_PGFSM_WRITE__SHIFT 0x18 1865 + #define SDMA0_PUB_REG_TYPE0__SDMA_PGFSM_READ_MASK 0x2000000 1866 + #define SDMA0_PUB_REG_TYPE0__SDMA_PGFSM_READ__SHIFT 0x19 1867 + #define SDMA0_PUB_REG_TYPE0__SDMA0_EDC_CONFIG_MASK 0x4000000 1868 + #define SDMA0_PUB_REG_TYPE0__SDMA0_EDC_CONFIG__SHIFT 0x1a 1869 + #define SDMA0_PUB_REG_TYPE0__SDMA0_BA_THRESHOLD_MASK 0x8000000 1870 + #define SDMA0_PUB_REG_TYPE0__SDMA0_BA_THRESHOLD__SHIFT 0x1b 1871 + #define SDMA0_PUB_REG_TYPE0__SDMA0_DEVICE_ID_MASK 0x10000000 1872 + #define SDMA0_PUB_REG_TYPE0__SDMA0_DEVICE_ID__SHIFT 0x1c 1873 + #define SDMA0_PUB_REG_TYPE0__SDMA0_VERSION_MASK 0x20000000 1874 + #define SDMA0_PUB_REG_TYPE0__SDMA0_VERSION__SHIFT 0x1d 1875 + #define SDMA0_PUB_REG_TYPE0__RESERVED_MASK 0xc0000000 1876 + #define SDMA0_PUB_REG_TYPE0__RESERVED__SHIFT 0x1e 1877 + #define SDMA0_PUB_REG_TYPE1__SDMA0_VM_CNTL_MASK 0x1 1878 + #define SDMA0_PUB_REG_TYPE1__SDMA0_VM_CNTL__SHIFT 0x0 1879 + #define SDMA0_PUB_REG_TYPE1__SDMA0_VM_CTX_LO_MASK 0x2 1880 + #define SDMA0_PUB_REG_TYPE1__SDMA0_VM_CTX_LO__SHIFT 0x1 1881 + #define SDMA0_PUB_REG_TYPE1__SDMA0_VM_CTX_HI_MASK 0x4 1882 + #define SDMA0_PUB_REG_TYPE1__SDMA0_VM_CTX_HI__SHIFT 0x2 1883 + #define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS2_REG_MASK 0x8 1884 + #define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS2_REG__SHIFT 0x3 1885 + #define SDMA0_PUB_REG_TYPE1__SDMA0_ACTIVE_FCN_ID_MASK 0x10 1886 + #define SDMA0_PUB_REG_TYPE1__SDMA0_ACTIVE_FCN_ID__SHIFT 0x4 1887 + #define SDMA0_PUB_REG_TYPE1__SDMA0_VM_CTX_CNTL_MASK 0x20 1888 + #define SDMA0_PUB_REG_TYPE1__SDMA0_VM_CTX_CNTL__SHIFT 0x5 1889 + #define SDMA0_PUB_REG_TYPE1__SDMA0_VIRT_RESET_REQ_MASK 0x40 1890 + #define SDMA0_PUB_REG_TYPE1__SDMA0_VIRT_RESET_REQ__SHIFT 0x6 1891 + #define SDMA0_PUB_REG_TYPE1__SDMA0_VF_ENABLE_MASK 0x80 1892 + #define SDMA0_PUB_REG_TYPE1__SDMA0_VF_ENABLE__SHIFT 0x7 1893 + #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_CNTL_MASK 0x100 1894 + #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_CNTL__SHIFT 0x8 1895 + #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_LO_MASK 0x200 1896 + #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_LO__SHIFT 0x9 1897 + #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_HI_MASK 0x400 1898 + #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_HI__SHIFT 0xa 1899 + #define SDMA0_PUB_REG_TYPE1__RESERVED_MASK 0xfffff800 1900 + #define SDMA0_PUB_REG_TYPE1__RESERVED__SHIFT 0xb 1901 + #define SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK 0x1 1902 + #define SDMA0_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0 1903 + #define SDMA0_GFX_RB_CNTL__RB_SIZE_MASK 0x3e 1904 + #define SDMA0_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1 1905 + #define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200 1906 + #define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1907 + #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000 1908 + #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1909 + #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000 1910 + #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1911 + #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000 1912 + #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1913 + #define SDMA0_GFX_RB_CNTL__RB_PRIV_MASK 0x800000 1914 + #define SDMA0_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17 1915 + #define SDMA0_GFX_RB_CNTL__RB_VMID_MASK 0xf000000 1916 + #define SDMA0_GFX_RB_CNTL__RB_VMID__SHIFT 0x18 1917 + #define SDMA0_GFX_RB_BASE__ADDR_MASK 0xffffffff 1918 + #define SDMA0_GFX_RB_BASE__ADDR__SHIFT 0x0 1919 + #define SDMA0_GFX_RB_BASE_HI__ADDR_MASK 0xffffff 1920 + #define SDMA0_GFX_RB_BASE_HI__ADDR__SHIFT 0x0 1921 + #define SDMA0_GFX_RB_RPTR__OFFSET_MASK 0xfffffffc 1922 + #define SDMA0_GFX_RB_RPTR__OFFSET__SHIFT 0x2 1923 + #define SDMA0_GFX_RB_WPTR__OFFSET_MASK 0xfffffffc 1924 + #define SDMA0_GFX_RB_WPTR__OFFSET__SHIFT 0x2 1925 + #define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1 1926 + #define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1927 + #define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2 1928 + #define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1929 + #define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x4 1930 + #define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1931 + #define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0 1932 + #define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1933 + #define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000 1934 + #define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1935 + #define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff 1936 + #define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 1937 + #define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc 1938 + #define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 1939 + #define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff 1940 + #define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1941 + #define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc 1942 + #define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1943 + #define SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK 0x1 1944 + #define SDMA0_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0 1945 + #define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10 1946 + #define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1947 + #define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100 1948 + #define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1949 + #define SDMA0_GFX_IB_CNTL__CMD_VMID_MASK 0xf0000 1950 + #define SDMA0_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10 1951 + #define SDMA0_GFX_IB_RPTR__OFFSET_MASK 0x3ffffc 1952 + #define SDMA0_GFX_IB_RPTR__OFFSET__SHIFT 0x2 1953 + #define SDMA0_GFX_IB_OFFSET__OFFSET_MASK 0x3ffffc 1954 + #define SDMA0_GFX_IB_OFFSET__OFFSET__SHIFT 0x2 1955 + #define SDMA0_GFX_IB_BASE_LO__ADDR_MASK 0xffffffe0 1956 + #define SDMA0_GFX_IB_BASE_LO__ADDR__SHIFT 0x5 1957 + #define SDMA0_GFX_IB_BASE_HI__ADDR_MASK 0xffffffff 1958 + #define SDMA0_GFX_IB_BASE_HI__ADDR__SHIFT 0x0 1959 + #define SDMA0_GFX_IB_SIZE__SIZE_MASK 0xfffff 1960 + #define SDMA0_GFX_IB_SIZE__SIZE__SHIFT 0x0 1961 + #define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff 1962 + #define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1963 + #define SDMA0_GFX_CONTEXT_STATUS__SELECTED_MASK 0x1 1964 + #define SDMA0_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1965 + #define SDMA0_GFX_CONTEXT_STATUS__IDLE_MASK 0x4 1966 + #define SDMA0_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2 1967 + #define SDMA0_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x8 1968 + #define SDMA0_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1969 + #define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x70 1970 + #define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1971 + #define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80 1972 + #define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1973 + #define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x100 1974 + #define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1975 + #define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x200 1976 + #define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1977 + #define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x400 1978 + #define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1979 + #define SDMA0_GFX_DOORBELL__OFFSET_MASK 0x1fffff 1980 + #define SDMA0_GFX_DOORBELL__OFFSET__SHIFT 0x0 1981 + #define SDMA0_GFX_DOORBELL__ENABLE_MASK 0x10000000 1982 + #define SDMA0_GFX_DOORBELL__ENABLE__SHIFT 0x1c 1983 + #define SDMA0_GFX_DOORBELL__CAPTURED_MASK 0x40000000 1984 + #define SDMA0_GFX_DOORBELL__CAPTURED__SHIFT 0x1e 1985 + #define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x10000 1986 + #define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10 1987 + #define SDMA0_GFX_CONTEXT_CNTL__SESSION_SEL_MASK 0xf000000 1988 + #define SDMA0_GFX_CONTEXT_CNTL__SESSION_SEL__SHIFT 0x18 1989 + #define SDMA0_GFX_VIRTUAL_ADDR__ATC_MASK 0x1 1990 + #define SDMA0_GFX_VIRTUAL_ADDR__ATC__SHIFT 0x0 1991 + #define SDMA0_GFX_VIRTUAL_ADDR__INVAL_MASK 0x2 1992 + #define SDMA0_GFX_VIRTUAL_ADDR__INVAL__SHIFT 0x1 1993 + #define SDMA0_GFX_VIRTUAL_ADDR__PTR32_MASK 0x10 1994 + #define SDMA0_GFX_VIRTUAL_ADDR__PTR32__SHIFT 0x4 1995 + #define SDMA0_GFX_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700 1996 + #define SDMA0_GFX_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8 1997 + #define SDMA0_GFX_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000 1998 + #define SDMA0_GFX_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e 1999 + #define SDMA0_GFX_APE1_CNTL__BASE_MASK 0xffff 2000 + #define SDMA0_GFX_APE1_CNTL__BASE__SHIFT 0x0 2001 + #define SDMA0_GFX_APE1_CNTL__LIMIT_MASK 0xffff0000 2002 + #define SDMA0_GFX_APE1_CNTL__LIMIT__SHIFT 0x10 2003 + #define SDMA0_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x1 2004 + #define SDMA0_GFX_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 2005 + #define SDMA0_GFX_DOORBELL_LOG__DATA_MASK 0xfffffffc 2006 + #define SDMA0_GFX_DOORBELL_LOG__DATA__SHIFT 0x2 2007 + #define SDMA0_GFX_WATERMARK__RD_OUTSTANDING_MASK 0xfff 2008 + #define SDMA0_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 2009 + #define SDMA0_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000 2010 + #define SDMA0_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 2011 + #define SDMA0_GFX_CSA_ADDR_LO__ADDR_MASK 0xfffffffc 2012 + #define SDMA0_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2 2013 + #define SDMA0_GFX_CSA_ADDR_HI__ADDR_MASK 0xffffffff 2014 + #define SDMA0_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0 2015 + #define SDMA0_GFX_IB_SUB_REMAIN__SIZE_MASK 0x3fff 2016 + #define SDMA0_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0 2017 + #define SDMA0_GFX_PREEMPT__IB_PREEMPT_MASK 0x1 2018 + #define SDMA0_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0 2019 + #define SDMA0_GFX_DUMMY_REG__DUMMY_MASK 0xffffffff 2020 + #define SDMA0_GFX_DUMMY_REG__DUMMY__SHIFT 0x0 2021 + #define SDMA0_GFX_MIDCMD_DATA0__DATA0_MASK 0xffffffff 2022 + #define SDMA0_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0 2023 + #define SDMA0_GFX_MIDCMD_DATA1__DATA1_MASK 0xffffffff 2024 + #define SDMA0_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0 2025 + #define SDMA0_GFX_MIDCMD_DATA2__DATA2_MASK 0xffffffff 2026 + #define SDMA0_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0 2027 + #define SDMA0_GFX_MIDCMD_DATA3__DATA3_MASK 0xffffffff 2028 + #define SDMA0_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0 2029 + #define SDMA0_GFX_MIDCMD_DATA4__DATA4_MASK 0xffffffff 2030 + #define SDMA0_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0 2031 + #define SDMA0_GFX_MIDCMD_DATA5__DATA5_MASK 0xffffffff 2032 + #define SDMA0_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0 2033 + #define SDMA0_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x1 2034 + #define SDMA0_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 2035 + #define SDMA0_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x2 2036 + #define SDMA0_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 2037 + #define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0xf0 2038 + #define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 2039 + #define SDMA0_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x100 2040 + #define SDMA0_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 2041 + #define SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK 0x1 2042 + #define SDMA0_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0 2043 + #define SDMA0_RLC0_RB_CNTL__RB_SIZE_MASK 0x3e 2044 + #define SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1 2045 + #define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200 2046 + #define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 2047 + #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000 2048 + #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 2049 + #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000 2050 + #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 2051 + #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000 2052 + #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 2053 + #define SDMA0_RLC0_RB_CNTL__RB_PRIV_MASK 0x800000 2054 + #define SDMA0_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17 2055 + #define SDMA0_RLC0_RB_CNTL__RB_VMID_MASK 0xf000000 2056 + #define SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18 2057 + #define SDMA0_RLC0_RB_BASE__ADDR_MASK 0xffffffff 2058 + #define SDMA0_RLC0_RB_BASE__ADDR__SHIFT 0x0 2059 + #define SDMA0_RLC0_RB_BASE_HI__ADDR_MASK 0xffffff 2060 + #define SDMA0_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0 2061 + #define SDMA0_RLC0_RB_RPTR__OFFSET_MASK 0xfffffffc 2062 + #define SDMA0_RLC0_RB_RPTR__OFFSET__SHIFT 0x2 2063 + #define SDMA0_RLC0_RB_WPTR__OFFSET_MASK 0xfffffffc 2064 + #define SDMA0_RLC0_RB_WPTR__OFFSET__SHIFT 0x2 2065 + #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1 2066 + #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 2067 + #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2 2068 + #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 2069 + #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x4 2070 + #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 2071 + #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0 2072 + #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 2073 + #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000 2074 + #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 2075 + #define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff 2076 + #define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 2077 + #define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc 2078 + #define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 2079 + #define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff 2080 + #define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 2081 + #define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc 2082 + #define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 2083 + #define SDMA0_RLC0_IB_CNTL__IB_ENABLE_MASK 0x1 2084 + #define SDMA0_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0 2085 + #define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10 2086 + #define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 2087 + #define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100 2088 + #define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 2089 + #define SDMA0_RLC0_IB_CNTL__CMD_VMID_MASK 0xf0000 2090 + #define SDMA0_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10 2091 + #define SDMA0_RLC0_IB_RPTR__OFFSET_MASK 0x3ffffc 2092 + #define SDMA0_RLC0_IB_RPTR__OFFSET__SHIFT 0x2 2093 + #define SDMA0_RLC0_IB_OFFSET__OFFSET_MASK 0x3ffffc 2094 + #define SDMA0_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2 2095 + #define SDMA0_RLC0_IB_BASE_LO__ADDR_MASK 0xffffffe0 2096 + #define SDMA0_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5 2097 + #define SDMA0_RLC0_IB_BASE_HI__ADDR_MASK 0xffffffff 2098 + #define SDMA0_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0 2099 + #define SDMA0_RLC0_IB_SIZE__SIZE_MASK 0xfffff 2100 + #define SDMA0_RLC0_IB_SIZE__SIZE__SHIFT 0x0 2101 + #define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff 2102 + #define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 2103 + #define SDMA0_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x1 2104 + #define SDMA0_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0 2105 + #define SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK 0x4 2106 + #define SDMA0_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2 2107 + #define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x8 2108 + #define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 2109 + #define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x70 2110 + #define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 2111 + #define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80 2112 + #define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 2113 + #define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x100 2114 + #define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 2115 + #define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x200 2116 + #define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 2117 + #define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x400 2118 + #define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 2119 + #define SDMA0_RLC0_DOORBELL__OFFSET_MASK 0x1fffff 2120 + #define SDMA0_RLC0_DOORBELL__OFFSET__SHIFT 0x0 2121 + #define SDMA0_RLC0_DOORBELL__ENABLE_MASK 0x10000000 2122 + #define SDMA0_RLC0_DOORBELL__ENABLE__SHIFT 0x1c 2123 + #define SDMA0_RLC0_DOORBELL__CAPTURED_MASK 0x40000000 2124 + #define SDMA0_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e 2125 + #define SDMA0_RLC0_VIRTUAL_ADDR__ATC_MASK 0x1 2126 + #define SDMA0_RLC0_VIRTUAL_ADDR__ATC__SHIFT 0x0 2127 + #define SDMA0_RLC0_VIRTUAL_ADDR__INVAL_MASK 0x2 2128 + #define SDMA0_RLC0_VIRTUAL_ADDR__INVAL__SHIFT 0x1 2129 + #define SDMA0_RLC0_VIRTUAL_ADDR__PTR32_MASK 0x10 2130 + #define SDMA0_RLC0_VIRTUAL_ADDR__PTR32__SHIFT 0x4 2131 + #define SDMA0_RLC0_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700 2132 + #define SDMA0_RLC0_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8 2133 + #define SDMA0_RLC0_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000 2134 + #define SDMA0_RLC0_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e 2135 + #define SDMA0_RLC0_APE1_CNTL__BASE_MASK 0xffff 2136 + #define SDMA0_RLC0_APE1_CNTL__BASE__SHIFT 0x0 2137 + #define SDMA0_RLC0_APE1_CNTL__LIMIT_MASK 0xffff0000 2138 + #define SDMA0_RLC0_APE1_CNTL__LIMIT__SHIFT 0x10 2139 + #define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x1 2140 + #define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 2141 + #define SDMA0_RLC0_DOORBELL_LOG__DATA_MASK 0xfffffffc 2142 + #define SDMA0_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2 2143 + #define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0xfff 2144 + #define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 2145 + #define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000 2146 + #define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 2147 + #define SDMA0_RLC0_CSA_ADDR_LO__ADDR_MASK 0xfffffffc 2148 + #define SDMA0_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2 2149 + #define SDMA0_RLC0_CSA_ADDR_HI__ADDR_MASK 0xffffffff 2150 + #define SDMA0_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0 2151 + #define SDMA0_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x3fff 2152 + #define SDMA0_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0 2153 + #define SDMA0_RLC0_PREEMPT__IB_PREEMPT_MASK 0x1 2154 + #define SDMA0_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0 2155 + #define SDMA0_RLC0_DUMMY_REG__DUMMY_MASK 0xffffffff 2156 + #define SDMA0_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0 2157 + #define SDMA0_RLC0_MIDCMD_DATA0__DATA0_MASK 0xffffffff 2158 + #define SDMA0_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0 2159 + #define SDMA0_RLC0_MIDCMD_DATA1__DATA1_MASK 0xffffffff 2160 + #define SDMA0_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0 2161 + #define SDMA0_RLC0_MIDCMD_DATA2__DATA2_MASK 0xffffffff 2162 + #define SDMA0_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0 2163 + #define SDMA0_RLC0_MIDCMD_DATA3__DATA3_MASK 0xffffffff 2164 + #define SDMA0_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0 2165 + #define SDMA0_RLC0_MIDCMD_DATA4__DATA4_MASK 0xffffffff 2166 + #define SDMA0_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0 2167 + #define SDMA0_RLC0_MIDCMD_DATA5__DATA5_MASK 0xffffffff 2168 + #define SDMA0_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0 2169 + #define SDMA0_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x1 2170 + #define SDMA0_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 2171 + #define SDMA0_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x2 2172 + #define SDMA0_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 2173 + #define SDMA0_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0xf0 2174 + #define SDMA0_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 2175 + #define SDMA0_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x100 2176 + #define SDMA0_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 2177 + #define SDMA0_RLC1_RB_CNTL__RB_ENABLE_MASK 0x1 2178 + #define SDMA0_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0 2179 + #define SDMA0_RLC1_RB_CNTL__RB_SIZE_MASK 0x3e 2180 + #define SDMA0_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1 2181 + #define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200 2182 + #define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 2183 + #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000 2184 + #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 2185 + #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000 2186 + #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 2187 + #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000 2188 + #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 2189 + #define SDMA0_RLC1_RB_CNTL__RB_PRIV_MASK 0x800000 2190 + #define SDMA0_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17 2191 + #define SDMA0_RLC1_RB_CNTL__RB_VMID_MASK 0xf000000 2192 + #define SDMA0_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18 2193 + #define SDMA0_RLC1_RB_BASE__ADDR_MASK 0xffffffff 2194 + #define SDMA0_RLC1_RB_BASE__ADDR__SHIFT 0x0 2195 + #define SDMA0_RLC1_RB_BASE_HI__ADDR_MASK 0xffffff 2196 + #define SDMA0_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0 2197 + #define SDMA0_RLC1_RB_RPTR__OFFSET_MASK 0xfffffffc 2198 + #define SDMA0_RLC1_RB_RPTR__OFFSET__SHIFT 0x2 2199 + #define SDMA0_RLC1_RB_WPTR__OFFSET_MASK 0xfffffffc 2200 + #define SDMA0_RLC1_RB_WPTR__OFFSET__SHIFT 0x2 2201 + #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1 2202 + #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 2203 + #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2 2204 + #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 2205 + #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x4 2206 + #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 2207 + #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0 2208 + #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 2209 + #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000 2210 + #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 2211 + #define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff 2212 + #define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 2213 + #define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc 2214 + #define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 2215 + #define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff 2216 + #define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 2217 + #define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc 2218 + #define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 2219 + #define SDMA0_RLC1_IB_CNTL__IB_ENABLE_MASK 0x1 2220 + #define SDMA0_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0 2221 + #define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10 2222 + #define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 2223 + #define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100 2224 + #define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 2225 + #define SDMA0_RLC1_IB_CNTL__CMD_VMID_MASK 0xf0000 2226 + #define SDMA0_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10 2227 + #define SDMA0_RLC1_IB_RPTR__OFFSET_MASK 0x3ffffc 2228 + #define SDMA0_RLC1_IB_RPTR__OFFSET__SHIFT 0x2 2229 + #define SDMA0_RLC1_IB_OFFSET__OFFSET_MASK 0x3ffffc 2230 + #define SDMA0_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2 2231 + #define SDMA0_RLC1_IB_BASE_LO__ADDR_MASK 0xffffffe0 2232 + #define SDMA0_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5 2233 + #define SDMA0_RLC1_IB_BASE_HI__ADDR_MASK 0xffffffff 2234 + #define SDMA0_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0 2235 + #define SDMA0_RLC1_IB_SIZE__SIZE_MASK 0xfffff 2236 + #define SDMA0_RLC1_IB_SIZE__SIZE__SHIFT 0x0 2237 + #define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff 2238 + #define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 2239 + #define SDMA0_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x1 2240 + #define SDMA0_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0 2241 + #define SDMA0_RLC1_CONTEXT_STATUS__IDLE_MASK 0x4 2242 + #define SDMA0_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2 2243 + #define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x8 2244 + #define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 2245 + #define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x70 2246 + #define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 2247 + #define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80 2248 + #define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 2249 + #define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x100 2250 + #define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 2251 + #define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x200 2252 + #define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 2253 + #define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x400 2254 + #define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 2255 + #define SDMA0_RLC1_DOORBELL__OFFSET_MASK 0x1fffff 2256 + #define SDMA0_RLC1_DOORBELL__OFFSET__SHIFT 0x0 2257 + #define SDMA0_RLC1_DOORBELL__ENABLE_MASK 0x10000000 2258 + #define SDMA0_RLC1_DOORBELL__ENABLE__SHIFT 0x1c 2259 + #define SDMA0_RLC1_DOORBELL__CAPTURED_MASK 0x40000000 2260 + #define SDMA0_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e 2261 + #define SDMA0_RLC1_VIRTUAL_ADDR__ATC_MASK 0x1 2262 + #define SDMA0_RLC1_VIRTUAL_ADDR__ATC__SHIFT 0x0 2263 + #define SDMA0_RLC1_VIRTUAL_ADDR__INVAL_MASK 0x2 2264 + #define SDMA0_RLC1_VIRTUAL_ADDR__INVAL__SHIFT 0x1 2265 + #define SDMA0_RLC1_VIRTUAL_ADDR__PTR32_MASK 0x10 2266 + #define SDMA0_RLC1_VIRTUAL_ADDR__PTR32__SHIFT 0x4 2267 + #define SDMA0_RLC1_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700 2268 + #define SDMA0_RLC1_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8 2269 + #define SDMA0_RLC1_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000 2270 + #define SDMA0_RLC1_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e 2271 + #define SDMA0_RLC1_APE1_CNTL__BASE_MASK 0xffff 2272 + #define SDMA0_RLC1_APE1_CNTL__BASE__SHIFT 0x0 2273 + #define SDMA0_RLC1_APE1_CNTL__LIMIT_MASK 0xffff0000 2274 + #define SDMA0_RLC1_APE1_CNTL__LIMIT__SHIFT 0x10 2275 + #define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x1 2276 + #define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 2277 + #define SDMA0_RLC1_DOORBELL_LOG__DATA_MASK 0xfffffffc 2278 + #define SDMA0_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2 2279 + #define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0xfff 2280 + #define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 2281 + #define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000 2282 + #define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 2283 + #define SDMA0_RLC1_CSA_ADDR_LO__ADDR_MASK 0xfffffffc 2284 + #define SDMA0_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2 2285 + #define SDMA0_RLC1_CSA_ADDR_HI__ADDR_MASK 0xffffffff 2286 + #define SDMA0_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0 2287 + #define SDMA0_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x3fff 2288 + #define SDMA0_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0 2289 + #define SDMA0_RLC1_PREEMPT__IB_PREEMPT_MASK 0x1 2290 + #define SDMA0_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0 2291 + #define SDMA0_RLC1_DUMMY_REG__DUMMY_MASK 0xffffffff 2292 + #define SDMA0_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0 2293 + #define SDMA0_RLC1_MIDCMD_DATA0__DATA0_MASK 0xffffffff 2294 + #define SDMA0_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0 2295 + #define SDMA0_RLC1_MIDCMD_DATA1__DATA1_MASK 0xffffffff 2296 + #define SDMA0_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0 2297 + #define SDMA0_RLC1_MIDCMD_DATA2__DATA2_MASK 0xffffffff 2298 + #define SDMA0_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0 2299 + #define SDMA0_RLC1_MIDCMD_DATA3__DATA3_MASK 0xffffffff 2300 + #define SDMA0_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0 2301 + #define SDMA0_RLC1_MIDCMD_DATA4__DATA4_MASK 0xffffffff 2302 + #define SDMA0_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0 2303 + #define SDMA0_RLC1_MIDCMD_DATA5__DATA5_MASK 0xffffffff 2304 + #define SDMA0_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0 2305 + #define SDMA0_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x1 2306 + #define SDMA0_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 2307 + #define SDMA0_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x2 2308 + #define SDMA0_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 2309 + #define SDMA0_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0xf0 2310 + #define SDMA0_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 2311 + #define SDMA0_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x100 2312 + #define SDMA0_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 2313 + #define SDMA1_UCODE_ADDR__VALUE_MASK 0x1fff 2314 + #define SDMA1_UCODE_ADDR__VALUE__SHIFT 0x0 2315 + #define SDMA1_UCODE_DATA__VALUE_MASK 0xffffffff 2316 + #define SDMA1_UCODE_DATA__VALUE__SHIFT 0x0 2317 + #define SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x100 2318 + #define SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8 2319 + #define SDMA1_POWER_CNTL__MEM_POWER_LS_EN_MASK 0x200 2320 + #define SDMA1_POWER_CNTL__MEM_POWER_LS_EN__SHIFT 0x9 2321 + #define SDMA1_POWER_CNTL__MEM_POWER_DS_EN_MASK 0x400 2322 + #define SDMA1_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa 2323 + #define SDMA1_POWER_CNTL__MEM_POWER_SD_EN_MASK 0x800 2324 + #define SDMA1_POWER_CNTL__MEM_POWER_SD_EN__SHIFT 0xb 2325 + #define SDMA1_POWER_CNTL__MEM_POWER_DELAY_MASK 0x3ff000 2326 + #define SDMA1_POWER_CNTL__MEM_POWER_DELAY__SHIFT 0xc 2327 + #define SDMA1_CLK_CTRL__ON_DELAY_MASK 0xf 2328 + #define SDMA1_CLK_CTRL__ON_DELAY__SHIFT 0x0 2329 + #define SDMA1_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 2330 + #define SDMA1_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 2331 + #define SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 2332 + #define SDMA1_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 2333 + #define SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000 2334 + #define SDMA1_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 2335 + #define SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000 2336 + #define SDMA1_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a 2337 + #define SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 2338 + #define SDMA1_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b 2339 + #define SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000 2340 + #define SDMA1_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c 2341 + #define SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000 2342 + #define SDMA1_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d 2343 + #define SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000 2344 + #define SDMA1_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e 2345 + #define SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000 2346 + #define SDMA1_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f 2347 + #define SDMA1_CNTL__TRAP_ENABLE_MASK 0x1 2348 + #define SDMA1_CNTL__TRAP_ENABLE__SHIFT 0x0 2349 + #define SDMA1_CNTL__ATC_L1_ENABLE_MASK 0x2 2350 + #define SDMA1_CNTL__ATC_L1_ENABLE__SHIFT 0x1 2351 + #define SDMA1_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x4 2352 + #define SDMA1_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2 2353 + #define SDMA1_CNTL__DATA_SWAP_ENABLE_MASK 0x8 2354 + #define SDMA1_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3 2355 + #define SDMA1_CNTL__FENCE_SWAP_ENABLE_MASK 0x10 2356 + #define SDMA1_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4 2357 + #define SDMA1_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x20 2358 + #define SDMA1_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5 2359 + #define SDMA1_CNTL__MC_WRREQ_CREDIT_MASK 0x1f800 2360 + #define SDMA1_CNTL__MC_WRREQ_CREDIT__SHIFT 0xb 2361 + #define SDMA1_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x20000 2362 + #define SDMA1_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11 2363 + #define SDMA1_CNTL__AUTO_CTXSW_ENABLE_MASK 0x40000 2364 + #define SDMA1_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12 2365 + #define SDMA1_CNTL__MC_RDREQ_CREDIT_MASK 0xfc00000 2366 + #define SDMA1_CNTL__MC_RDREQ_CREDIT__SHIFT 0x16 2367 + #define SDMA1_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000 2368 + #define SDMA1_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c 2369 + #define SDMA1_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000 2370 + #define SDMA1_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d 2371 + #define SDMA1_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000 2372 + #define SDMA1_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e 2373 + #define SDMA1_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x1 2374 + #define SDMA1_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0 2375 + #define SDMA1_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x2 2376 + #define SDMA1_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1 2377 + #define SDMA1_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x4 2378 + #define SDMA1_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2 2379 + #define SDMA1_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x10000 2380 + #define SDMA1_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10 2381 + #define SDMA1_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x100000 2382 + #define SDMA1_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14 2383 + #define SDMA1_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x800000 2384 + #define SDMA1_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17 2385 + #define SDMA1_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK 0xc000000 2386 + #define SDMA1_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT 0x1a 2387 + #define SDMA1_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK 0x30000000 2388 + #define SDMA1_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT 0x1c 2389 + #define SDMA1_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK 0xc0000000 2390 + #define SDMA1_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT 0x1e 2391 + #define SDMA1_TILING_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 2392 + #define SDMA1_TILING_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 2393 + #define SDMA1_HASH__CHANNEL_BITS_MASK 0x7 2394 + #define SDMA1_HASH__CHANNEL_BITS__SHIFT 0x0 2395 + #define SDMA1_HASH__BANK_BITS_MASK 0x70 2396 + #define SDMA1_HASH__BANK_BITS__SHIFT 0x4 2397 + #define SDMA1_HASH__CHANNEL_XOR_COUNT_MASK 0x700 2398 + #define SDMA1_HASH__CHANNEL_XOR_COUNT__SHIFT 0x8 2399 + #define SDMA1_HASH__BANK_XOR_COUNT_MASK 0x7000 2400 + #define SDMA1_HASH__BANK_XOR_COUNT__SHIFT 0xc 2401 + #define SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xffffffff 2402 + #define SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0 2403 + #define SDMA1_RB_RPTR_FETCH__OFFSET_MASK 0xfffffffc 2404 + #define SDMA1_RB_RPTR_FETCH__OFFSET__SHIFT 0x2 2405 + #define SDMA1_IB_OFFSET_FETCH__OFFSET_MASK 0x3ffffc 2406 + #define SDMA1_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2 2407 + #define SDMA1_PROGRAM__STREAM_MASK 0xffffffff 2408 + #define SDMA1_PROGRAM__STREAM__SHIFT 0x0 2409 + #define SDMA1_STATUS_REG__IDLE_MASK 0x1 2410 + #define SDMA1_STATUS_REG__IDLE__SHIFT 0x0 2411 + #define SDMA1_STATUS_REG__REG_IDLE_MASK 0x2 2412 + #define SDMA1_STATUS_REG__REG_IDLE__SHIFT 0x1 2413 + #define SDMA1_STATUS_REG__RB_EMPTY_MASK 0x4 2414 + #define SDMA1_STATUS_REG__RB_EMPTY__SHIFT 0x2 2415 + #define SDMA1_STATUS_REG__RB_FULL_MASK 0x8 2416 + #define SDMA1_STATUS_REG__RB_FULL__SHIFT 0x3 2417 + #define SDMA1_STATUS_REG__RB_CMD_IDLE_MASK 0x10 2418 + #define SDMA1_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4 2419 + #define SDMA1_STATUS_REG__RB_CMD_FULL_MASK 0x20 2420 + #define SDMA1_STATUS_REG__RB_CMD_FULL__SHIFT 0x5 2421 + #define SDMA1_STATUS_REG__IB_CMD_IDLE_MASK 0x40 2422 + #define SDMA1_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6 2423 + #define SDMA1_STATUS_REG__IB_CMD_FULL_MASK 0x80 2424 + #define SDMA1_STATUS_REG__IB_CMD_FULL__SHIFT 0x7 2425 + #define SDMA1_STATUS_REG__BLOCK_IDLE_MASK 0x100 2426 + #define SDMA1_STATUS_REG__BLOCK_IDLE__SHIFT 0x8 2427 + #define SDMA1_STATUS_REG__INSIDE_IB_MASK 0x200 2428 + #define SDMA1_STATUS_REG__INSIDE_IB__SHIFT 0x9 2429 + #define SDMA1_STATUS_REG__EX_IDLE_MASK 0x400 2430 + #define SDMA1_STATUS_REG__EX_IDLE__SHIFT 0xa 2431 + #define SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x800 2432 + #define SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb 2433 + #define SDMA1_STATUS_REG__PACKET_READY_MASK 0x1000 2434 + #define SDMA1_STATUS_REG__PACKET_READY__SHIFT 0xc 2435 + #define SDMA1_STATUS_REG__MC_WR_IDLE_MASK 0x2000 2436 + #define SDMA1_STATUS_REG__MC_WR_IDLE__SHIFT 0xd 2437 + #define SDMA1_STATUS_REG__SRBM_IDLE_MASK 0x4000 2438 + #define SDMA1_STATUS_REG__SRBM_IDLE__SHIFT 0xe 2439 + #define SDMA1_STATUS_REG__CONTEXT_EMPTY_MASK 0x8000 2440 + #define SDMA1_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf 2441 + #define SDMA1_STATUS_REG__DELTA_RPTR_FULL_MASK 0x10000 2442 + #define SDMA1_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10 2443 + #define SDMA1_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x20000 2444 + #define SDMA1_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11 2445 + #define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x40000 2446 + #define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12 2447 + #define SDMA1_STATUS_REG__MC_RD_IDLE_MASK 0x80000 2448 + #define SDMA1_STATUS_REG__MC_RD_IDLE__SHIFT 0x13 2449 + #define SDMA1_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x100000 2450 + #define SDMA1_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14 2451 + #define SDMA1_STATUS_REG__MC_RD_RET_STALL_MASK 0x200000 2452 + #define SDMA1_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15 2453 + #define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x400000 2454 + #define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16 2455 + #define SDMA1_STATUS_REG__PREV_CMD_IDLE_MASK 0x2000000 2456 + #define SDMA1_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19 2457 + #define SDMA1_STATUS_REG__SEM_IDLE_MASK 0x4000000 2458 + #define SDMA1_STATUS_REG__SEM_IDLE__SHIFT 0x1a 2459 + #define SDMA1_STATUS_REG__SEM_REQ_STALL_MASK 0x8000000 2460 + #define SDMA1_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b 2461 + #define SDMA1_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000 2462 + #define SDMA1_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c 2463 + #define SDMA1_STATUS_REG__INT_IDLE_MASK 0x40000000 2464 + #define SDMA1_STATUS_REG__INT_IDLE__SHIFT 0x1e 2465 + #define SDMA1_STATUS_REG__INT_REQ_STALL_MASK 0x80000000 2466 + #define SDMA1_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f 2467 + #define SDMA1_STATUS1_REG__CE_WREQ_IDLE_MASK 0x1 2468 + #define SDMA1_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0 2469 + #define SDMA1_STATUS1_REG__CE_WR_IDLE_MASK 0x2 2470 + #define SDMA1_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 2471 + #define SDMA1_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x4 2472 + #define SDMA1_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2 2473 + #define SDMA1_STATUS1_REG__CE_RREQ_IDLE_MASK 0x8 2474 + #define SDMA1_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3 2475 + #define SDMA1_STATUS1_REG__CE_OUT_IDLE_MASK 0x10 2476 + #define SDMA1_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4 2477 + #define SDMA1_STATUS1_REG__CE_IN_IDLE_MASK 0x20 2478 + #define SDMA1_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5 2479 + #define SDMA1_STATUS1_REG__CE_DST_IDLE_MASK 0x40 2480 + #define SDMA1_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6 2481 + #define SDMA1_STATUS1_REG__CE_CMD_IDLE_MASK 0x200 2482 + #define SDMA1_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9 2483 + #define SDMA1_STATUS1_REG__CE_AFIFO_FULL_MASK 0x400 2484 + #define SDMA1_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa 2485 + #define SDMA1_STATUS1_REG__CE_INFO_FULL_MASK 0x2000 2486 + #define SDMA1_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd 2487 + #define SDMA1_STATUS1_REG__CE_INFO1_FULL_MASK 0x4000 2488 + #define SDMA1_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe 2489 + #define SDMA1_STATUS1_REG__CE_RD_STALL_MASK 0x20000 2490 + #define SDMA1_STATUS1_REG__CE_RD_STALL__SHIFT 0x11 2491 + #define SDMA1_STATUS1_REG__CE_WR_STALL_MASK 0x40000 2492 + #define SDMA1_STATUS1_REG__CE_WR_STALL__SHIFT 0x12 2493 + #define SDMA1_RD_BURST_CNTL__RD_BURST_MASK 0x3 2494 + #define SDMA1_RD_BURST_CNTL__RD_BURST__SHIFT 0x0 2495 + #define SDMA1_PERFMON_CNTL__PERF_ENABLE0_MASK 0x1 2496 + #define SDMA1_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0 2497 + #define SDMA1_PERFMON_CNTL__PERF_CLEAR0_MASK 0x2 2498 + #define SDMA1_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1 2499 + #define SDMA1_PERFMON_CNTL__PERF_SEL0_MASK 0xfc 2500 + #define SDMA1_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2 2501 + #define SDMA1_PERFMON_CNTL__PERF_ENABLE1_MASK 0x100 2502 + #define SDMA1_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0x8 2503 + #define SDMA1_PERFMON_CNTL__PERF_CLEAR1_MASK 0x200 2504 + #define SDMA1_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0x9 2505 + #define SDMA1_PERFMON_CNTL__PERF_SEL1_MASK 0xfc00 2506 + #define SDMA1_PERFMON_CNTL__PERF_SEL1__SHIFT 0xa 2507 + #define SDMA1_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xffffffff 2508 + #define SDMA1_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0 2509 + #define SDMA1_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xffffffff 2510 + #define SDMA1_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0 2511 + #define SDMA1_F32_CNTL__HALT_MASK 0x1 2512 + #define SDMA1_F32_CNTL__HALT__SHIFT 0x0 2513 + #define SDMA1_F32_CNTL__STEP_MASK 0x2 2514 + #define SDMA1_F32_CNTL__STEP__SHIFT 0x1 2515 + #define SDMA1_F32_CNTL__DBG_SELECT_BITS_MASK 0xfc 2516 + #define SDMA1_F32_CNTL__DBG_SELECT_BITS__SHIFT 0x2 2517 + #define SDMA1_FREEZE__FREEZE_MASK 0x10 2518 + #define SDMA1_FREEZE__FREEZE__SHIFT 0x4 2519 + #define SDMA1_FREEZE__FROZEN_MASK 0x20 2520 + #define SDMA1_FREEZE__FROZEN__SHIFT 0x5 2521 + #define SDMA1_FREEZE__F32_FREEZE_MASK 0x40 2522 + #define SDMA1_FREEZE__F32_FREEZE__SHIFT 0x6 2523 + #define SDMA1_PHASE0_QUANTUM__UNIT_MASK 0xf 2524 + #define SDMA1_PHASE0_QUANTUM__UNIT__SHIFT 0x0 2525 + #define SDMA1_PHASE0_QUANTUM__VALUE_MASK 0xffff00 2526 + #define SDMA1_PHASE0_QUANTUM__VALUE__SHIFT 0x8 2527 + #define SDMA1_PHASE0_QUANTUM__PREFER_MASK 0x40000000 2528 + #define SDMA1_PHASE0_QUANTUM__PREFER__SHIFT 0x1e 2529 + #define SDMA1_PHASE1_QUANTUM__UNIT_MASK 0xf 2530 + #define SDMA1_PHASE1_QUANTUM__UNIT__SHIFT 0x0 2531 + #define SDMA1_PHASE1_QUANTUM__VALUE_MASK 0xffff00 2532 + #define SDMA1_PHASE1_QUANTUM__VALUE__SHIFT 0x8 2533 + #define SDMA1_PHASE1_QUANTUM__PREFER_MASK 0x40000000 2534 + #define SDMA1_PHASE1_QUANTUM__PREFER__SHIFT 0x1e 2535 + #define SDMA1_EDC_CONFIG__DIS_EDC_MASK 0x2 2536 + #define SDMA1_EDC_CONFIG__DIS_EDC__SHIFT 0x1 2537 + #define SDMA1_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x4 2538 + #define SDMA1_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2 2539 + #define SDMA1_VM_CNTL__CMD_MASK 0xf 2540 + #define SDMA1_VM_CNTL__CMD__SHIFT 0x0 2541 + #define SDMA1_VM_CTX_LO__ADDR_MASK 0xfffffffc 2542 + #define SDMA1_VM_CTX_LO__ADDR__SHIFT 0x2 2543 + #define SDMA1_VM_CTX_HI__ADDR_MASK 0xffffffff 2544 + #define SDMA1_VM_CTX_HI__ADDR__SHIFT 0x0 2545 + #define SDMA1_STATUS2_REG__ID_MASK 0x3 2546 + #define SDMA1_STATUS2_REG__ID__SHIFT 0x0 2547 + #define SDMA1_STATUS2_REG__F32_INSTR_PTR_MASK 0xffc 2548 + #define SDMA1_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x2 2549 + #define SDMA1_STATUS2_REG__CURRENT_FCN_IDLE_MASK 0xc000 2550 + #define SDMA1_STATUS2_REG__CURRENT_FCN_IDLE__SHIFT 0xe 2551 + #define SDMA1_STATUS2_REG__CMD_OP_MASK 0xffff0000 2552 + #define SDMA1_STATUS2_REG__CMD_OP__SHIFT 0x10 2553 + #define SDMA1_ACTIVE_FCN_ID__VFID_MASK 0xf 2554 + #define SDMA1_ACTIVE_FCN_ID__VFID__SHIFT 0x0 2555 + #define SDMA1_ACTIVE_FCN_ID__VF_MASK 0x80000000 2556 + #define SDMA1_ACTIVE_FCN_ID__VF__SHIFT 0x1f 2557 + #define SDMA1_VM_CTX_CNTL__PRIV_MASK 0x1 2558 + #define SDMA1_VM_CTX_CNTL__PRIV__SHIFT 0x0 2559 + #define SDMA1_VM_CTX_CNTL__VMID_MASK 0xf0 2560 + #define SDMA1_VM_CTX_CNTL__VMID__SHIFT 0x4 2561 + #define SDMA1_VIRT_RESET_REQ__VF_MASK 0xffff 2562 + #define SDMA1_VIRT_RESET_REQ__VF__SHIFT 0x0 2563 + #define SDMA1_VIRT_RESET_REQ__PF_MASK 0x80000000 2564 + #define SDMA1_VIRT_RESET_REQ__PF__SHIFT 0x1f 2565 + #define SDMA1_VF_ENABLE__VF_ENABLE_MASK 0x1 2566 + #define SDMA1_VF_ENABLE__VF_ENABLE__SHIFT 0x0 2567 + #define SDMA1_BA_THRESHOLD__READ_THRES_MASK 0x3ff 2568 + #define SDMA1_BA_THRESHOLD__READ_THRES__SHIFT 0x0 2569 + #define SDMA1_BA_THRESHOLD__WRITE_THRES_MASK 0x3ff0000 2570 + #define SDMA1_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10 2571 + #define SDMA1_ID__DEVICE_ID_MASK 0xff 2572 + #define SDMA1_ID__DEVICE_ID__SHIFT 0x0 2573 + #define SDMA1_VERSION__VALUE_MASK 0xffff 2574 + #define SDMA1_VERSION__VALUE__SHIFT 0x0 2575 + #define SDMA1_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7fffffff 2576 + #define SDMA1_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0 2577 + #define SDMA1_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000 2578 + #define SDMA1_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f 2579 + #define SDMA1_ATOMIC_PREOP_LO__DATA_MASK 0xffffffff 2580 + #define SDMA1_ATOMIC_PREOP_LO__DATA__SHIFT 0x0 2581 + #define SDMA1_ATOMIC_PREOP_HI__DATA_MASK 0xffffffff 2582 + #define SDMA1_ATOMIC_PREOP_HI__DATA__SHIFT 0x0 2583 + #define SDMA1_POWER_CNTL_IDLE__DELAY1_MASK 0xffff 2584 + #define SDMA1_POWER_CNTL_IDLE__DELAY1__SHIFT 0x0 2585 + #define SDMA1_POWER_CNTL_IDLE__DELAY2_MASK 0xffff0000 2586 + #define SDMA1_POWER_CNTL_IDLE__DELAY2__SHIFT 0x10 2587 + #define SDMA1_PERF_REG_TYPE0__SDMA1_PERFMON_CNTL_MASK 0x1 2588 + #define SDMA1_PERF_REG_TYPE0__SDMA1_PERFMON_CNTL__SHIFT 0x0 2589 + #define SDMA1_PERF_REG_TYPE0__SDMA1_PERFCOUNTER0_RESULT_MASK 0x2 2590 + #define SDMA1_PERF_REG_TYPE0__SDMA1_PERFCOUNTER0_RESULT__SHIFT 0x1 2591 + #define SDMA1_PERF_REG_TYPE0__SDMA1_PERFCOUNTER1_RESULT_MASK 0x4 2592 + #define SDMA1_PERF_REG_TYPE0__SDMA1_PERFCOUNTER1_RESULT__SHIFT 0x2 2593 + #define SDMA1_PERF_REG_TYPE0__RESERVED_31_3_MASK 0xfffffff8 2594 + #define SDMA1_PERF_REG_TYPE0__RESERVED_31_3__SHIFT 0x3 2595 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_CNTL_MASK 0x1 2596 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_CNTL__SHIFT 0x0 2597 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_MASK 0x2 2598 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE__SHIFT 0x1 2599 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_HI_MASK 0x4 2600 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_HI__SHIFT 0x2 2601 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_MASK 0x8 2602 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR__SHIFT 0x3 2603 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_MASK 0x10 2604 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR__SHIFT 0x4 2605 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_CNTL_MASK 0x20 2606 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_CNTL__SHIFT 0x5 2607 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_ADDR_HI_MASK 0x40 2608 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT 0x6 2609 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_ADDR_LO_MASK 0x80 2610 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT 0x7 2611 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_HI_MASK 0x100 2612 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_HI__SHIFT 0x8 2613 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_LO_MASK 0x200 2614 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_LO__SHIFT 0x9 2615 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_CNTL_MASK 0x400 2616 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_CNTL__SHIFT 0xa 2617 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_RPTR_MASK 0x800 2618 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_RPTR__SHIFT 0xb 2619 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_OFFSET_MASK 0x1000 2620 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_OFFSET__SHIFT 0xc 2621 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_LO_MASK 0x2000 2622 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_LO__SHIFT 0xd 2623 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_HI_MASK 0x4000 2624 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_HI__SHIFT 0xe 2625 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_SIZE_MASK 0x8000 2626 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_SIZE__SHIFT 0xf 2627 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_SKIP_CNTL_MASK 0x10000 2628 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_SKIP_CNTL__SHIFT 0x10 2629 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_STATUS_MASK 0x20000 2630 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_STATUS__SHIFT 0x11 2631 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_DOORBELL_MASK 0x40000 2632 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_DOORBELL__SHIFT 0x12 2633 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_CNTL_MASK 0x80000 2634 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_CNTL__SHIFT 0x13 2635 + #define SDMA1_CONTEXT_REG_TYPE0__RESERVED_MASK 0xfff00000 2636 + #define SDMA1_CONTEXT_REG_TYPE0__RESERVED__SHIFT 0x14 2637 + #define SDMA1_CONTEXT_REG_TYPE1__VOID_REG0_MASK 0x7f 2638 + #define SDMA1_CONTEXT_REG_TYPE1__VOID_REG0__SHIFT 0x0 2639 + #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_VIRTUAL_ADDR_MASK 0x80 2640 + #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_VIRTUAL_ADDR__SHIFT 0x7 2641 + #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_APE1_CNTL_MASK 0x100 2642 + #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_APE1_CNTL__SHIFT 0x8 2643 + #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_LOG_MASK 0x200 2644 + #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_LOG__SHIFT 0x9 2645 + #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_WATERMARK_MASK 0x400 2646 + #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_WATERMARK__SHIFT 0xa 2647 + #define SDMA1_CONTEXT_REG_TYPE1__VOID_REG2_MASK 0x800 2648 + #define SDMA1_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT 0xb 2649 + #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_LO_MASK 0x1000 2650 + #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_LO__SHIFT 0xc 2651 + #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_HI_MASK 0x2000 2652 + #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_HI__SHIFT 0xd 2653 + #define SDMA1_CONTEXT_REG_TYPE1__VOID_REG3_MASK 0x4000 2654 + #define SDMA1_CONTEXT_REG_TYPE1__VOID_REG3__SHIFT 0xe 2655 + #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_IB_SUB_REMAIN_MASK 0x8000 2656 + #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_IB_SUB_REMAIN__SHIFT 0xf 2657 + #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_PREEMPT_MASK 0x10000 2658 + #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_PREEMPT__SHIFT 0x10 2659 + #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DUMMY_REG_MASK 0x20000 2660 + #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DUMMY_REG__SHIFT 0x11 2661 + #define SDMA1_CONTEXT_REG_TYPE1__RESERVED_MASK 0xfffc0000 2662 + #define SDMA1_CONTEXT_REG_TYPE1__RESERVED__SHIFT 0x12 2663 + #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA0_MASK 0x1 2664 + #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA0__SHIFT 0x0 2665 + #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA1_MASK 0x2 2666 + #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA1__SHIFT 0x1 2667 + #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA2_MASK 0x4 2668 + #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA2__SHIFT 0x2 2669 + #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA3_MASK 0x8 2670 + #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA3__SHIFT 0x3 2671 + #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA4_MASK 0x10 2672 + #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA4__SHIFT 0x4 2673 + #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA5_MASK 0x20 2674 + #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA5__SHIFT 0x5 2675 + #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_CNTL_MASK 0x40 2676 + #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_CNTL__SHIFT 0x6 2677 + #define SDMA1_CONTEXT_REG_TYPE2__RESERVED_MASK 0xffffff80 2678 + #define SDMA1_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0x7 2679 + #define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_ADDR_MASK 0x1 2680 + #define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_ADDR__SHIFT 0x0 2681 + #define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_DATA_MASK 0x2 2682 + #define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_DATA__SHIFT 0x1 2683 + #define SDMA1_PUB_REG_TYPE0__SDMA1_POWER_CNTL_MASK 0x4 2684 + #define SDMA1_PUB_REG_TYPE0__SDMA1_POWER_CNTL__SHIFT 0x2 2685 + #define SDMA1_PUB_REG_TYPE0__SDMA1_CLK_CTRL_MASK 0x8 2686 + #define SDMA1_PUB_REG_TYPE0__SDMA1_CLK_CTRL__SHIFT 0x3 2687 + #define SDMA1_PUB_REG_TYPE0__SDMA1_CNTL_MASK 0x10 2688 + #define SDMA1_PUB_REG_TYPE0__SDMA1_CNTL__SHIFT 0x4 2689 + #define SDMA1_PUB_REG_TYPE0__SDMA1_CHICKEN_BITS_MASK 0x20 2690 + #define SDMA1_PUB_REG_TYPE0__SDMA1_CHICKEN_BITS__SHIFT 0x5 2691 + #define SDMA1_PUB_REG_TYPE0__SDMA1_TILING_CONFIG_MASK 0x40 2692 + #define SDMA1_PUB_REG_TYPE0__SDMA1_TILING_CONFIG__SHIFT 0x6 2693 + #define SDMA1_PUB_REG_TYPE0__SDMA1_HASH_MASK 0x80 2694 + #define SDMA1_PUB_REG_TYPE0__SDMA1_HASH__SHIFT 0x7 2695 + #define SDMA1_PUB_REG_TYPE0__SDMA1_SEM_WAIT_FAIL_TIMER_CNTL_MASK 0x200 2696 + #define SDMA1_PUB_REG_TYPE0__SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__SHIFT 0x9 2697 + #define SDMA1_PUB_REG_TYPE0__SDMA1_RB_RPTR_FETCH_MASK 0x400 2698 + #define SDMA1_PUB_REG_TYPE0__SDMA1_RB_RPTR_FETCH__SHIFT 0xa 2699 + #define SDMA1_PUB_REG_TYPE0__SDMA1_IB_OFFSET_FETCH_MASK 0x800 2700 + #define SDMA1_PUB_REG_TYPE0__SDMA1_IB_OFFSET_FETCH__SHIFT 0xb 2701 + #define SDMA1_PUB_REG_TYPE0__SDMA1_PROGRAM_MASK 0x1000 2702 + #define SDMA1_PUB_REG_TYPE0__SDMA1_PROGRAM__SHIFT 0xc 2703 + #define SDMA1_PUB_REG_TYPE0__SDMA1_STATUS_REG_MASK 0x2000 2704 + #define SDMA1_PUB_REG_TYPE0__SDMA1_STATUS_REG__SHIFT 0xd 2705 + #define SDMA1_PUB_REG_TYPE0__SDMA1_STATUS1_REG_MASK 0x4000 2706 + #define SDMA1_PUB_REG_TYPE0__SDMA1_STATUS1_REG__SHIFT 0xe 2707 + #define SDMA1_PUB_REG_TYPE0__SDMA1_RD_BURST_CNTL_MASK 0x8000 2708 + #define SDMA1_PUB_REG_TYPE0__SDMA1_RD_BURST_CNTL__SHIFT 0xf 2709 + #define SDMA1_PUB_REG_TYPE0__RESERVED_16_MASK 0x10000 2710 + #define SDMA1_PUB_REG_TYPE0__RESERVED_16__SHIFT 0x10 2711 + #define SDMA1_PUB_REG_TYPE0__RESERVED_17_MASK 0x20000 2712 + #define SDMA1_PUB_REG_TYPE0__RESERVED_17__SHIFT 0x11 2713 + #define SDMA1_PUB_REG_TYPE0__SDMA1_F32_CNTL_MASK 0x40000 2714 + #define SDMA1_PUB_REG_TYPE0__SDMA1_F32_CNTL__SHIFT 0x12 2715 + #define SDMA1_PUB_REG_TYPE0__SDMA1_FREEZE_MASK 0x80000 2716 + #define SDMA1_PUB_REG_TYPE0__SDMA1_FREEZE__SHIFT 0x13 2717 + #define SDMA1_PUB_REG_TYPE0__SDMA1_PHASE0_QUANTUM_MASK 0x100000 2718 + #define SDMA1_PUB_REG_TYPE0__SDMA1_PHASE0_QUANTUM__SHIFT 0x14 2719 + #define SDMA1_PUB_REG_TYPE0__SDMA1_PHASE1_QUANTUM_MASK 0x200000 2720 + #define SDMA1_PUB_REG_TYPE0__SDMA1_PHASE1_QUANTUM__SHIFT 0x15 2721 + #define SDMA1_PUB_REG_TYPE0__VOID_REG0_MASK 0x3c00000 2722 + #define SDMA1_PUB_REG_TYPE0__VOID_REG0__SHIFT 0x16 2723 + #define SDMA1_PUB_REG_TYPE0__SDMA1_EDC_CONFIG_MASK 0x4000000 2724 + #define SDMA1_PUB_REG_TYPE0__SDMA1_EDC_CONFIG__SHIFT 0x1a 2725 + #define SDMA1_PUB_REG_TYPE0__SDMA1_BA_THRESHOLD_MASK 0x8000000 2726 + #define SDMA1_PUB_REG_TYPE0__SDMA1_BA_THRESHOLD__SHIFT 0x1b 2727 + #define SDMA1_PUB_REG_TYPE0__SDMA1_DEVICE_ID_MASK 0x10000000 2728 + #define SDMA1_PUB_REG_TYPE0__SDMA1_DEVICE_ID__SHIFT 0x1c 2729 + #define SDMA1_PUB_REG_TYPE0__SDMA1_VERSION_MASK 0x20000000 2730 + #define SDMA1_PUB_REG_TYPE0__SDMA1_VERSION__SHIFT 0x1d 2731 + #define SDMA1_PUB_REG_TYPE0__RESERVED_MASK 0xc0000000 2732 + #define SDMA1_PUB_REG_TYPE0__RESERVED__SHIFT 0x1e 2733 + #define SDMA1_PUB_REG_TYPE1__SDMA1_VM_CNTL_MASK 0x1 2734 + #define SDMA1_PUB_REG_TYPE1__SDMA1_VM_CNTL__SHIFT 0x0 2735 + #define SDMA1_PUB_REG_TYPE1__SDMA1_VM_CTX_LO_MASK 0x2 2736 + #define SDMA1_PUB_REG_TYPE1__SDMA1_VM_CTX_LO__SHIFT 0x1 2737 + #define SDMA1_PUB_REG_TYPE1__SDMA1_VM_CTX_HI_MASK 0x4 2738 + #define SDMA1_PUB_REG_TYPE1__SDMA1_VM_CTX_HI__SHIFT 0x2 2739 + #define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS2_REG_MASK 0x8 2740 + #define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS2_REG__SHIFT 0x3 2741 + #define SDMA1_PUB_REG_TYPE1__SDMA1_ACTIVE_FCN_ID_MASK 0x10 2742 + #define SDMA1_PUB_REG_TYPE1__SDMA1_ACTIVE_FCN_ID__SHIFT 0x4 2743 + #define SDMA1_PUB_REG_TYPE1__SDMA1_VM_CTX_CNTL_MASK 0x20 2744 + #define SDMA1_PUB_REG_TYPE1__SDMA1_VM_CTX_CNTL__SHIFT 0x5 2745 + #define SDMA1_PUB_REG_TYPE1__SDMA1_VIRT_RESET_REQ_MASK 0x40 2746 + #define SDMA1_PUB_REG_TYPE1__SDMA1_VIRT_RESET_REQ__SHIFT 0x6 2747 + #define SDMA1_PUB_REG_TYPE1__SDMA1_VF_ENABLE_MASK 0x80 2748 + #define SDMA1_PUB_REG_TYPE1__SDMA1_VF_ENABLE__SHIFT 0x7 2749 + #define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_CNTL_MASK 0x100 2750 + #define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_CNTL__SHIFT 0x8 2751 + #define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_LO_MASK 0x200 2752 + #define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_LO__SHIFT 0x9 2753 + #define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_HI_MASK 0x400 2754 + #define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_HI__SHIFT 0xa 2755 + #define SDMA1_PUB_REG_TYPE1__RESERVED_MASK 0xfffff800 2756 + #define SDMA1_PUB_REG_TYPE1__RESERVED__SHIFT 0xb 2757 + #define SDMA1_GFX_RB_CNTL__RB_ENABLE_MASK 0x1 2758 + #define SDMA1_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0 2759 + #define SDMA1_GFX_RB_CNTL__RB_SIZE_MASK 0x3e 2760 + #define SDMA1_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1 2761 + #define SDMA1_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200 2762 + #define SDMA1_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 2763 + #define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000 2764 + #define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 2765 + #define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000 2766 + #define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 2767 + #define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000 2768 + #define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 2769 + #define SDMA1_GFX_RB_CNTL__RB_PRIV_MASK 0x800000 2770 + #define SDMA1_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17 2771 + #define SDMA1_GFX_RB_CNTL__RB_VMID_MASK 0xf000000 2772 + #define SDMA1_GFX_RB_CNTL__RB_VMID__SHIFT 0x18 2773 + #define SDMA1_GFX_RB_BASE__ADDR_MASK 0xffffffff 2774 + #define SDMA1_GFX_RB_BASE__ADDR__SHIFT 0x0 2775 + #define SDMA1_GFX_RB_BASE_HI__ADDR_MASK 0xffffff 2776 + #define SDMA1_GFX_RB_BASE_HI__ADDR__SHIFT 0x0 2777 + #define SDMA1_GFX_RB_RPTR__OFFSET_MASK 0xfffffffc 2778 + #define SDMA1_GFX_RB_RPTR__OFFSET__SHIFT 0x2 2779 + #define SDMA1_GFX_RB_WPTR__OFFSET_MASK 0xfffffffc 2780 + #define SDMA1_GFX_RB_WPTR__OFFSET__SHIFT 0x2 2781 + #define SDMA1_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1 2782 + #define SDMA1_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 2783 + #define SDMA1_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2 2784 + #define SDMA1_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 2785 + #define SDMA1_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x4 2786 + #define SDMA1_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 2787 + #define SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0 2788 + #define SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 2789 + #define SDMA1_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000 2790 + #define SDMA1_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 2791 + #define SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff 2792 + #define SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 2793 + #define SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc 2794 + #define SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 2795 + #define SDMA1_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff 2796 + #define SDMA1_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 2797 + #define SDMA1_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc 2798 + #define SDMA1_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 2799 + #define SDMA1_GFX_IB_CNTL__IB_ENABLE_MASK 0x1 2800 + #define SDMA1_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0 2801 + #define SDMA1_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10 2802 + #define SDMA1_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 2803 + #define SDMA1_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100 2804 + #define SDMA1_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 2805 + #define SDMA1_GFX_IB_CNTL__CMD_VMID_MASK 0xf0000 2806 + #define SDMA1_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10 2807 + #define SDMA1_GFX_IB_RPTR__OFFSET_MASK 0x3ffffc 2808 + #define SDMA1_GFX_IB_RPTR__OFFSET__SHIFT 0x2 2809 + #define SDMA1_GFX_IB_OFFSET__OFFSET_MASK 0x3ffffc 2810 + #define SDMA1_GFX_IB_OFFSET__OFFSET__SHIFT 0x2 2811 + #define SDMA1_GFX_IB_BASE_LO__ADDR_MASK 0xffffffe0 2812 + #define SDMA1_GFX_IB_BASE_LO__ADDR__SHIFT 0x5 2813 + #define SDMA1_GFX_IB_BASE_HI__ADDR_MASK 0xffffffff 2814 + #define SDMA1_GFX_IB_BASE_HI__ADDR__SHIFT 0x0 2815 + #define SDMA1_GFX_IB_SIZE__SIZE_MASK 0xfffff 2816 + #define SDMA1_GFX_IB_SIZE__SIZE__SHIFT 0x0 2817 + #define SDMA1_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff 2818 + #define SDMA1_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 2819 + #define SDMA1_GFX_CONTEXT_STATUS__SELECTED_MASK 0x1 2820 + #define SDMA1_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0 2821 + #define SDMA1_GFX_CONTEXT_STATUS__IDLE_MASK 0x4 2822 + #define SDMA1_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2 2823 + #define SDMA1_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x8 2824 + #define SDMA1_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 2825 + #define SDMA1_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x70 2826 + #define SDMA1_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 2827 + #define SDMA1_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80 2828 + #define SDMA1_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 2829 + #define SDMA1_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x100 2830 + #define SDMA1_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 2831 + #define SDMA1_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x200 2832 + #define SDMA1_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 2833 + #define SDMA1_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x400 2834 + #define SDMA1_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 2835 + #define SDMA1_GFX_DOORBELL__OFFSET_MASK 0x1fffff 2836 + #define SDMA1_GFX_DOORBELL__OFFSET__SHIFT 0x0 2837 + #define SDMA1_GFX_DOORBELL__ENABLE_MASK 0x10000000 2838 + #define SDMA1_GFX_DOORBELL__ENABLE__SHIFT 0x1c 2839 + #define SDMA1_GFX_DOORBELL__CAPTURED_MASK 0x40000000 2840 + #define SDMA1_GFX_DOORBELL__CAPTURED__SHIFT 0x1e 2841 + #define SDMA1_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x10000 2842 + #define SDMA1_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10 2843 + #define SDMA1_GFX_CONTEXT_CNTL__SESSION_SEL_MASK 0xf000000 2844 + #define SDMA1_GFX_CONTEXT_CNTL__SESSION_SEL__SHIFT 0x18 2845 + #define SDMA1_GFX_VIRTUAL_ADDR__ATC_MASK 0x1 2846 + #define SDMA1_GFX_VIRTUAL_ADDR__ATC__SHIFT 0x0 2847 + #define SDMA1_GFX_VIRTUAL_ADDR__INVAL_MASK 0x2 2848 + #define SDMA1_GFX_VIRTUAL_ADDR__INVAL__SHIFT 0x1 2849 + #define SDMA1_GFX_VIRTUAL_ADDR__PTR32_MASK 0x10 2850 + #define SDMA1_GFX_VIRTUAL_ADDR__PTR32__SHIFT 0x4 2851 + #define SDMA1_GFX_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700 2852 + #define SDMA1_GFX_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8 2853 + #define SDMA1_GFX_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000 2854 + #define SDMA1_GFX_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e 2855 + #define SDMA1_GFX_APE1_CNTL__BASE_MASK 0xffff 2856 + #define SDMA1_GFX_APE1_CNTL__BASE__SHIFT 0x0 2857 + #define SDMA1_GFX_APE1_CNTL__LIMIT_MASK 0xffff0000 2858 + #define SDMA1_GFX_APE1_CNTL__LIMIT__SHIFT 0x10 2859 + #define SDMA1_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x1 2860 + #define SDMA1_GFX_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 2861 + #define SDMA1_GFX_DOORBELL_LOG__DATA_MASK 0xfffffffc 2862 + #define SDMA1_GFX_DOORBELL_LOG__DATA__SHIFT 0x2 2863 + #define SDMA1_GFX_WATERMARK__RD_OUTSTANDING_MASK 0xfff 2864 + #define SDMA1_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 2865 + #define SDMA1_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000 2866 + #define SDMA1_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 2867 + #define SDMA1_GFX_CSA_ADDR_LO__ADDR_MASK 0xfffffffc 2868 + #define SDMA1_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2 2869 + #define SDMA1_GFX_CSA_ADDR_HI__ADDR_MASK 0xffffffff 2870 + #define SDMA1_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0 2871 + #define SDMA1_GFX_IB_SUB_REMAIN__SIZE_MASK 0x3fff 2872 + #define SDMA1_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0 2873 + #define SDMA1_GFX_PREEMPT__IB_PREEMPT_MASK 0x1 2874 + #define SDMA1_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0 2875 + #define SDMA1_GFX_DUMMY_REG__DUMMY_MASK 0xffffffff 2876 + #define SDMA1_GFX_DUMMY_REG__DUMMY__SHIFT 0x0 2877 + #define SDMA1_GFX_MIDCMD_DATA0__DATA0_MASK 0xffffffff 2878 + #define SDMA1_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0 2879 + #define SDMA1_GFX_MIDCMD_DATA1__DATA1_MASK 0xffffffff 2880 + #define SDMA1_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0 2881 + #define SDMA1_GFX_MIDCMD_DATA2__DATA2_MASK 0xffffffff 2882 + #define SDMA1_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0 2883 + #define SDMA1_GFX_MIDCMD_DATA3__DATA3_MASK 0xffffffff 2884 + #define SDMA1_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0 2885 + #define SDMA1_GFX_MIDCMD_DATA4__DATA4_MASK 0xffffffff 2886 + #define SDMA1_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0 2887 + #define SDMA1_GFX_MIDCMD_DATA5__DATA5_MASK 0xffffffff 2888 + #define SDMA1_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0 2889 + #define SDMA1_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x1 2890 + #define SDMA1_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 2891 + #define SDMA1_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x2 2892 + #define SDMA1_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 2893 + #define SDMA1_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0xf0 2894 + #define SDMA1_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 2895 + #define SDMA1_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x100 2896 + #define SDMA1_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 2897 + #define SDMA1_RLC0_RB_CNTL__RB_ENABLE_MASK 0x1 2898 + #define SDMA1_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0 2899 + #define SDMA1_RLC0_RB_CNTL__RB_SIZE_MASK 0x3e 2900 + #define SDMA1_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1 2901 + #define SDMA1_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200 2902 + #define SDMA1_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 2903 + #define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000 2904 + #define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 2905 + #define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000 2906 + #define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 2907 + #define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000 2908 + #define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 2909 + #define SDMA1_RLC0_RB_CNTL__RB_PRIV_MASK 0x800000 2910 + #define SDMA1_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17 2911 + #define SDMA1_RLC0_RB_CNTL__RB_VMID_MASK 0xf000000 2912 + #define SDMA1_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18 2913 + #define SDMA1_RLC0_RB_BASE__ADDR_MASK 0xffffffff 2914 + #define SDMA1_RLC0_RB_BASE__ADDR__SHIFT 0x0 2915 + #define SDMA1_RLC0_RB_BASE_HI__ADDR_MASK 0xffffff 2916 + #define SDMA1_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0 2917 + #define SDMA1_RLC0_RB_RPTR__OFFSET_MASK 0xfffffffc 2918 + #define SDMA1_RLC0_RB_RPTR__OFFSET__SHIFT 0x2 2919 + #define SDMA1_RLC0_RB_WPTR__OFFSET_MASK 0xfffffffc 2920 + #define SDMA1_RLC0_RB_WPTR__OFFSET__SHIFT 0x2 2921 + #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1 2922 + #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 2923 + #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2 2924 + #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 2925 + #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x4 2926 + #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 2927 + #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0 2928 + #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 2929 + #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000 2930 + #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 2931 + #define SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff 2932 + #define SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 2933 + #define SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc 2934 + #define SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 2935 + #define SDMA1_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff 2936 + #define SDMA1_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 2937 + #define SDMA1_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc 2938 + #define SDMA1_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 2939 + #define SDMA1_RLC0_IB_CNTL__IB_ENABLE_MASK 0x1 2940 + #define SDMA1_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0 2941 + #define SDMA1_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10 2942 + #define SDMA1_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 2943 + #define SDMA1_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100 2944 + #define SDMA1_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 2945 + #define SDMA1_RLC0_IB_CNTL__CMD_VMID_MASK 0xf0000 2946 + #define SDMA1_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10 2947 + #define SDMA1_RLC0_IB_RPTR__OFFSET_MASK 0x3ffffc 2948 + #define SDMA1_RLC0_IB_RPTR__OFFSET__SHIFT 0x2 2949 + #define SDMA1_RLC0_IB_OFFSET__OFFSET_MASK 0x3ffffc 2950 + #define SDMA1_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2 2951 + #define SDMA1_RLC0_IB_BASE_LO__ADDR_MASK 0xffffffe0 2952 + #define SDMA1_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5 2953 + #define SDMA1_RLC0_IB_BASE_HI__ADDR_MASK 0xffffffff 2954 + #define SDMA1_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0 2955 + #define SDMA1_RLC0_IB_SIZE__SIZE_MASK 0xfffff 2956 + #define SDMA1_RLC0_IB_SIZE__SIZE__SHIFT 0x0 2957 + #define SDMA1_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff 2958 + #define SDMA1_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 2959 + #define SDMA1_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x1 2960 + #define SDMA1_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0 2961 + #define SDMA1_RLC0_CONTEXT_STATUS__IDLE_MASK 0x4 2962 + #define SDMA1_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2 2963 + #define SDMA1_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x8 2964 + #define SDMA1_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 2965 + #define SDMA1_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x70 2966 + #define SDMA1_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 2967 + #define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80 2968 + #define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 2969 + #define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x100 2970 + #define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 2971 + #define SDMA1_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x200 2972 + #define SDMA1_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 2973 + #define SDMA1_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x400 2974 + #define SDMA1_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 2975 + #define SDMA1_RLC0_DOORBELL__OFFSET_MASK 0x1fffff 2976 + #define SDMA1_RLC0_DOORBELL__OFFSET__SHIFT 0x0 2977 + #define SDMA1_RLC0_DOORBELL__ENABLE_MASK 0x10000000 2978 + #define SDMA1_RLC0_DOORBELL__ENABLE__SHIFT 0x1c 2979 + #define SDMA1_RLC0_DOORBELL__CAPTURED_MASK 0x40000000 2980 + #define SDMA1_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e 2981 + #define SDMA1_RLC0_VIRTUAL_ADDR__ATC_MASK 0x1 2982 + #define SDMA1_RLC0_VIRTUAL_ADDR__ATC__SHIFT 0x0 2983 + #define SDMA1_RLC0_VIRTUAL_ADDR__INVAL_MASK 0x2 2984 + #define SDMA1_RLC0_VIRTUAL_ADDR__INVAL__SHIFT 0x1 2985 + #define SDMA1_RLC0_VIRTUAL_ADDR__PTR32_MASK 0x10 2986 + #define SDMA1_RLC0_VIRTUAL_ADDR__PTR32__SHIFT 0x4 2987 + #define SDMA1_RLC0_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700 2988 + #define SDMA1_RLC0_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8 2989 + #define SDMA1_RLC0_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000 2990 + #define SDMA1_RLC0_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e 2991 + #define SDMA1_RLC0_APE1_CNTL__BASE_MASK 0xffff 2992 + #define SDMA1_RLC0_APE1_CNTL__BASE__SHIFT 0x0 2993 + #define SDMA1_RLC0_APE1_CNTL__LIMIT_MASK 0xffff0000 2994 + #define SDMA1_RLC0_APE1_CNTL__LIMIT__SHIFT 0x10 2995 + #define SDMA1_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x1 2996 + #define SDMA1_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 2997 + #define SDMA1_RLC0_DOORBELL_LOG__DATA_MASK 0xfffffffc 2998 + #define SDMA1_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2 2999 + #define SDMA1_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0xfff 3000 + #define SDMA1_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 3001 + #define SDMA1_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000 3002 + #define SDMA1_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 3003 + #define SDMA1_RLC0_CSA_ADDR_LO__ADDR_MASK 0xfffffffc 3004 + #define SDMA1_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2 3005 + #define SDMA1_RLC0_CSA_ADDR_HI__ADDR_MASK 0xffffffff 3006 + #define SDMA1_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0 3007 + #define SDMA1_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x3fff 3008 + #define SDMA1_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0 3009 + #define SDMA1_RLC0_PREEMPT__IB_PREEMPT_MASK 0x1 3010 + #define SDMA1_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0 3011 + #define SDMA1_RLC0_DUMMY_REG__DUMMY_MASK 0xffffffff 3012 + #define SDMA1_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0 3013 + #define SDMA1_RLC0_MIDCMD_DATA0__DATA0_MASK 0xffffffff 3014 + #define SDMA1_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0 3015 + #define SDMA1_RLC0_MIDCMD_DATA1__DATA1_MASK 0xffffffff 3016 + #define SDMA1_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0 3017 + #define SDMA1_RLC0_MIDCMD_DATA2__DATA2_MASK 0xffffffff 3018 + #define SDMA1_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0 3019 + #define SDMA1_RLC0_MIDCMD_DATA3__DATA3_MASK 0xffffffff 3020 + #define SDMA1_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0 3021 + #define SDMA1_RLC0_MIDCMD_DATA4__DATA4_MASK 0xffffffff 3022 + #define SDMA1_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0 3023 + #define SDMA1_RLC0_MIDCMD_DATA5__DATA5_MASK 0xffffffff 3024 + #define SDMA1_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0 3025 + #define SDMA1_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x1 3026 + #define SDMA1_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 3027 + #define SDMA1_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x2 3028 + #define SDMA1_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 3029 + #define SDMA1_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0xf0 3030 + #define SDMA1_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 3031 + #define SDMA1_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x100 3032 + #define SDMA1_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 3033 + #define SDMA1_RLC1_RB_CNTL__RB_ENABLE_MASK 0x1 3034 + #define SDMA1_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0 3035 + #define SDMA1_RLC1_RB_CNTL__RB_SIZE_MASK 0x3e 3036 + #define SDMA1_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1 3037 + #define SDMA1_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200 3038 + #define SDMA1_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 3039 + #define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000 3040 + #define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 3041 + #define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000 3042 + #define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 3043 + #define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000 3044 + #define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 3045 + #define SDMA1_RLC1_RB_CNTL__RB_PRIV_MASK 0x800000 3046 + #define SDMA1_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17 3047 + #define SDMA1_RLC1_RB_CNTL__RB_VMID_MASK 0xf000000 3048 + #define SDMA1_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18 3049 + #define SDMA1_RLC1_RB_BASE__ADDR_MASK 0xffffffff 3050 + #define SDMA1_RLC1_RB_BASE__ADDR__SHIFT 0x0 3051 + #define SDMA1_RLC1_RB_BASE_HI__ADDR_MASK 0xffffff 3052 + #define SDMA1_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0 3053 + #define SDMA1_RLC1_RB_RPTR__OFFSET_MASK 0xfffffffc 3054 + #define SDMA1_RLC1_RB_RPTR__OFFSET__SHIFT 0x2 3055 + #define SDMA1_RLC1_RB_WPTR__OFFSET_MASK 0xfffffffc 3056 + #define SDMA1_RLC1_RB_WPTR__OFFSET__SHIFT 0x2 3057 + #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1 3058 + #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 3059 + #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2 3060 + #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 3061 + #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x4 3062 + #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 3063 + #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0 3064 + #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 3065 + #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000 3066 + #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 3067 + #define SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff 3068 + #define SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 3069 + #define SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc 3070 + #define SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 3071 + #define SDMA1_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff 3072 + #define SDMA1_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 3073 + #define SDMA1_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc 3074 + #define SDMA1_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 3075 + #define SDMA1_RLC1_IB_CNTL__IB_ENABLE_MASK 0x1 3076 + #define SDMA1_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0 3077 + #define SDMA1_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10 3078 + #define SDMA1_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 3079 + #define SDMA1_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100 3080 + #define SDMA1_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 3081 + #define SDMA1_RLC1_IB_CNTL__CMD_VMID_MASK 0xf0000 3082 + #define SDMA1_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10 3083 + #define SDMA1_RLC1_IB_RPTR__OFFSET_MASK 0x3ffffc 3084 + #define SDMA1_RLC1_IB_RPTR__OFFSET__SHIFT 0x2 3085 + #define SDMA1_RLC1_IB_OFFSET__OFFSET_MASK 0x3ffffc 3086 + #define SDMA1_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2 3087 + #define SDMA1_RLC1_IB_BASE_LO__ADDR_MASK 0xffffffe0 3088 + #define SDMA1_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5 3089 + #define SDMA1_RLC1_IB_BASE_HI__ADDR_MASK 0xffffffff 3090 + #define SDMA1_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0 3091 + #define SDMA1_RLC1_IB_SIZE__SIZE_MASK 0xfffff 3092 + #define SDMA1_RLC1_IB_SIZE__SIZE__SHIFT 0x0 3093 + #define SDMA1_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff 3094 + #define SDMA1_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 3095 + #define SDMA1_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x1 3096 + #define SDMA1_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0 3097 + #define SDMA1_RLC1_CONTEXT_STATUS__IDLE_MASK 0x4 3098 + #define SDMA1_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2 3099 + #define SDMA1_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x8 3100 + #define SDMA1_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 3101 + #define SDMA1_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x70 3102 + #define SDMA1_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 3103 + #define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80 3104 + #define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 3105 + #define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x100 3106 + #define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 3107 + #define SDMA1_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x200 3108 + #define SDMA1_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 3109 + #define SDMA1_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x400 3110 + #define SDMA1_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 3111 + #define SDMA1_RLC1_DOORBELL__OFFSET_MASK 0x1fffff 3112 + #define SDMA1_RLC1_DOORBELL__OFFSET__SHIFT 0x0 3113 + #define SDMA1_RLC1_DOORBELL__ENABLE_MASK 0x10000000 3114 + #define SDMA1_RLC1_DOORBELL__ENABLE__SHIFT 0x1c 3115 + #define SDMA1_RLC1_DOORBELL__CAPTURED_MASK 0x40000000 3116 + #define SDMA1_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e 3117 + #define SDMA1_RLC1_VIRTUAL_ADDR__ATC_MASK 0x1 3118 + #define SDMA1_RLC1_VIRTUAL_ADDR__ATC__SHIFT 0x0 3119 + #define SDMA1_RLC1_VIRTUAL_ADDR__INVAL_MASK 0x2 3120 + #define SDMA1_RLC1_VIRTUAL_ADDR__INVAL__SHIFT 0x1 3121 + #define SDMA1_RLC1_VIRTUAL_ADDR__PTR32_MASK 0x10 3122 + #define SDMA1_RLC1_VIRTUAL_ADDR__PTR32__SHIFT 0x4 3123 + #define SDMA1_RLC1_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700 3124 + #define SDMA1_RLC1_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8 3125 + #define SDMA1_RLC1_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000 3126 + #define SDMA1_RLC1_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e 3127 + #define SDMA1_RLC1_APE1_CNTL__BASE_MASK 0xffff 3128 + #define SDMA1_RLC1_APE1_CNTL__BASE__SHIFT 0x0 3129 + #define SDMA1_RLC1_APE1_CNTL__LIMIT_MASK 0xffff0000 3130 + #define SDMA1_RLC1_APE1_CNTL__LIMIT__SHIFT 0x10 3131 + #define SDMA1_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x1 3132 + #define SDMA1_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 3133 + #define SDMA1_RLC1_DOORBELL_LOG__DATA_MASK 0xfffffffc 3134 + #define SDMA1_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2 3135 + #define SDMA1_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0xfff 3136 + #define SDMA1_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 3137 + #define SDMA1_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000 3138 + #define SDMA1_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 3139 + #define SDMA1_RLC1_CSA_ADDR_LO__ADDR_MASK 0xfffffffc 3140 + #define SDMA1_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2 3141 + #define SDMA1_RLC1_CSA_ADDR_HI__ADDR_MASK 0xffffffff 3142 + #define SDMA1_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0 3143 + #define SDMA1_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x3fff 3144 + #define SDMA1_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0 3145 + #define SDMA1_RLC1_PREEMPT__IB_PREEMPT_MASK 0x1 3146 + #define SDMA1_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0 3147 + #define SDMA1_RLC1_DUMMY_REG__DUMMY_MASK 0xffffffff 3148 + #define SDMA1_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0 3149 + #define SDMA1_RLC1_MIDCMD_DATA0__DATA0_MASK 0xffffffff 3150 + #define SDMA1_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0 3151 + #define SDMA1_RLC1_MIDCMD_DATA1__DATA1_MASK 0xffffffff 3152 + #define SDMA1_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0 3153 + #define SDMA1_RLC1_MIDCMD_DATA2__DATA2_MASK 0xffffffff 3154 + #define SDMA1_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0 3155 + #define SDMA1_RLC1_MIDCMD_DATA3__DATA3_MASK 0xffffffff 3156 + #define SDMA1_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0 3157 + #define SDMA1_RLC1_MIDCMD_DATA4__DATA4_MASK 0xffffffff 3158 + #define SDMA1_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0 3159 + #define SDMA1_RLC1_MIDCMD_DATA5__DATA5_MASK 0xffffffff 3160 + #define SDMA1_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0 3161 + #define SDMA1_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x1 3162 + #define SDMA1_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 3163 + #define SDMA1_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x2 3164 + #define SDMA1_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 3165 + #define SDMA1_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0xf0 3166 + #define SDMA1_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 3167 + #define SDMA1_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x100 3168 + #define SDMA1_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 3169 + #define HDP_HOST_PATH_CNTL__BIF_RDRET_CREDIT_MASK 0x7 3170 + #define HDP_HOST_PATH_CNTL__BIF_RDRET_CREDIT__SHIFT 0x0 3171 + #define HDP_HOST_PATH_CNTL__MC_WRREQ_CREDIT_MASK 0x1f8 3172 + #define HDP_HOST_PATH_CNTL__MC_WRREQ_CREDIT__SHIFT 0x3 3173 + #define HDP_HOST_PATH_CNTL__WR_STALL_TIMER_MASK 0x600 3174 + #define HDP_HOST_PATH_CNTL__WR_STALL_TIMER__SHIFT 0x9 3175 + #define HDP_HOST_PATH_CNTL__RD_STALL_TIMER_MASK 0x1800 3176 + #define HDP_HOST_PATH_CNTL__RD_STALL_TIMER__SHIFT 0xb 3177 + #define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER_MASK 0x180000 3178 + #define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER__SHIFT 0x13 3179 + #define HDP_HOST_PATH_CNTL__WRITE_COMBINE_EN_MASK 0x200000 3180 + #define HDP_HOST_PATH_CNTL__WRITE_COMBINE_EN__SHIFT 0x15 3181 + #define HDP_HOST_PATH_CNTL__CACHE_INVALIDATE_MASK 0x400000 3182 + #define HDP_HOST_PATH_CNTL__CACHE_INVALIDATE__SHIFT 0x16 3183 + #define HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK 0x800000 3184 + #define HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS__SHIFT 0x17 3185 + #define HDP_HOST_PATH_CNTL__REG_CLK_ENABLE_COUNT_MASK 0xf000000 3186 + #define HDP_HOST_PATH_CNTL__REG_CLK_ENABLE_COUNT__SHIFT 0x18 3187 + #define HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS_MASK 0x20000000 3188 + #define HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS__SHIFT 0x1d 3189 + #define HDP_HOST_PATH_CNTL__WRITE_THROUGH_CACHE_DIS_MASK 0x40000000 3190 + #define HDP_HOST_PATH_CNTL__WRITE_THROUGH_CACHE_DIS__SHIFT 0x1e 3191 + #define HDP_HOST_PATH_CNTL__LIN_RD_CACHE_DIS_MASK 0x80000000 3192 + #define HDP_HOST_PATH_CNTL__LIN_RD_CACHE_DIS__SHIFT 0x1f 3193 + #define HDP_NONSURFACE_BASE__NONSURF_BASE_MASK 0xffffffff 3194 + #define HDP_NONSURFACE_BASE__NONSURF_BASE__SHIFT 0x0 3195 + #define HDP_NONSURFACE_INFO__NONSURF_ADDR_TYPE_MASK 0x1 3196 + #define HDP_NONSURFACE_INFO__NONSURF_ADDR_TYPE__SHIFT 0x0 3197 + #define HDP_NONSURFACE_INFO__NONSURF_ARRAY_MODE_MASK 0x1e 3198 + #define HDP_NONSURFACE_INFO__NONSURF_ARRAY_MODE__SHIFT 0x1 3199 + #define HDP_NONSURFACE_INFO__NONSURF_ENDIAN_MASK 0x60 3200 + #define HDP_NONSURFACE_INFO__NONSURF_ENDIAN__SHIFT 0x5 3201 + #define HDP_NONSURFACE_INFO__NONSURF_PIXEL_SIZE_MASK 0x380 3202 + #define HDP_NONSURFACE_INFO__NONSURF_PIXEL_SIZE__SHIFT 0x7 3203 + #define HDP_NONSURFACE_INFO__NONSURF_SAMPLE_NUM_MASK 0x1c00 3204 + #define HDP_NONSURFACE_INFO__NONSURF_SAMPLE_NUM__SHIFT 0xa 3205 + #define HDP_NONSURFACE_INFO__NONSURF_SAMPLE_SIZE_MASK 0x6000 3206 + #define HDP_NONSURFACE_INFO__NONSURF_SAMPLE_SIZE__SHIFT 0xd 3207 + #define HDP_NONSURFACE_INFO__NONSURF_PRIV_MASK 0x8000 3208 + #define HDP_NONSURFACE_INFO__NONSURF_PRIV__SHIFT 0xf 3209 + #define HDP_NONSURFACE_INFO__NONSURF_TILE_COMPACT_MASK 0x10000 3210 + #define HDP_NONSURFACE_INFO__NONSURF_TILE_COMPACT__SHIFT 0x10 3211 + #define HDP_NONSURFACE_INFO__NONSURF_TILE_SPLIT_MASK 0xe0000 3212 + #define HDP_NONSURFACE_INFO__NONSURF_TILE_SPLIT__SHIFT 0x11 3213 + #define HDP_NONSURFACE_INFO__NONSURF_NUM_BANKS_MASK 0x300000 3214 + #define HDP_NONSURFACE_INFO__NONSURF_NUM_BANKS__SHIFT 0x14 3215 + #define HDP_NONSURFACE_INFO__NONSURF_BANK_WIDTH_MASK 0xc00000 3216 + #define HDP_NONSURFACE_INFO__NONSURF_BANK_WIDTH__SHIFT 0x16 3217 + #define HDP_NONSURFACE_INFO__NONSURF_BANK_HEIGHT_MASK 0x3000000 3218 + #define HDP_NONSURFACE_INFO__NONSURF_BANK_HEIGHT__SHIFT 0x18 3219 + #define HDP_NONSURFACE_INFO__NONSURF_MACRO_TILE_ASPECT_MASK 0xc000000 3220 + #define HDP_NONSURFACE_INFO__NONSURF_MACRO_TILE_ASPECT__SHIFT 0x1a 3221 + #define HDP_NONSURFACE_INFO__NONSURF_MICRO_TILE_MODE_MASK 0x70000000 3222 + #define HDP_NONSURFACE_INFO__NONSURF_MICRO_TILE_MODE__SHIFT 0x1c 3223 + #define HDP_NONSURFACE_INFO__NONSURF_SLICE_TILE_MAX_MSB_MASK 0x80000000 3224 + #define HDP_NONSURFACE_INFO__NONSURF_SLICE_TILE_MAX_MSB__SHIFT 0x1f 3225 + #define HDP_NONSURFACE_SIZE__NONSURF_PITCH_TILE_MAX_MASK 0x7ff 3226 + #define HDP_NONSURFACE_SIZE__NONSURF_PITCH_TILE_MAX__SHIFT 0x0 3227 + #define HDP_NONSURFACE_SIZE__NONSURF_SLICE_TILE_MAX_MASK 0xfffff800 3228 + #define HDP_NONSURFACE_SIZE__NONSURF_SLICE_TILE_MAX__SHIFT 0xb 3229 + #define HDP_NONSURF_FLAGS__NONSURF_WRITE_FLAG_MASK 0x1 3230 + #define HDP_NONSURF_FLAGS__NONSURF_WRITE_FLAG__SHIFT 0x0 3231 + #define HDP_NONSURF_FLAGS__NONSURF_READ_FLAG_MASK 0x2 3232 + #define HDP_NONSURF_FLAGS__NONSURF_READ_FLAG__SHIFT 0x1 3233 + #define HDP_NONSURF_FLAGS_CLR__NONSURF_WRITE_FLAG_CLR_MASK 0x1 3234 + #define HDP_NONSURF_FLAGS_CLR__NONSURF_WRITE_FLAG_CLR__SHIFT 0x0 3235 + #define HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR_MASK 0x2 3236 + #define HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR__SHIFT 0x1 3237 + #define HDP_SW_SEMAPHORE__SW_SEMAPHORE_MASK 0xffffffff 3238 + #define HDP_SW_SEMAPHORE__SW_SEMAPHORE__SHIFT 0x0 3239 + #define HDP_DEBUG0__HDP_DEBUG__SHIFT 0x0 3240 + #define HDP_DEBUG1__HDP_DEBUG__SHIFT 0x0 3241 + #define HDP_LAST_SURFACE_HIT__LAST_SURFACE_HIT_MASK 0x3f 3242 + #define HDP_LAST_SURFACE_HIT__LAST_SURFACE_HIT__SHIFT 0x0 3243 + #define HDP_TILING_CONFIG__PIPE_TILING_MASK 0xe 3244 + #define HDP_TILING_CONFIG__PIPE_TILING__SHIFT 0x1 3245 + #define HDP_TILING_CONFIG__BANK_TILING_MASK 0x30 3246 + #define HDP_TILING_CONFIG__BANK_TILING__SHIFT 0x4 3247 + #define HDP_TILING_CONFIG__GROUP_SIZE_MASK 0xc0 3248 + #define HDP_TILING_CONFIG__GROUP_SIZE__SHIFT 0x6 3249 + #define HDP_TILING_CONFIG__ROW_TILING_MASK 0x700 3250 + #define HDP_TILING_CONFIG__ROW_TILING__SHIFT 0x8 3251 + #define HDP_TILING_CONFIG__BANK_SWAPS_MASK 0x3800 3252 + #define HDP_TILING_CONFIG__BANK_SWAPS__SHIFT 0xb 3253 + #define HDP_TILING_CONFIG__SAMPLE_SPLIT_MASK 0xc000 3254 + #define HDP_TILING_CONFIG__SAMPLE_SPLIT__SHIFT 0xe 3255 + #define HDP_SC_MULTI_CHIP_CNTL__LOG2_NUM_CHIPS_MASK 0x7 3256 + #define HDP_SC_MULTI_CHIP_CNTL__LOG2_NUM_CHIPS__SHIFT 0x0 3257 + #define HDP_SC_MULTI_CHIP_CNTL__MULTI_CHIP_TILE_SIZE_MASK 0x18 3258 + #define HDP_SC_MULTI_CHIP_CNTL__MULTI_CHIP_TILE_SIZE__SHIFT 0x3 3259 + #define HDP_OUTSTANDING_REQ__WRITE_REQ_MASK 0xff 3260 + #define HDP_OUTSTANDING_REQ__WRITE_REQ__SHIFT 0x0 3261 + #define HDP_OUTSTANDING_REQ__READ_REQ_MASK 0xff00 3262 + #define HDP_OUTSTANDING_REQ__READ_REQ__SHIFT 0x8 3263 + #define HDP_ADDR_CONFIG__NUM_PIPES_MASK 0x7 3264 + #define HDP_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 3265 + #define HDP_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 3266 + #define HDP_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 3267 + #define HDP_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 3268 + #define HDP_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 3269 + #define HDP_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 3270 + #define HDP_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc 3271 + #define HDP_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 3272 + #define HDP_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 3273 + #define HDP_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 3274 + #define HDP_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 3275 + #define HDP_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 3276 + #define HDP_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 3277 + #define HDP_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 3278 + #define HDP_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c 3279 + #define HDP_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 3280 + #define HDP_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e 3281 + #define HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE_MASK 0x1 3282 + #define HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE__SHIFT 0x0 3283 + #define HDP_MISC_CNTL__VM_ID_MASK 0x1e 3284 + #define HDP_MISC_CNTL__VM_ID__SHIFT 0x1 3285 + #define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024_MASK 0x20 3286 + #define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024__SHIFT 0x5 3287 + #define HDP_MISC_CNTL__MULTIPLE_READS_MASK 0x40 3288 + #define HDP_MISC_CNTL__MULTIPLE_READS__SHIFT 0x6 3289 + #define HDP_MISC_CNTL__HDP_BIF_RDRET_CREDIT_MASK 0x780 3290 + #define HDP_MISC_CNTL__HDP_BIF_RDRET_CREDIT__SHIFT 0x7 3291 + #define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES_MASK 0x800 3292 + #define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES__SHIFT 0xb 3293 + #define HDP_MISC_CNTL__NO_SPLIT_ARRAY_LINEAR_MASK 0x1000 3294 + #define HDP_MISC_CNTL__NO_SPLIT_ARRAY_LINEAR__SHIFT 0xc 3295 + #define HDP_MISC_CNTL__MC_RDREQ_CREDIT_MASK 0x7e000 3296 + #define HDP_MISC_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd 3297 + #define HDP_MISC_CNTL__READ_CACHE_INVALIDATE_MASK 0x80000 3298 + #define HDP_MISC_CNTL__READ_CACHE_INVALIDATE__SHIFT 0x13 3299 + #define HDP_MISC_CNTL__ADDRLIB_LINEAR_BYPASS_MASK 0x100000 3300 + #define HDP_MISC_CNTL__ADDRLIB_LINEAR_BYPASS__SHIFT 0x14 3301 + #define HDP_MISC_CNTL__FED_ENABLE_MASK 0x200000 3302 + #define HDP_MISC_CNTL__FED_ENABLE__SHIFT 0x15 3303 + #define HDP_MISC_CNTL__LEGACY_TILING_ENABLE_MASK 0x400000 3304 + #define HDP_MISC_CNTL__LEGACY_TILING_ENABLE__SHIFT 0x16 3305 + #define HDP_MISC_CNTL__LEGACY_SURFACES_ENABLE_MASK 0x800000 3306 + #define HDP_MISC_CNTL__LEGACY_SURFACES_ENABLE__SHIFT 0x17 3307 + #define HDP_MEM_POWER_LS__LS_ENABLE_MASK 0x1 3308 + #define HDP_MEM_POWER_LS__LS_ENABLE__SHIFT 0x0 3309 + #define HDP_MEM_POWER_LS__LS_SETUP_MASK 0x7e 3310 + #define HDP_MEM_POWER_LS__LS_SETUP__SHIFT 0x1 3311 + #define HDP_MEM_POWER_LS__LS_HOLD_MASK 0x1f80 3312 + #define HDP_MEM_POWER_LS__LS_HOLD__SHIFT 0x7 3313 + #define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_PRI_MASK 0x7 3314 + #define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_PRI__SHIFT 0x0 3315 + #define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_DIR_MASK 0x38 3316 + #define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_DIR__SHIFT 0x3 3317 + #define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_NUM_MASK 0x1c0 3318 + #define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_NUM__SHIFT 0x6 3319 + #define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_MAX_Z_MASK 0xffe00 3320 + #define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_MAX_Z__SHIFT 0x9 3321 + #define HDP_NONSURFACE_PREFETCH__NONSURF_PIPE_CONFIG_MASK 0xf8000000 3322 + #define HDP_NONSURFACE_PREFETCH__NONSURF_PIPE_CONFIG__SHIFT 0x1b 3323 + #define HDP_MEMIO_CNTL__MEMIO_SEND_MASK 0x1 3324 + #define HDP_MEMIO_CNTL__MEMIO_SEND__SHIFT 0x0 3325 + #define HDP_MEMIO_CNTL__MEMIO_OP_MASK 0x2 3326 + #define HDP_MEMIO_CNTL__MEMIO_OP__SHIFT 0x1 3327 + #define HDP_MEMIO_CNTL__MEMIO_BE_MASK 0x3c 3328 + #define HDP_MEMIO_CNTL__MEMIO_BE__SHIFT 0x2 3329 + #define HDP_MEMIO_CNTL__MEMIO_WR_STROBE_MASK 0x40 3330 + #define HDP_MEMIO_CNTL__MEMIO_WR_STROBE__SHIFT 0x6 3331 + #define HDP_MEMIO_CNTL__MEMIO_RD_STROBE_MASK 0x80 3332 + #define HDP_MEMIO_CNTL__MEMIO_RD_STROBE__SHIFT 0x7 3333 + #define HDP_MEMIO_CNTL__MEMIO_ADDR_UPPER_MASK 0x3f00 3334 + #define HDP_MEMIO_CNTL__MEMIO_ADDR_UPPER__SHIFT 0x8 3335 + #define HDP_MEMIO_CNTL__MEMIO_CLR_WR_ERROR_MASK 0x4000 3336 + #define HDP_MEMIO_CNTL__MEMIO_CLR_WR_ERROR__SHIFT 0xe 3337 + #define HDP_MEMIO_CNTL__MEMIO_CLR_RD_ERROR_MASK 0x8000 3338 + #define HDP_MEMIO_CNTL__MEMIO_CLR_RD_ERROR__SHIFT 0xf 3339 + #define HDP_MEMIO_CNTL__MEMIO_VF_MASK 0x10000 3340 + #define HDP_MEMIO_CNTL__MEMIO_VF__SHIFT 0x10 3341 + #define HDP_MEMIO_CNTL__MEMIO_VFID_MASK 0x1e0000 3342 + #define HDP_MEMIO_CNTL__MEMIO_VFID__SHIFT 0x11 3343 + #define HDP_MEMIO_ADDR__MEMIO_ADDR_LOWER_MASK 0xffffffff 3344 + #define HDP_MEMIO_ADDR__MEMIO_ADDR_LOWER__SHIFT 0x0 3345 + #define HDP_MEMIO_STATUS__MEMIO_WR_STATUS_MASK 0x1 3346 + #define HDP_MEMIO_STATUS__MEMIO_WR_STATUS__SHIFT 0x0 3347 + #define HDP_MEMIO_STATUS__MEMIO_RD_STATUS_MASK 0x2 3348 + #define HDP_MEMIO_STATUS__MEMIO_RD_STATUS__SHIFT 0x1 3349 + #define HDP_MEMIO_STATUS__MEMIO_WR_ERROR_MASK 0x4 3350 + #define HDP_MEMIO_STATUS__MEMIO_WR_ERROR__SHIFT 0x2 3351 + #define HDP_MEMIO_STATUS__MEMIO_RD_ERROR_MASK 0x8 3352 + #define HDP_MEMIO_STATUS__MEMIO_RD_ERROR__SHIFT 0x3 3353 + #define HDP_MEMIO_WR_DATA__MEMIO_WR_DATA_MASK 0xffffffff 3354 + #define HDP_MEMIO_WR_DATA__MEMIO_WR_DATA__SHIFT 0x0 3355 + #define HDP_MEMIO_RD_DATA__MEMIO_RD_DATA_MASK 0xffffffff 3356 + #define HDP_MEMIO_RD_DATA__MEMIO_RD_DATA__SHIFT 0x0 3357 + #define HDP_VF_ENABLE__VF_EN_MASK 0x1 3358 + #define HDP_VF_ENABLE__VF_EN__SHIFT 0x0 3359 + #define HDP_VF_ENABLE__VF_NUM_MASK 0xffff0000 3360 + #define HDP_VF_ENABLE__VF_NUM__SHIFT 0x10 3361 + #define HDP_XDP_DIRECT2HDP_FIRST__RESERVED_MASK 0xffffffff 3362 + #define HDP_XDP_DIRECT2HDP_FIRST__RESERVED__SHIFT 0x0 3363 + #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_FLUSH_NUM_MASK 0xf 3364 + #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_FLUSH_NUM__SHIFT 0x0 3365 + #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ENC_DATA_MASK 0xf0 3366 + #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ENC_DATA__SHIFT 0x4 3367 + #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ADDR_SEL_MASK 0x700 3368 + #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ADDR_SEL__SHIFT 0x8 3369 + #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_XPB_CLG_MASK 0xf800 3370 + #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_XPB_CLG__SHIFT 0xb 3371 + #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_HOST_MASK 0x10000 3372 + #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_HOST__SHIFT 0x10 3373 + #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_SIDE_MASK 0x20000 3374 + #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_SIDE__SHIFT 0x11 3375 + #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_ALTER_FLUSH_NUM_MASK 0x40000 3376 + #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_ALTER_FLUSH_NUM__SHIFT 0x12 3377 + #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_0_MASK 0x80000 3378 + #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_0__SHIFT 0x13 3379 + #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1_MASK 0x100000 3380 + #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1__SHIFT 0x14 3381 + #define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_ADDR_MASK 0xffff 3382 + #define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_ADDR__SHIFT 0x0 3383 + #define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_FLUSH_NUM_MASK 0xf0000 3384 + #define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_FLUSH_NUM__SHIFT 0x10 3385 + #define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM_MASK 0x700000 3386 + #define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM__SHIFT 0x14 3387 + #define HDP_XDP_D2H_RSVD_3__RESERVED_MASK 0xffffffff 3388 + #define HDP_XDP_D2H_RSVD_3__RESERVED__SHIFT 0x0 3389 + #define HDP_XDP_D2H_RSVD_4__RESERVED_MASK 0xffffffff 3390 + #define HDP_XDP_D2H_RSVD_4__RESERVED__SHIFT 0x0 3391 + #define HDP_XDP_D2H_RSVD_5__RESERVED_MASK 0xffffffff 3392 + #define HDP_XDP_D2H_RSVD_5__RESERVED__SHIFT 0x0 3393 + #define HDP_XDP_D2H_RSVD_6__RESERVED_MASK 0xffffffff 3394 + #define HDP_XDP_D2H_RSVD_6__RESERVED__SHIFT 0x0 3395 + #define HDP_XDP_D2H_RSVD_7__RESERVED_MASK 0xffffffff 3396 + #define HDP_XDP_D2H_RSVD_7__RESERVED__SHIFT 0x0 3397 + #define HDP_XDP_D2H_RSVD_8__RESERVED_MASK 0xffffffff 3398 + #define HDP_XDP_D2H_RSVD_8__RESERVED__SHIFT 0x0 3399 + #define HDP_XDP_D2H_RSVD_9__RESERVED_MASK 0xffffffff 3400 + #define HDP_XDP_D2H_RSVD_9__RESERVED__SHIFT 0x0 3401 + #define HDP_XDP_D2H_RSVD_10__RESERVED_MASK 0xffffffff 3402 + #define HDP_XDP_D2H_RSVD_10__RESERVED__SHIFT 0x0 3403 + #define HDP_XDP_D2H_RSVD_11__RESERVED_MASK 0xffffffff 3404 + #define HDP_XDP_D2H_RSVD_11__RESERVED__SHIFT 0x0 3405 + #define HDP_XDP_D2H_RSVD_12__RESERVED_MASK 0xffffffff 3406 + #define HDP_XDP_D2H_RSVD_12__RESERVED__SHIFT 0x0 3407 + #define HDP_XDP_D2H_RSVD_13__RESERVED_MASK 0xffffffff 3408 + #define HDP_XDP_D2H_RSVD_13__RESERVED__SHIFT 0x0 3409 + #define HDP_XDP_D2H_RSVD_14__RESERVED_MASK 0xffffffff 3410 + #define HDP_XDP_D2H_RSVD_14__RESERVED__SHIFT 0x0 3411 + #define HDP_XDP_D2H_RSVD_15__RESERVED_MASK 0xffffffff 3412 + #define HDP_XDP_D2H_RSVD_15__RESERVED__SHIFT 0x0 3413 + #define HDP_XDP_D2H_RSVD_16__RESERVED_MASK 0xffffffff 3414 + #define HDP_XDP_D2H_RSVD_16__RESERVED__SHIFT 0x0 3415 + #define HDP_XDP_D2H_RSVD_17__RESERVED_MASK 0xffffffff 3416 + #define HDP_XDP_D2H_RSVD_17__RESERVED__SHIFT 0x0 3417 + #define HDP_XDP_D2H_RSVD_18__RESERVED_MASK 0xffffffff 3418 + #define HDP_XDP_D2H_RSVD_18__RESERVED__SHIFT 0x0 3419 + #define HDP_XDP_D2H_RSVD_19__RESERVED_MASK 0xffffffff 3420 + #define HDP_XDP_D2H_RSVD_19__RESERVED__SHIFT 0x0 3421 + #define HDP_XDP_D2H_RSVD_20__RESERVED_MASK 0xffffffff 3422 + #define HDP_XDP_D2H_RSVD_20__RESERVED__SHIFT 0x0 3423 + #define HDP_XDP_D2H_RSVD_21__RESERVED_MASK 0xffffffff 3424 + #define HDP_XDP_D2H_RSVD_21__RESERVED__SHIFT 0x0 3425 + #define HDP_XDP_D2H_RSVD_22__RESERVED_MASK 0xffffffff 3426 + #define HDP_XDP_D2H_RSVD_22__RESERVED__SHIFT 0x0 3427 + #define HDP_XDP_D2H_RSVD_23__RESERVED_MASK 0xffffffff 3428 + #define HDP_XDP_D2H_RSVD_23__RESERVED__SHIFT 0x0 3429 + #define HDP_XDP_D2H_RSVD_24__RESERVED_MASK 0xffffffff 3430 + #define HDP_XDP_D2H_RSVD_24__RESERVED__SHIFT 0x0 3431 + #define HDP_XDP_D2H_RSVD_25__RESERVED_MASK 0xffffffff 3432 + #define HDP_XDP_D2H_RSVD_25__RESERVED__SHIFT 0x0 3433 + #define HDP_XDP_D2H_RSVD_26__RESERVED_MASK 0xffffffff 3434 + #define HDP_XDP_D2H_RSVD_26__RESERVED__SHIFT 0x0 3435 + #define HDP_XDP_D2H_RSVD_27__RESERVED_MASK 0xffffffff 3436 + #define HDP_XDP_D2H_RSVD_27__RESERVED__SHIFT 0x0 3437 + #define HDP_XDP_D2H_RSVD_28__RESERVED_MASK 0xffffffff 3438 + #define HDP_XDP_D2H_RSVD_28__RESERVED__SHIFT 0x0 3439 + #define HDP_XDP_D2H_RSVD_29__RESERVED_MASK 0xffffffff 3440 + #define HDP_XDP_D2H_RSVD_29__RESERVED__SHIFT 0x0 3441 + #define HDP_XDP_D2H_RSVD_30__RESERVED_MASK 0xffffffff 3442 + #define HDP_XDP_D2H_RSVD_30__RESERVED__SHIFT 0x0 3443 + #define HDP_XDP_D2H_RSVD_31__RESERVED_MASK 0xffffffff 3444 + #define HDP_XDP_D2H_RSVD_31__RESERVED__SHIFT 0x0 3445 + #define HDP_XDP_D2H_RSVD_32__RESERVED_MASK 0xffffffff 3446 + #define HDP_XDP_D2H_RSVD_32__RESERVED__SHIFT 0x0 3447 + #define HDP_XDP_D2H_RSVD_33__RESERVED_MASK 0xffffffff 3448 + #define HDP_XDP_D2H_RSVD_33__RESERVED__SHIFT 0x0 3449 + #define HDP_XDP_D2H_RSVD_34__RESERVED_MASK 0xffffffff 3450 + #define HDP_XDP_D2H_RSVD_34__RESERVED__SHIFT 0x0 3451 + #define HDP_XDP_DIRECT2HDP_LAST__RESERVED_MASK 0xffffffff 3452 + #define HDP_XDP_DIRECT2HDP_LAST__RESERVED__SHIFT 0x0 3453 + #define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_ADDR_SIZE_MASK 0xf 3454 + #define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_ADDR_SIZE__SHIFT 0x0 3455 + #define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_BAR_FROM_MASK 0x30 3456 + #define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_BAR_FROM__SHIFT 0x4 3457 + #define HDP_XDP_P2P_MBX_OFFSET__P2P_MBX_OFFSET_MASK 0x3fff 3458 + #define HDP_XDP_P2P_MBX_OFFSET__P2P_MBX_OFFSET__SHIFT 0x0 3459 + #define HDP_XDP_P2P_MBX_ADDR0__VALID_MASK 0x1 3460 + #define HDP_XDP_P2P_MBX_ADDR0__VALID__SHIFT 0x0 3461 + #define HDP_XDP_P2P_MBX_ADDR0__ADDR_MASK 0x1ffffe 3462 + #define HDP_XDP_P2P_MBX_ADDR0__ADDR__SHIFT 0x1 3463 + #define HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36_MASK 0x1e00000 3464 + #define HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36__SHIFT 0x15 3465 + #define HDP_XDP_P2P_MBX_ADDR1__VALID_MASK 0x1 3466 + #define HDP_XDP_P2P_MBX_ADDR1__VALID__SHIFT 0x0 3467 + #define HDP_XDP_P2P_MBX_ADDR1__ADDR_MASK 0x1ffffe 3468 + #define HDP_XDP_P2P_MBX_ADDR1__ADDR__SHIFT 0x1 3469 + #define HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36_MASK 0x1e00000 3470 + #define HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36__SHIFT 0x15 3471 + #define HDP_XDP_P2P_MBX_ADDR2__VALID_MASK 0x1 3472 + #define HDP_XDP_P2P_MBX_ADDR2__VALID__SHIFT 0x0 3473 + #define HDP_XDP_P2P_MBX_ADDR2__ADDR_MASK 0x1ffffe 3474 + #define HDP_XDP_P2P_MBX_ADDR2__ADDR__SHIFT 0x1 3475 + #define HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36_MASK 0x1e00000 3476 + #define HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36__SHIFT 0x15 3477 + #define HDP_XDP_P2P_MBX_ADDR3__VALID_MASK 0x1 3478 + #define HDP_XDP_P2P_MBX_ADDR3__VALID__SHIFT 0x0 3479 + #define HDP_XDP_P2P_MBX_ADDR3__ADDR_MASK 0x1ffffe 3480 + #define HDP_XDP_P2P_MBX_ADDR3__ADDR__SHIFT 0x1 3481 + #define HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36_MASK 0x1e00000 3482 + #define HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36__SHIFT 0x15 3483 + #define HDP_XDP_P2P_MBX_ADDR4__VALID_MASK 0x1 3484 + #define HDP_XDP_P2P_MBX_ADDR4__VALID__SHIFT 0x0 3485 + #define HDP_XDP_P2P_MBX_ADDR4__ADDR_MASK 0x1ffffe 3486 + #define HDP_XDP_P2P_MBX_ADDR4__ADDR__SHIFT 0x1 3487 + #define HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36_MASK 0x1e00000 3488 + #define HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36__SHIFT 0x15 3489 + #define HDP_XDP_P2P_MBX_ADDR5__VALID_MASK 0x1 3490 + #define HDP_XDP_P2P_MBX_ADDR5__VALID__SHIFT 0x0 3491 + #define HDP_XDP_P2P_MBX_ADDR5__ADDR_MASK 0x1ffffe 3492 + #define HDP_XDP_P2P_MBX_ADDR5__ADDR__SHIFT 0x1 3493 + #define HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36_MASK 0x1e00000 3494 + #define HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36__SHIFT 0x15 3495 + #define HDP_XDP_P2P_MBX_ADDR6__VALID_MASK 0x1 3496 + #define HDP_XDP_P2P_MBX_ADDR6__VALID__SHIFT 0x0 3497 + #define HDP_XDP_P2P_MBX_ADDR6__ADDR_MASK 0x1ffffe 3498 + #define HDP_XDP_P2P_MBX_ADDR6__ADDR__SHIFT 0x1 3499 + #define HDP_XDP_P2P_MBX_ADDR6__ADDR_39_36_MASK 0x1e00000 3500 + #define HDP_XDP_P2P_MBX_ADDR6__ADDR_39_36__SHIFT 0x15 3501 + #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_PRIV_MASK 0x1 3502 + #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_PRIV__SHIFT 0x0 3503 + #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SWAP_MASK 0x6 3504 + #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SWAP__SHIFT 0x1 3505 + #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_TRAN_MASK 0x8 3506 + #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_TRAN__SHIFT 0x3 3507 + #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_VMID_MASK 0xf0 3508 + #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_VMID__SHIFT 0x4 3509 + #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_PRIV_MASK 0x1 3510 + #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_PRIV__SHIFT 0x0 3511 + #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_SWAP_MASK 0x6 3512 + #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_SWAP__SHIFT 0x1 3513 + #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_TRAN_MASK 0x8 3514 + #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_TRAN__SHIFT 0x3 3515 + #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_PRIV_MASK 0x10 3516 + #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_PRIV__SHIFT 0x4 3517 + #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_SWAP_MASK 0x60 3518 + #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_SWAP__SHIFT 0x5 3519 + #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_TRAN_MASK 0x80 3520 + #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_TRAN__SHIFT 0x7 3521 + #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XL8R_WRREQ_CRD_OVERRIDE_MASK 0x3f00 3522 + #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XL8R_WRREQ_CRD_OVERRIDE__SHIFT 0x8 3523 + #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XDP_HIGHER_PRI_THRESH_MASK 0xfc000 3524 + #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XDP_HIGHER_PRI_THRESH__SHIFT 0xe 3525 + #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_MC_STALL_ON_BUF_FULL_MASK_MASK 0x700000 3526 + #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_MC_STALL_ON_BUF_FULL_MASK__SHIFT 0x14 3527 + #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_VMID_MASK 0x7800000 3528 + #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_VMID__SHIFT 0x17 3529 + #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_VMID_MASK 0x78000000 3530 + #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_VMID__SHIFT 0x1b 3531 + #define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_EN_MASK 0x1 3532 + #define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_EN__SHIFT 0x0 3533 + #define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER_MASK 0x6 3534 + #define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER__SHIFT 0x1 3535 + #define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_EN_MASK 0x1 3536 + #define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_EN__SHIFT 0x0 3537 + #define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_TIMER_MASK 0x6 3538 + #define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_TIMER__SHIFT 0x1 3539 + #define HDP_XDP_SID_CFG__SID_CFG_FLNUM_MSB_SEL_MASK 0x18 3540 + #define HDP_XDP_SID_CFG__SID_CFG_FLNUM_MSB_SEL__SHIFT 0x3 3541 + #define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_SYS_FIFO_DEPTH_OVERRIDE_MASK 0x3f 3542 + #define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_SYS_FIFO_DEPTH_OVERRIDE__SHIFT 0x0 3543 + #define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_XDP_FIFO_DEPTH_OVERRIDE_MASK 0xfc0 3544 + #define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_XDP_FIFO_DEPTH_OVERRIDE__SHIFT 0x6 3545 + #define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING_MASK 0x1000 3546 + #define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING__SHIFT 0xc 3547 + #define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_P2P_RD_EN_MASK 0x2000 3548 + #define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_P2P_RD_EN__SHIFT 0xd 3549 + #define HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_ENABLE_COUNT_MASK 0x3f 3550 + #define HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_ENABLE_COUNT__SHIFT 0x0 3551 + #define HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_GATING_DIS_MASK 0x40 3552 + #define HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_GATING_DIS__SHIFT 0x6 3553 + #define HDP_XDP_SRBM_CFG__SRBM_CFG_WAKE_DYN_CLK_MASK 0x80 3554 + #define HDP_XDP_SRBM_CFG__SRBM_CFG_WAKE_DYN_CLK__SHIFT 0x7 3555 + #define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_0_ON_DELAY_MASK 0xf 3556 + #define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_0_ON_DELAY__SHIFT 0x0 3557 + #define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_1_OFF_DELAY_MASK 0xff0 3558 + #define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_1_OFF_DELAY__SHIFT 0x4 3559 + #define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_2_RSVD_MASK 0x3ffff000 3560 + #define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_2_RSVD__SHIFT 0xc 3561 + #define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_3_SOFT_CORE_OVERRIDE_MASK 0x40000000 3562 + #define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_3_SOFT_CORE_OVERRIDE__SHIFT 0x1e 3563 + #define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_4_SOFT_REG_OVERRIDE_MASK 0x80000000 3564 + #define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_4_SOFT_REG_OVERRIDE__SHIFT 0x1f 3565 + #define HDP_XDP_P2P_BAR0__ADDR_MASK 0xffff 3566 + #define HDP_XDP_P2P_BAR0__ADDR__SHIFT 0x0 3567 + #define HDP_XDP_P2P_BAR0__FLUSH_MASK 0xf0000 3568 + #define HDP_XDP_P2P_BAR0__FLUSH__SHIFT 0x10 3569 + #define HDP_XDP_P2P_BAR0__VALID_MASK 0x100000 3570 + #define HDP_XDP_P2P_BAR0__VALID__SHIFT 0x14 3571 + #define HDP_XDP_P2P_BAR1__ADDR_MASK 0xffff 3572 + #define HDP_XDP_P2P_BAR1__ADDR__SHIFT 0x0 3573 + #define HDP_XDP_P2P_BAR1__FLUSH_MASK 0xf0000 3574 + #define HDP_XDP_P2P_BAR1__FLUSH__SHIFT 0x10 3575 + #define HDP_XDP_P2P_BAR1__VALID_MASK 0x100000 3576 + #define HDP_XDP_P2P_BAR1__VALID__SHIFT 0x14 3577 + #define HDP_XDP_P2P_BAR2__ADDR_MASK 0xffff 3578 + #define HDP_XDP_P2P_BAR2__ADDR__SHIFT 0x0 3579 + #define HDP_XDP_P2P_BAR2__FLUSH_MASK 0xf0000 3580 + #define HDP_XDP_P2P_BAR2__FLUSH__SHIFT 0x10 3581 + #define HDP_XDP_P2P_BAR2__VALID_MASK 0x100000 3582 + #define HDP_XDP_P2P_BAR2__VALID__SHIFT 0x14 3583 + #define HDP_XDP_P2P_BAR3__ADDR_MASK 0xffff 3584 + #define HDP_XDP_P2P_BAR3__ADDR__SHIFT 0x0 3585 + #define HDP_XDP_P2P_BAR3__FLUSH_MASK 0xf0000 3586 + #define HDP_XDP_P2P_BAR3__FLUSH__SHIFT 0x10 3587 + #define HDP_XDP_P2P_BAR3__VALID_MASK 0x100000 3588 + #define HDP_XDP_P2P_BAR3__VALID__SHIFT 0x14 3589 + #define HDP_XDP_P2P_BAR4__ADDR_MASK 0xffff 3590 + #define HDP_XDP_P2P_BAR4__ADDR__SHIFT 0x0 3591 + #define HDP_XDP_P2P_BAR4__FLUSH_MASK 0xf0000 3592 + #define HDP_XDP_P2P_BAR4__FLUSH__SHIFT 0x10 3593 + #define HDP_XDP_P2P_BAR4__VALID_MASK 0x100000 3594 + #define HDP_XDP_P2P_BAR4__VALID__SHIFT 0x14 3595 + #define HDP_XDP_P2P_BAR5__ADDR_MASK 0xffff 3596 + #define HDP_XDP_P2P_BAR5__ADDR__SHIFT 0x0 3597 + #define HDP_XDP_P2P_BAR5__FLUSH_MASK 0xf0000 3598 + #define HDP_XDP_P2P_BAR5__FLUSH__SHIFT 0x10 3599 + #define HDP_XDP_P2P_BAR5__VALID_MASK 0x100000 3600 + #define HDP_XDP_P2P_BAR5__VALID__SHIFT 0x14 3601 + #define HDP_XDP_P2P_BAR6__ADDR_MASK 0xffff 3602 + #define HDP_XDP_P2P_BAR6__ADDR__SHIFT 0x0 3603 + #define HDP_XDP_P2P_BAR6__FLUSH_MASK 0xf0000 3604 + #define HDP_XDP_P2P_BAR6__FLUSH__SHIFT 0x10 3605 + #define HDP_XDP_P2P_BAR6__VALID_MASK 0x100000 3606 + #define HDP_XDP_P2P_BAR6__VALID__SHIFT 0x14 3607 + #define HDP_XDP_P2P_BAR7__ADDR_MASK 0xffff 3608 + #define HDP_XDP_P2P_BAR7__ADDR__SHIFT 0x0 3609 + #define HDP_XDP_P2P_BAR7__FLUSH_MASK 0xf0000 3610 + #define HDP_XDP_P2P_BAR7__FLUSH__SHIFT 0x10 3611 + #define HDP_XDP_P2P_BAR7__VALID_MASK 0x100000 3612 + #define HDP_XDP_P2P_BAR7__VALID__SHIFT 0x14 3613 + #define HDP_XDP_FLUSH_ARMED_STS__FLUSH_ARMED_STS_MASK 0xffffffff 3614 + #define HDP_XDP_FLUSH_ARMED_STS__FLUSH_ARMED_STS__SHIFT 0x0 3615 + #define HDP_XDP_FLUSH_CNTR0_STS__FLUSH_CNTR0_STS_MASK 0x3ffffff 3616 + #define HDP_XDP_FLUSH_CNTR0_STS__FLUSH_CNTR0_STS__SHIFT 0x0 3617 + #define HDP_XDP_BUSY_STS__BUSY_BITS_MASK 0x3ffff 3618 + #define HDP_XDP_BUSY_STS__BUSY_BITS__SHIFT 0x0 3619 + #define HDP_XDP_STICKY__STICKY_STS_MASK 0xffff 3620 + #define HDP_XDP_STICKY__STICKY_STS__SHIFT 0x0 3621 + #define HDP_XDP_STICKY__STICKY_W1C_MASK 0xffff0000 3622 + #define HDP_XDP_STICKY__STICKY_W1C__SHIFT 0x10 3623 + #define HDP_XDP_CHKN__CHKN_0_RSVD_MASK 0xff 3624 + #define HDP_XDP_CHKN__CHKN_0_RSVD__SHIFT 0x0 3625 + #define HDP_XDP_CHKN__CHKN_1_RSVD_MASK 0xff00 3626 + #define HDP_XDP_CHKN__CHKN_1_RSVD__SHIFT 0x8 3627 + #define HDP_XDP_CHKN__CHKN_2_RSVD_MASK 0xff0000 3628 + #define HDP_XDP_CHKN__CHKN_2_RSVD__SHIFT 0x10 3629 + #define HDP_XDP_CHKN__CHKN_3_RSVD_MASK 0xff000000 3630 + #define HDP_XDP_CHKN__CHKN_3_RSVD__SHIFT 0x18 3631 + #define HDP_XDP_DBG_ADDR__STS_MASK 0xffff 3632 + #define HDP_XDP_DBG_ADDR__STS__SHIFT 0x0 3633 + #define HDP_XDP_DBG_ADDR__CTRL_MASK 0xffff0000 3634 + #define HDP_XDP_DBG_ADDR__CTRL__SHIFT 0x10 3635 + #define HDP_XDP_DBG_DATA__STS_MASK 0xffff 3636 + #define HDP_XDP_DBG_DATA__STS__SHIFT 0x0 3637 + #define HDP_XDP_DBG_DATA__CTRL_MASK 0xffff0000 3638 + #define HDP_XDP_DBG_DATA__CTRL__SHIFT 0x10 3639 + #define HDP_XDP_DBG_MASK__STS_MASK 0xffff 3640 + #define HDP_XDP_DBG_MASK__STS__SHIFT 0x0 3641 + #define HDP_XDP_DBG_MASK__CTRL_MASK 0xffff0000 3642 + #define HDP_XDP_DBG_MASK__CTRL__SHIFT 0x10 3643 + #define HDP_XDP_BARS_ADDR_39_36__BAR0_ADDR_39_36_MASK 0xf 3644 + #define HDP_XDP_BARS_ADDR_39_36__BAR0_ADDR_39_36__SHIFT 0x0 3645 + #define HDP_XDP_BARS_ADDR_39_36__BAR1_ADDR_39_36_MASK 0xf0 3646 + #define HDP_XDP_BARS_ADDR_39_36__BAR1_ADDR_39_36__SHIFT 0x4 3647 + #define HDP_XDP_BARS_ADDR_39_36__BAR2_ADDR_39_36_MASK 0xf00 3648 + #define HDP_XDP_BARS_ADDR_39_36__BAR2_ADDR_39_36__SHIFT 0x8 3649 + #define HDP_XDP_BARS_ADDR_39_36__BAR3_ADDR_39_36_MASK 0xf000 3650 + #define HDP_XDP_BARS_ADDR_39_36__BAR3_ADDR_39_36__SHIFT 0xc 3651 + #define HDP_XDP_BARS_ADDR_39_36__BAR4_ADDR_39_36_MASK 0xf0000 3652 + #define HDP_XDP_BARS_ADDR_39_36__BAR4_ADDR_39_36__SHIFT 0x10 3653 + #define HDP_XDP_BARS_ADDR_39_36__BAR5_ADDR_39_36_MASK 0xf00000 3654 + #define HDP_XDP_BARS_ADDR_39_36__BAR5_ADDR_39_36__SHIFT 0x14 3655 + #define HDP_XDP_BARS_ADDR_39_36__BAR6_ADDR_39_36_MASK 0xf000000 3656 + #define HDP_XDP_BARS_ADDR_39_36__BAR6_ADDR_39_36__SHIFT 0x18 3657 + #define HDP_XDP_BARS_ADDR_39_36__BAR7_ADDR_39_36_MASK 0xf0000000 3658 + #define HDP_XDP_BARS_ADDR_39_36__BAR7_ADDR_39_36__SHIFT 0x1c 3659 + 3660 + #endif /* OSS_3_0_SH_MASK_H */