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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
pinctrl: samsung: Add Exynos9810 SoC specific data
Add Samsung Exynos9810 SoC specific data to enable pinctrl
support for platforms based on Exynos9810.
Co-developed-by: Maksym Holovach <nergzd@nergzd723.xyz>
Signed-off-by: Maksym Holovach <nergzd@nergzd723.xyz>
Signed-off-by: Markuss Broks <markuss.broks@gmail.com>
Link: https://lore.kernel.org/r/20241026-exynos9810-v3-8-b89de9441ea8@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
authored by
Markuss Broks
and committed by
Krzysztof Kozlowski
6d2dbd4c
e830431e
+157
+154
drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
+154
drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
···
767
767
.num_ctrl = ARRAY_SIZE(exynos990_pin_ctrl),
768
768
};
769
769
770
+
/* pin banks of exynos9810 pin-controller 0 (ALIVE) */
771
+
static const struct samsung_pin_bank_data exynos9810_pin_banks0[] __initconst = {
772
+
EXYNOS850_PIN_BANK_EINTN(6, 0x000, "etc1"),
773
+
EXYNOS850_PIN_BANK_EINTW(8, 0x020, "gpa0", 0x00),
774
+
EXYNOS850_PIN_BANK_EINTW(8, 0x040, "gpa1", 0x04),
775
+
EXYNOS850_PIN_BANK_EINTW(8, 0x060, "gpa2", 0x08),
776
+
EXYNOS850_PIN_BANK_EINTW(8, 0x080, "gpa3", 0x0c),
777
+
EXYNOS850_PIN_BANK_EINTN(6, 0x0A0, "gpq0"),
778
+
EXYNOS850_PIN_BANK_EINTW(2, 0x0C0, "gpa4", 0x10),
779
+
};
780
+
781
+
/* pin banks of exynos9810 pin-controller 1 (AUD) */
782
+
static const struct samsung_pin_bank_data exynos9810_pin_banks1[] __initconst = {
783
+
EXYNOS850_PIN_BANK_EINTG(5, 0x000, "gpb0", 0x00),
784
+
EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpb1", 0x04),
785
+
EXYNOS850_PIN_BANK_EINTG(4, 0x040, "gpb2", 0x08),
786
+
};
787
+
788
+
/* pin banks of exynos9810 pin-controller 2 (CHUB) */
789
+
static const struct samsung_pin_bank_data exynos9810_pin_banks2[] __initconst = {
790
+
EXYNOS850_PIN_BANK_EINTG(8, 0x000, "gph0", 0x00),
791
+
EXYNOS850_PIN_BANK_EINTG(5, 0x020, "gph1", 0x04),
792
+
};
793
+
794
+
/* pin banks of exynos9810 pin-controller 3 (CMGP) */
795
+
static const struct samsung_pin_bank_data exynos9810_pin_banks3[] __initconst = {
796
+
EXYNOS850_PIN_BANK_EINTW(1, 0x000, "gpm0", 0x00),
797
+
EXYNOS850_PIN_BANK_EINTW(1, 0x020, "gpm1", 0x04),
798
+
EXYNOS850_PIN_BANK_EINTW(1, 0x040, "gpm2", 0x08),
799
+
EXYNOS850_PIN_BANK_EINTW(1, 0x060, "gpm3", 0x0C),
800
+
EXYNOS850_PIN_BANK_EINTW(1, 0x080, "gpm4", 0x10),
801
+
EXYNOS850_PIN_BANK_EINTW(1, 0x0A0, "gpm5", 0x14),
802
+
EXYNOS850_PIN_BANK_EINTW(1, 0x0C0, "gpm6", 0x18),
803
+
EXYNOS850_PIN_BANK_EINTW(1, 0x0E0, "gpm7", 0x1C),
804
+
EXYNOS850_PIN_BANK_EINTW(1, 0x100, "gpm10", 0x20),
805
+
EXYNOS850_PIN_BANK_EINTW(1, 0x120, "gpm11", 0x24),
806
+
EXYNOS850_PIN_BANK_EINTW(1, 0x140, "gpm12", 0x28),
807
+
EXYNOS850_PIN_BANK_EINTW(1, 0x160, "gpm13", 0x2C),
808
+
EXYNOS850_PIN_BANK_EINTW(1, 0x180, "gpm14", 0x30),
809
+
EXYNOS850_PIN_BANK_EINTW(1, 0x1A0, "gpm15", 0x34),
810
+
EXYNOS850_PIN_BANK_EINTW(1, 0x1C0, "gpm16", 0x38),
811
+
EXYNOS850_PIN_BANK_EINTW(1, 0x1E0, "gpm17", 0x3C),
812
+
EXYNOS850_PIN_BANK_EINTW(1, 0x200, "gpm40", 0x40),
813
+
EXYNOS850_PIN_BANK_EINTW(1, 0x220, "gpm41", 0x44),
814
+
EXYNOS850_PIN_BANK_EINTW(1, 0x240, "gpm42", 0x48),
815
+
EXYNOS850_PIN_BANK_EINTW(1, 0x260, "gpm43", 0x4C),
816
+
};
817
+
818
+
/* pin banks of exynos9810 pin-controller 4 (FSYS0) */
819
+
static const struct samsung_pin_bank_data exynos9810_pin_banks4[] __initconst = {
820
+
EXYNOS850_PIN_BANK_EINTG(2, 0x000, "gpf0", 0x00),
821
+
};
822
+
823
+
/* pin banks of exynos9810 pin-controller 5 (FSYS1) */
824
+
static const struct samsung_pin_bank_data exynos9810_pin_banks5[] __initconst = {
825
+
EXYNOS850_PIN_BANK_EINTG(7, 0x000, "gpf1", 0x00),
826
+
EXYNOS850_PIN_BANK_EINTG(6, 0x020, "gpf2", 0x04),
827
+
};
828
+
829
+
/* pin banks of exynos9810 pin-controller 6 (PERIC0) */
830
+
static const struct samsung_pin_bank_data exynos9810_pin_banks6[] __initconst = {
831
+
EXYNOS850_PIN_BANK_EINTG(8, 0x000, "gpp0", 0x00),
832
+
EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpp1", 0x04),
833
+
EXYNOS850_PIN_BANK_EINTG(8, 0x040, "gpp2", 0x08),
834
+
EXYNOS850_PIN_BANK_EINTG(4, 0x060, "gpp3", 0x0C),
835
+
EXYNOS850_PIN_BANK_EINTG(8, 0x080, "gpg0", 0x10),
836
+
EXYNOS850_PIN_BANK_EINTG(8, 0x0A0, "gpg1", 0x14),
837
+
EXYNOS850_PIN_BANK_EINTG(8, 0x0C0, "gpg2", 0x18),
838
+
};
839
+
840
+
/* pin banks of exynos9810 pin-controller 7 (PERIC1) */
841
+
static const struct samsung_pin_bank_data exynos9810_pin_banks7[] __initconst = {
842
+
EXYNOS850_PIN_BANK_EINTG(8, 0x000, "gpp4", 0x00),
843
+
EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpp5", 0x04),
844
+
EXYNOS850_PIN_BANK_EINTG(4, 0x040, "gpp6", 0x08),
845
+
EXYNOS850_PIN_BANK_EINTG(8, 0x060, "gpc0", 0x0C),
846
+
EXYNOS850_PIN_BANK_EINTG(8, 0x080, "gpc1", 0x10),
847
+
EXYNOS850_PIN_BANK_EINTG(4, 0x0A0, "gpd0", 0x14),
848
+
EXYNOS850_PIN_BANK_EINTG(7, 0x0C0, "gpg3", 0x18),
849
+
};
850
+
851
+
/* pin banks of exynos9810 pin-controller 8 (VTS) */
852
+
static const struct samsung_pin_bank_data exynos9810_pin_banks8[] __initconst = {
853
+
EXYNOS850_PIN_BANK_EINTG(3, 0x000, "gpt0", 0x00),
854
+
};
855
+
856
+
static const struct samsung_pin_ctrl exynos9810_pin_ctrl[] __initconst = {
857
+
{
858
+
/* pin-controller instance 0 ALIVE data */
859
+
.pin_banks = exynos9810_pin_banks0,
860
+
.nr_banks = ARRAY_SIZE(exynos9810_pin_banks0),
861
+
.eint_wkup_init = exynos_eint_wkup_init,
862
+
.eint_gpio_init = exynos_eint_gpio_init,
863
+
.suspend = exynos_pinctrl_suspend,
864
+
.resume = exynos_pinctrl_resume,
865
+
}, {
866
+
/* pin-controller instance 1 AUD data */
867
+
.pin_banks = exynos9810_pin_banks1,
868
+
.nr_banks = ARRAY_SIZE(exynos9810_pin_banks1),
869
+
}, {
870
+
/* pin-controller instance 2 CHUB data */
871
+
.pin_banks = exynos9810_pin_banks2,
872
+
.nr_banks = ARRAY_SIZE(exynos9810_pin_banks2),
873
+
.eint_gpio_init = exynos_eint_gpio_init,
874
+
.suspend = exynos_pinctrl_suspend,
875
+
.resume = exynos_pinctrl_resume,
876
+
}, {
877
+
/* pin-controller instance 3 CMGP data */
878
+
.pin_banks = exynos9810_pin_banks3,
879
+
.nr_banks = ARRAY_SIZE(exynos9810_pin_banks3),
880
+
.eint_wkup_init = exynos_eint_wkup_init,
881
+
.eint_gpio_init = exynos_eint_gpio_init,
882
+
.suspend = exynos_pinctrl_suspend,
883
+
.resume = exynos_pinctrl_resume,
884
+
}, {
885
+
/* pin-controller instance 4 FSYS0 data */
886
+
.pin_banks = exynos9810_pin_banks4,
887
+
.nr_banks = ARRAY_SIZE(exynos9810_pin_banks4),
888
+
.eint_gpio_init = exynos_eint_gpio_init,
889
+
.suspend = exynos_pinctrl_suspend,
890
+
.resume = exynos_pinctrl_resume,
891
+
}, {
892
+
/* pin-controller instance 5 FSYS1 data */
893
+
.pin_banks = exynos9810_pin_banks5,
894
+
.nr_banks = ARRAY_SIZE(exynos9810_pin_banks5),
895
+
.eint_gpio_init = exynos_eint_gpio_init,
896
+
.suspend = exynos_pinctrl_suspend,
897
+
.resume = exynos_pinctrl_resume,
898
+
}, {
899
+
/* pin-controller instance 6 PERIC0 data */
900
+
.pin_banks = exynos9810_pin_banks6,
901
+
.nr_banks = ARRAY_SIZE(exynos9810_pin_banks6),
902
+
.eint_gpio_init = exynos_eint_gpio_init,
903
+
.suspend = exynos_pinctrl_suspend,
904
+
.resume = exynos_pinctrl_resume,
905
+
}, {
906
+
/* pin-controller instance 7 PERIC1 data */
907
+
.pin_banks = exynos9810_pin_banks7,
908
+
.nr_banks = ARRAY_SIZE(exynos9810_pin_banks7),
909
+
.eint_gpio_init = exynos_eint_gpio_init,
910
+
.suspend = exynos_pinctrl_suspend,
911
+
.resume = exynos_pinctrl_resume,
912
+
}, {
913
+
/* pin-controller instance 8 VTS data */
914
+
.pin_banks = exynos9810_pin_banks8,
915
+
.nr_banks = ARRAY_SIZE(exynos9810_pin_banks8),
916
+
},
917
+
};
918
+
919
+
const struct samsung_pinctrl_of_match_data exynos9810_of_data __initconst = {
920
+
.ctrl = exynos9810_pin_ctrl,
921
+
.num_ctrl = ARRAY_SIZE(exynos9810_pin_ctrl),
922
+
};
923
+
770
924
/* pin banks of exynosautov9 pin-controller 0 (ALIVE) */
771
925
static const struct samsung_pin_bank_data exynosautov9_pin_banks0[] __initconst = {
772
926
EXYNOS850_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00),
+2
drivers/pinctrl/samsung/pinctrl-samsung.c
+2
drivers/pinctrl/samsung/pinctrl-samsung.c
···
1479
1479
.data = &exynos850_of_data },
1480
1480
{ .compatible = "samsung,exynos8895-pinctrl",
1481
1481
.data = &exynos8895_of_data },
1482
+
{ .compatible = "samsung,exynos9810-pinctrl",
1483
+
.data = &exynos9810_of_data },
1482
1484
{ .compatible = "samsung,exynos990-pinctrl",
1483
1485
.data = &exynos990_of_data },
1484
1486
{ .compatible = "samsung,exynosautov9-pinctrl",
+1
drivers/pinctrl/samsung/pinctrl-samsung.h
+1
drivers/pinctrl/samsung/pinctrl-samsung.h
···
385
385
extern const struct samsung_pinctrl_of_match_data exynos7885_of_data;
386
386
extern const struct samsung_pinctrl_of_match_data exynos850_of_data;
387
387
extern const struct samsung_pinctrl_of_match_data exynos8895_of_data;
388
+
extern const struct samsung_pinctrl_of_match_data exynos9810_of_data;
388
389
extern const struct samsung_pinctrl_of_match_data exynos990_of_data;
389
390
extern const struct samsung_pinctrl_of_match_data exynosautov9_of_data;
390
391
extern const struct samsung_pinctrl_of_match_data exynosautov920_of_data;