tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
sh: Add SH7203 CPU support.
This adds support for the SH7203 (SH-2A) CPU.
Signed-off-by: Kieran Bingham <kbingham@mpc-data.co.uk>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
+399
-15
+6
-2
arch/sh/Kconfig
+6
-2
arch/sh/Kconfig
···
158
158
159
159
# SH-2A Processor Support
160
160
161
+
config CPU_SUBTYPE_SH7203
162
+
bool "Support SH7203 processor"
163
+
select CPU_SH2A
164
+
161
165
config CPU_SUBTYPE_SH7206
162
166
bool "Support SH7206 processor"
163
167
select CPU_SH2A
···
560
556
default "32000000" if CPU_SUBTYPE_SH7722
561
557
default "33333333" if CPU_SUBTYPE_SH7770 || \
562
558
CPU_SUBTYPE_SH7760 || CPU_SUBTYPE_SH7705 || \
563
-
CPU_SUBTYPE_SH7206
559
+
CPU_SUBTYPE_SH7203 || CPU_SUBTYPE_SH7206
564
560
default "60000000" if CPU_SUBTYPE_SH7751 || CPU_SUBTYPE_SH7751R
565
561
default "66000000" if CPU_SUBTYPE_SH4_202
566
562
default "50000000"
···
571
567
572
568
config SH_CLK_MD
573
569
int "CPU Mode Pin Setting"
574
-
depends on CPU_SUBTYPE_SH7619 || CPU_SUBTYPE_SH7206
570
+
depends on CPU_SH2
575
571
default 6 if CPU_SUBTYPE_SH7206
576
572
default 5 if CPU_SUBTYPE_SH7619
577
573
default 0
+1
arch/sh/Kconfig.debug
+1
arch/sh/Kconfig.debug
···
32
32
depends on EARLY_SCIF_CONSOLE
33
33
default "0xffe00000" if CPU_SUBTYPE_SH7780
34
34
default "0xffea0000" if CPU_SUBTYPE_SH7785
35
+
default "0xfffe8000" if CPU_SUBTYPE_SH7203
35
36
default "0xfffe9800" if CPU_SUBTYPE_SH7206
36
37
default "0xf8420000" if CPU_SUBTYPE_SH7619
37
38
default "0xa4400000" if CPU_SUBTYPE_SH7712 || CPU_SUBTYPE_SH7705
+1
arch/sh/kernel/cpu/sh2a/Makefile
+1
arch/sh/kernel/cpu/sh2a/Makefile
+89
arch/sh/kernel/cpu/sh2a/clock-sh7203.c
+89
arch/sh/kernel/cpu/sh2a/clock-sh7203.c
···
1
+
/*
2
+
* arch/sh/kernel/cpu/sh2a/clock-sh7203.c
3
+
*
4
+
* SH7203 support for the clock framework
5
+
*
6
+
* Copyright (C) 2007 Kieran Bingham (MPC-Data Ltd)
7
+
*
8
+
* Based on clock-sh7263.c
9
+
* Copyright (C) 2006 Yoshinori Sato
10
+
*
11
+
* Based on clock-sh4.c
12
+
* Copyright (C) 2005 Paul Mundt
13
+
*
14
+
* This file is subject to the terms and conditions of the GNU General Public
15
+
* License. See the file "COPYING" in the main directory of this archive
16
+
* for more details.
17
+
*/
18
+
#include <linux/init.h>
19
+
#include <linux/kernel.h>
20
+
#include <asm/clock.h>
21
+
#include <asm/freq.h>
22
+
#include <asm/io.h>
23
+
24
+
const static int pll1rate[]={8,12,16,0};
25
+
const static int pfc_divisors[]={1,2,3,4,6,8,12};
26
+
#define ifc_divisors pfc_divisors
27
+
28
+
#if (CONFIG_SH_CLK_MD == 0)
29
+
#define PLL2 (1)
30
+
#elif (CONFIG_SH_CLK_MD == 1)
31
+
#define PLL2 (2)
32
+
#elif (CONFIG_SH_CLK_MD == 2)
33
+
#define PLL2 (4)
34
+
#elif (CONFIG_SH_CLK_MD == 3)
35
+
#define PLL2 (4)
36
+
#else
37
+
#error "Illegal Clock Mode!"
38
+
#endif
39
+
40
+
static void master_clk_init(struct clk *clk)
41
+
{
42
+
clk->rate *= pll1rate[(ctrl_inw(FREQCR) >> 8) & 0x0003] * PLL2 ;
43
+
}
44
+
45
+
static struct clk_ops sh7203_master_clk_ops = {
46
+
.init = master_clk_init,
47
+
};
48
+
49
+
static void module_clk_recalc(struct clk *clk)
50
+
{
51
+
int idx = (ctrl_inw(FREQCR) & 0x0007);
52
+
clk->rate = clk->parent->rate / pfc_divisors[idx];
53
+
}
54
+
55
+
static struct clk_ops sh7203_module_clk_ops = {
56
+
.recalc = module_clk_recalc,
57
+
};
58
+
59
+
static void bus_clk_recalc(struct clk *clk)
60
+
{
61
+
int idx = (ctrl_inw(FREQCR) & 0x0007);
62
+
clk->rate = clk->parent->rate / pfc_divisors[idx-2];
63
+
}
64
+
65
+
static struct clk_ops sh7203_bus_clk_ops = {
66
+
.recalc = bus_clk_recalc,
67
+
};
68
+
69
+
static void cpu_clk_recalc(struct clk *clk)
70
+
{
71
+
clk->rate = clk->parent->rate;
72
+
}
73
+
74
+
static struct clk_ops sh7203_cpu_clk_ops = {
75
+
.recalc = cpu_clk_recalc,
76
+
};
77
+
78
+
static struct clk_ops *sh7203_clk_ops[] = {
79
+
&sh7203_master_clk_ops,
80
+
&sh7203_module_clk_ops,
81
+
&sh7203_bus_clk_ops,
82
+
&sh7203_cpu_clk_ops,
83
+
};
84
+
85
+
void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
86
+
{
87
+
if (idx < ARRAY_SIZE(sh7203_clk_ops))
88
+
*ops = sh7203_clk_ops[idx];
89
+
}
+13
-6
arch/sh/kernel/cpu/sh2a/probe.c
+13
-6
arch/sh/kernel/cpu/sh2a/probe.c
···
3
3
*
4
4
* CPU Subtype Probing for SH-2A.
5
5
*
6
-
* Copyright (C) 2004, 2005 Paul Mundt
6
+
* Copyright (C) 2004 - 2007 Paul Mundt
7
7
*
8
8
* This file is subject to the terms and conditions of the GNU General Public
9
9
* License. See the file "COPYING" in the main directory of this archive
10
10
* for more details.
11
11
*/
12
-
13
12
#include <linux/init.h>
14
13
#include <asm/processor.h>
15
14
#include <asm/cache.h>
16
15
17
16
int __init detect_cpu_and_cache_system(void)
18
17
{
19
-
/* Just SH7206 for now .. */
20
-
boot_cpu_data.type = CPU_SH7206;
18
+
/* All SH-2A CPUs have support for 16 and 32-bit opcodes.. */
21
19
boot_cpu_data.flags |= CPU_HAS_OP32;
22
20
21
+
#if defined(CONFIG_CPU_SUBTYPE_SH7203)
22
+
boot_cpu_data.type = CPU_SH7203;
23
+
/* SH7203 has an FPU.. */
24
+
boot_cpu_data.flags |= CPU_HAS_FPU;
25
+
#elif defined(CONFIG_CPU_SUBTYPE_SH7206)
26
+
boot_cpu_data.type = CPU_SH7206;
27
+
/* While SH7206 has a DSP.. */
28
+
boot_cpu_data.flags |= CPU_HAS_DSP;
29
+
#endif
30
+
23
31
boot_cpu_data.dcache.ways = 4;
24
-
boot_cpu_data.dcache.way_incr = (1 << 11);
32
+
boot_cpu_data.dcache.way_incr = (1 << 11);
25
33
boot_cpu_data.dcache.sets = 128;
26
34
boot_cpu_data.dcache.entry_shift = 4;
27
35
boot_cpu_data.dcache.linesz = L1_CACHE_BYTES;
···
45
37
46
38
return 0;
47
39
}
48
-
+281
arch/sh/kernel/cpu/sh2a/setup-sh7203.c
+281
arch/sh/kernel/cpu/sh2a/setup-sh7203.c
···
1
+
/*
2
+
* SH7203 Setup
3
+
*
4
+
* Copyright (C) 2007 Paul Mundt
5
+
*
6
+
* This file is subject to the terms and conditions of the GNU General Public
7
+
* License. See the file "COPYING" in the main directory of this archive
8
+
* for more details.
9
+
*/
10
+
#include <linux/platform_device.h>
11
+
#include <linux/init.h>
12
+
#include <linux/serial.h>
13
+
#include <asm/sci.h>
14
+
15
+
enum {
16
+
UNUSED = 0,
17
+
18
+
/* interrupt sources */
19
+
IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
20
+
PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7,
21
+
DMAC0_DEI, DMAC0_HEI, DMAC1_DEI, DMAC1_HEI,
22
+
DMAC2_DEI, DMAC2_HEI, DMAC3_DEI, DMAC3_HEI,
23
+
DMAC4_DEI, DMAC4_HEI, DMAC5_DEI, DMAC5_HEI,
24
+
DMAC6_DEI, DMAC6_HEI, DMAC7_DEI, DMAC7_HEI,
25
+
USB, LCDC, CMT0, CMT1, BSC, WDT,
26
+
MTU2_TGI0A, MTU2_TGI0B, MTU2_TGI0C, MTU2_TGI0D,
27
+
MTU2_TCI0V, MTU2_TGI0E, MTU2_TGI0F,
28
+
MTU2_TGI1A, MTU2_TGI1B, MTU2_TCI1V, MTU2_TCI1U,
29
+
MTU2_TGI2A, MTU2_TGI2B, MTU2_TCI2V, MTU2_TCI2U,
30
+
MTU2_TGI3A, MTU2_TGI3B, MTU2_TGI3C, MTU2_TGI3D, MTU2_TCI3V,
31
+
MTU2_TGI4A, MTU2_TGI4B, MTU2_TGI4C, MTU2_TGI4D, MTU2_TCI4V,
32
+
ADC_ADI,
33
+
IIC30_STPI, IIC30_NAKI, IIC30_RXI, IIC30_TXI, IIC30_TEI,
34
+
IIC31_STPI, IIC31_NAKI, IIC31_RXI, IIC31_TXI, IIC31_TEI,
35
+
IIC32_STPI, IIC32_NAKI, IIC32_RXI, IIC32_TXI, IIC32_TEI,
36
+
IIC33_STPI, IIC33_NAKI, IIC33_RXI, IIC33_TXI, IIC33_TEI,
37
+
SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI,
38
+
SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI,
39
+
SCIF2_BRI, SCIF2_ERI, SCIF2_RXI, SCIF2_TXI,
40
+
SCIF3_BRI, SCIF3_ERI, SCIF3_RXI, SCIF3_TXI,
41
+
SSU0_SSERI, SSU0_SSRXI, SSU0_SSTXI,
42
+
SSU1_SSERI, SSU1_SSRXI, SSU1_SSTXI,
43
+
SSI0_SSII, SSI1_SSII, SSI2_SSII, SSI3_SSII,
44
+
FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
45
+
RTC_ARM, RTC_PRD, RTC_CUP,
46
+
RCAN0_ERS, RCAN0_OVR, RCAN0_RM0, RCAN0_RM1, RCAN0_SLE,
47
+
RCAN1_ERS, RCAN1_OVR, RCAN1_RM0, RCAN1_RM1, RCAN1_SLE,
48
+
49
+
/* interrupt groups */
50
+
PINT, DMAC0, DMAC1, DMAC2, DMAC3, DMAC4, DMAC5, DMAC6, DMAC7,
51
+
MTU0_ABCD, MTU0_VEF, MTU1_AB, MTU1_VU, MTU2_AB, MTU2_VU,
52
+
MTU3_ABCD, MTU4_ABCD,
53
+
IIC30, IIC31, IIC32, IIC33, SCIF0, SCIF1, SCIF2, SCIF3,
54
+
SSU0, SSU1, FLCTL, RTC, RCAN0, RCAN1
55
+
};
56
+
57
+
static struct intc_vect vectors[] __initdata = {
58
+
INTC_IRQ(IRQ0, 64), INTC_IRQ(IRQ1, 65),
59
+
INTC_IRQ(IRQ2, 66), INTC_IRQ(IRQ3, 67),
60
+
INTC_IRQ(IRQ4, 68), INTC_IRQ(IRQ5, 69),
61
+
INTC_IRQ(IRQ6, 70), INTC_IRQ(IRQ7, 71),
62
+
INTC_IRQ(PINT0, 80), INTC_IRQ(PINT1, 81),
63
+
INTC_IRQ(PINT2, 82), INTC_IRQ(PINT3, 83),
64
+
INTC_IRQ(PINT4, 84), INTC_IRQ(PINT5, 85),
65
+
INTC_IRQ(PINT6, 86), INTC_IRQ(PINT7, 87),
66
+
INTC_IRQ(DMAC0_DEI, 108), INTC_IRQ(DMAC0_HEI, 109),
67
+
INTC_IRQ(DMAC1_DEI, 112), INTC_IRQ(DMAC1_HEI, 113),
68
+
INTC_IRQ(DMAC2_DEI, 116), INTC_IRQ(DMAC2_HEI, 117),
69
+
INTC_IRQ(DMAC3_DEI, 120), INTC_IRQ(DMAC3_HEI, 121),
70
+
INTC_IRQ(DMAC4_DEI, 124), INTC_IRQ(DMAC4_HEI, 125),
71
+
INTC_IRQ(DMAC5_DEI, 128), INTC_IRQ(DMAC5_HEI, 129),
72
+
INTC_IRQ(DMAC6_DEI, 132), INTC_IRQ(DMAC6_HEI, 133),
73
+
INTC_IRQ(DMAC7_DEI, 136), INTC_IRQ(DMAC7_HEI, 137),
74
+
INTC_IRQ(USB, 140), INTC_IRQ(LCDC, 141),
75
+
INTC_IRQ(CMT0, 142), INTC_IRQ(CMT1, 143),
76
+
INTC_IRQ(BSC, 144), INTC_IRQ(WDT, 145),
77
+
INTC_IRQ(MTU2_TGI0A, 146), INTC_IRQ(MTU2_TGI0B, 147),
78
+
INTC_IRQ(MTU2_TGI0C, 148), INTC_IRQ(MTU2_TGI0D, 149),
79
+
INTC_IRQ(MTU2_TCI0V, 150),
80
+
INTC_IRQ(MTU2_TGI0E, 151), INTC_IRQ(MTU2_TGI0F, 152),
81
+
INTC_IRQ(MTU2_TGI1A, 153), INTC_IRQ(MTU2_TGI1B, 154),
82
+
INTC_IRQ(MTU2_TCI1V, 155), INTC_IRQ(MTU2_TCI1U, 156),
83
+
INTC_IRQ(MTU2_TGI2A, 157), INTC_IRQ(MTU2_TGI2B, 158),
84
+
INTC_IRQ(MTU2_TCI2V, 159), INTC_IRQ(MTU2_TCI2U, 160),
85
+
INTC_IRQ(MTU2_TGI3A, 161), INTC_IRQ(MTU2_TGI3B, 162),
86
+
INTC_IRQ(MTU2_TGI3C, 163), INTC_IRQ(MTU2_TGI3D, 164),
87
+
INTC_IRQ(MTU2_TCI3V, 165),
88
+
INTC_IRQ(MTU2_TGI4A, 166), INTC_IRQ(MTU2_TGI4B, 167),
89
+
INTC_IRQ(MTU2_TGI4C, 168), INTC_IRQ(MTU2_TGI4D, 169),
90
+
INTC_IRQ(MTU2_TCI4V, 170),
91
+
INTC_IRQ(ADC_ADI, 171),
92
+
INTC_IRQ(IIC30_STPI, 172), INTC_IRQ(IIC30_NAKI, 173),
93
+
INTC_IRQ(IIC30_RXI, 174), INTC_IRQ(IIC30_TXI, 175),
94
+
INTC_IRQ(IIC30_TEI, 176),
95
+
INTC_IRQ(IIC31_STPI, 177), INTC_IRQ(IIC31_NAKI, 178),
96
+
INTC_IRQ(IIC31_RXI, 179), INTC_IRQ(IIC31_TXI, 180),
97
+
INTC_IRQ(IIC31_TEI, 181),
98
+
INTC_IRQ(IIC32_STPI, 182), INTC_IRQ(IIC32_NAKI, 183),
99
+
INTC_IRQ(IIC32_RXI, 184), INTC_IRQ(IIC32_TXI, 185),
100
+
INTC_IRQ(IIC32_TEI, 186),
101
+
INTC_IRQ(IIC33_STPI, 187), INTC_IRQ(IIC33_NAKI, 188),
102
+
INTC_IRQ(IIC33_RXI, 189), INTC_IRQ(IIC33_TXI, 190),
103
+
INTC_IRQ(IIC33_TEI, 191),
104
+
INTC_IRQ(SCIF0_BRI, 192), INTC_IRQ(SCIF0_ERI, 193),
105
+
INTC_IRQ(SCIF0_RXI, 194), INTC_IRQ(SCIF0_TXI, 195),
106
+
INTC_IRQ(SCIF1_BRI, 196), INTC_IRQ(SCIF1_ERI, 197),
107
+
INTC_IRQ(SCIF1_RXI, 198), INTC_IRQ(SCIF1_TXI, 199),
108
+
INTC_IRQ(SCIF2_BRI, 200), INTC_IRQ(SCIF2_ERI, 201),
109
+
INTC_IRQ(SCIF2_RXI, 202), INTC_IRQ(SCIF2_TXI, 203),
110
+
INTC_IRQ(SCIF3_BRI, 204), INTC_IRQ(SCIF3_ERI, 205),
111
+
INTC_IRQ(SCIF3_RXI, 206), INTC_IRQ(SCIF3_TXI, 207),
112
+
INTC_IRQ(SSU0_SSERI, 208), INTC_IRQ(SSU0_SSRXI, 209),
113
+
INTC_IRQ(SSU0_SSTXI, 210),
114
+
INTC_IRQ(SSU1_SSERI, 211), INTC_IRQ(SSU1_SSRXI, 212),
115
+
INTC_IRQ(SSU1_SSTXI, 213),
116
+
INTC_IRQ(SSI0_SSII, 214), INTC_IRQ(SSI1_SSII, 215),
117
+
INTC_IRQ(SSI2_SSII, 216), INTC_IRQ(SSI3_SSII, 217),
118
+
INTC_IRQ(FLCTL_FLSTEI, 224), INTC_IRQ(FLCTL_FLTENDI, 225),
119
+
INTC_IRQ(FLCTL_FLTREQ0I, 226), INTC_IRQ(FLCTL_FLTREQ1I, 227),
120
+
INTC_IRQ(RTC_ARM, 231), INTC_IRQ(RTC_PRD, 232),
121
+
INTC_IRQ(RTC_CUP, 233),
122
+
INTC_IRQ(RCAN0_ERS, 234), INTC_IRQ(RCAN0_OVR, 235),
123
+
INTC_IRQ(RCAN0_RM0, 236), INTC_IRQ(RCAN0_RM1, 237),
124
+
INTC_IRQ(RCAN0_SLE, 238),
125
+
INTC_IRQ(RCAN1_ERS, 239), INTC_IRQ(RCAN1_OVR, 240),
126
+
INTC_IRQ(RCAN1_RM0, 241), INTC_IRQ(RCAN1_RM1, 242),
127
+
INTC_IRQ(RCAN1_SLE, 243),
128
+
};
129
+
130
+
static struct intc_group groups[] __initdata = {
131
+
INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3,
132
+
PINT4, PINT5, PINT6, PINT7),
133
+
INTC_GROUP(DMAC0, DMAC0_DEI, DMAC0_HEI),
134
+
INTC_GROUP(DMAC1, DMAC1_DEI, DMAC1_HEI),
135
+
INTC_GROUP(DMAC2, DMAC2_DEI, DMAC2_HEI),
136
+
INTC_GROUP(DMAC3, DMAC3_DEI, DMAC3_HEI),
137
+
INTC_GROUP(DMAC4, DMAC4_DEI, DMAC4_HEI),
138
+
INTC_GROUP(DMAC5, DMAC5_DEI, DMAC5_HEI),
139
+
INTC_GROUP(DMAC6, DMAC6_DEI, DMAC6_HEI),
140
+
INTC_GROUP(DMAC7, DMAC7_DEI, DMAC7_HEI),
141
+
INTC_GROUP(MTU0_ABCD, MTU2_TGI0A, MTU2_TGI0B, MTU2_TGI0C, MTU2_TGI0D),
142
+
INTC_GROUP(MTU0_VEF, MTU2_TCI0V, MTU2_TGI0E, MTU2_TGI0F),
143
+
INTC_GROUP(MTU1_AB, MTU2_TGI1A, MTU2_TGI1B),
144
+
INTC_GROUP(MTU1_VU, MTU2_TCI1V, MTU2_TCI1U),
145
+
INTC_GROUP(MTU2_AB, MTU2_TGI2A, MTU2_TGI2B),
146
+
INTC_GROUP(MTU2_VU, MTU2_TCI2V, MTU2_TCI2U),
147
+
INTC_GROUP(MTU3_ABCD, MTU2_TGI3A, MTU2_TGI3B, MTU2_TGI3C, MTU2_TGI3D),
148
+
INTC_GROUP(MTU4_ABCD, MTU2_TGI4A, MTU2_TGI4B, MTU2_TGI4C, MTU2_TGI4D),
149
+
INTC_GROUP(IIC30, IIC30_STPI, IIC30_NAKI, IIC30_RXI, IIC30_TXI,
150
+
IIC30_TEI),
151
+
INTC_GROUP(IIC31, IIC31_STPI, IIC31_NAKI, IIC31_RXI, IIC31_TXI,
152
+
IIC31_TEI),
153
+
INTC_GROUP(IIC32, IIC32_STPI, IIC32_NAKI, IIC32_RXI, IIC32_TXI,
154
+
IIC32_TEI),
155
+
INTC_GROUP(IIC33, IIC33_STPI, IIC33_NAKI, IIC33_RXI, IIC33_TXI,
156
+
IIC33_TEI),
157
+
INTC_GROUP(SCIF0, SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI),
158
+
INTC_GROUP(SCIF1, SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI),
159
+
INTC_GROUP(SCIF2, SCIF2_BRI, SCIF2_ERI, SCIF2_RXI, SCIF2_TXI),
160
+
INTC_GROUP(SCIF3, SCIF3_BRI, SCIF3_ERI, SCIF3_RXI, SCIF3_TXI),
161
+
INTC_GROUP(SSU0, SSU0_SSERI, SSU0_SSRXI, SSU0_SSTXI),
162
+
INTC_GROUP(SSU1, SSU1_SSERI, SSU1_SSRXI, SSU1_SSTXI),
163
+
INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I,
164
+
FLCTL_FLTREQ1I),
165
+
INTC_GROUP(RTC, RTC_ARM, RTC_PRD, RTC_CUP),
166
+
INTC_GROUP(RCAN0, RCAN0_ERS, RCAN0_OVR, RCAN0_RM0, RCAN0_RM1,
167
+
RCAN0_SLE),
168
+
INTC_GROUP(RCAN1, RCAN1_ERS, RCAN1_OVR, RCAN1_RM0, RCAN1_RM1,
169
+
RCAN1_SLE),
170
+
};
171
+
172
+
static struct intc_prio_reg prio_registers[] __initdata = {
173
+
{ 0xfffe0818, 0, 16, 4, /* IPR01 */ { IRQ0, IRQ1, IRQ2, IRQ3 } },
174
+
{ 0xfffe081a, 0, 16, 4, /* IPR02 */ { IRQ4, IRQ5, IRQ6, IRQ7 } },
175
+
{ 0xfffe0820, 0, 16, 4, /* IPR05 */ { PINT, 0, 0, 0 } },
176
+
{ 0xfffe0c00, 0, 16, 4, /* IPR06 */ { DMAC0, DMAC1, DMAC2, DMAC3 } },
177
+
{ 0xfffe0c02, 0, 16, 4, /* IPR07 */ { DMAC4, DMAC5, DMAC6, DMAC7 } },
178
+
{ 0xfffe0c04, 0, 16, 4, /* IPR08 */ { USB, LCDC, CMT0, CMT1 } },
179
+
{ 0xfffe0c06, 0, 16, 4, /* IPR09 */ { BSC, WDT, MTU0_ABCD, MTU0_VEF } },
180
+
{ 0xfffe0c08, 0, 16, 4, /* IPR10 */ { MTU1_AB, MTU1_VU, MTU2_AB,
181
+
MTU2_VU } },
182
+
{ 0xfffe0c0a, 0, 16, 4, /* IPR11 */ { MTU3_ABCD, MTU2_TCI3V, MTU4_ABCD,
183
+
MTU2_TCI4V } },
184
+
{ 0xfffe0c0c, 0, 16, 4, /* IPR12 */ { ADC_ADI, IIC30, IIC31, IIC32 } },
185
+
{ 0xfffe0c0e, 0, 16, 4, /* IPR13 */ { IIC33, SCIF0, SCIF1, SCIF2 } },
186
+
{ 0xfffe0c10, 0, 16, 4, /* IPR14 */ { SCIF3, SSU0, SSU1, SSI0_SSII } },
187
+
{ 0xfffe0c12, 0, 16, 4, /* IPR15 */ { SSI1_SSII, SSI2_SSII,
188
+
SSI3_SSII, 0 } },
189
+
{ 0xfffe0c14, 0, 16, 4, /* IPR16 */ { FLCTL, 0, RTC, RCAN0 } },
190
+
{ 0xfffe0c16, 0, 16, 4, /* IPR17 */ { RCAN1, 0, 0, 0 } },
191
+
};
192
+
193
+
static struct intc_mask_reg mask_registers[] __initdata = {
194
+
{ 0xfffe0808, 0, 16, /* PINTER */
195
+
{ 0, 0, 0, 0, 0, 0, 0, 0,
196
+
PINT7, PINT6, PINT5, PINT4, PINT3, PINT2, PINT1, PINT0 } },
197
+
};
198
+
199
+
static DECLARE_INTC_DESC(intc_desc, "sh7203", vectors, groups,
200
+
NULL, mask_registers, prio_registers, NULL);
201
+
202
+
static struct plat_sci_port sci_platform_data[] = {
203
+
{
204
+
.mapbase = 0xfffe8000,
205
+
.flags = UPF_BOOT_AUTOCONF,
206
+
.type = PORT_SCIF,
207
+
.irqs = { 193, 194, 195, 192 },
208
+
}, {
209
+
.mapbase = 0xfffe8800,
210
+
.flags = UPF_BOOT_AUTOCONF,
211
+
.type = PORT_SCIF,
212
+
.irqs = { 197, 198, 199, 196 },
213
+
}, {
214
+
.mapbase = 0xfffe9000,
215
+
.flags = UPF_BOOT_AUTOCONF,
216
+
.type = PORT_SCIF,
217
+
.irqs = { 201, 202, 203, 200 },
218
+
}, {
219
+
.mapbase = 0xfffe9800,
220
+
.flags = UPF_BOOT_AUTOCONF,
221
+
.type = PORT_SCIF,
222
+
.irqs = { 205, 206, 207, 204 },
223
+
}, {
224
+
.flags = 0,
225
+
}
226
+
};
227
+
228
+
static struct platform_device sci_device = {
229
+
.name = "sh-sci",
230
+
.id = -1,
231
+
.dev = {
232
+
.platform_data = sci_platform_data,
233
+
},
234
+
};
235
+
236
+
static struct resource rtc_resources[] = {
237
+
[0] = {
238
+
.start = 0xffff2000,
239
+
.end = 0xffff2000 + 0x58 - 1,
240
+
.flags = IORESOURCE_IO,
241
+
},
242
+
[1] = {
243
+
/* Period IRQ */
244
+
.start = 232,
245
+
.flags = IORESOURCE_IRQ,
246
+
},
247
+
[2] = {
248
+
/* Carry IRQ */
249
+
.start = 233,
250
+
.flags = IORESOURCE_IRQ,
251
+
},
252
+
[3] = {
253
+
/* Alarm IRQ */
254
+
.start = 231,
255
+
.flags = IORESOURCE_IRQ,
256
+
},
257
+
};
258
+
259
+
static struct platform_device rtc_device = {
260
+
.name = "sh-rtc",
261
+
.id = -1,
262
+
.num_resources = ARRAY_SIZE(rtc_resources),
263
+
.resource = rtc_resources,
264
+
};
265
+
266
+
static struct platform_device *sh7203_devices[] __initdata = {
267
+
&sci_device,
268
+
&rtc_device,
269
+
};
270
+
271
+
static int __init sh7203_devices_setup(void)
272
+
{
273
+
return platform_add_devices(sh7203_devices,
274
+
ARRAY_SIZE(sh7203_devices));
275
+
}
276
+
__initcall(sh7203_devices_setup);
277
+
278
+
void __init plat_irq_setup(void)
279
+
{
280
+
register_intc_controller(&intc_desc);
281
+
}
+1
arch/sh/kernel/setup.c
+1
arch/sh/kernel/setup.c
+1
-1
arch/sh/kernel/timers/timer-cmt.c
+1
-1
arch/sh/kernel/timers/timer-cmt.c
···
31
31
#define cmt_clock_enable() do { ctrl_outb(ctrl_inb(STBCR3) & ~0x10, STBCR3); } while(0)
32
32
#define CMT_CMCSR_INIT 0x0040
33
33
#define CMT_CMCSR_CALIB 0x0000
34
-
#elif defined(CONFIG_CPU_SUBTYPE_SH7206)
34
+
#elif defined(CONFIG_CPU_SUBTYPE_SH7203) || defined(CONFIG_CPU_SUBTYPE_SH7206)
35
35
#define CMT_CMSTR 0xfffec000
36
36
#define CMT_CMCSR_0 0xfffec002
37
37
#define CMT_CMCNT_0 0xfffec004
+4
-2
drivers/serial/sh-sci.h
+4
-2
drivers/serial/sh-sci.h
···
142
142
# define SCIF_OPER 0x0001 /* Overrun error bit */
143
143
# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
144
144
# define SCIF_ONLY
145
-
#elif defined(CONFIG_CPU_SUBTYPE_SH7206)
145
+
#elif defined(CONFIG_CPU_SUBTYPE_SH7203) || \
146
+
defined(CONFIG_CPU_SUBTYPE_SH7206)
146
147
# define SCSPTR0 0xfffe8020 /* 16 bit SCIF */
147
148
# define SCSPTR1 0xfffe8820 /* 16 bit SCIF */
148
149
# define SCSPTR2 0xfffe9020 /* 16 bit SCIF */
···
618
617
return ctrl_inw(SCSPTR5) & 0x0001 ? 1 : 0; /* SCIF */
619
618
return 1;
620
619
}
621
-
#elif defined(CONFIG_CPU_SUBTYPE_SH7206)
620
+
#elif defined(CONFIG_CPU_SUBTYPE_SH7203) || \
621
+
defined(CONFIG_CPU_SUBTYPE_SH7206)
622
622
static inline int sci_rxd_in(struct uart_port *port)
623
623
{
624
624
if (port->mapbase == 0xfffe8000)
+1
-1
include/asm-sh/bugs.h
+1
-1
include/asm-sh/bugs.h
-2
include/asm-sh/cpu-sh2a/freq.h
-2
include/asm-sh/cpu-sh2a/freq.h