ARM: dts: vt8500: Add L2 cache controller on WM8850/WM8950

WonderMedia WM8850/WM8950 uses an ARM PL310 cache controller for its
L2 cache, add it.

The parameters have been deduced from vendor's U-boot environment
variables, which the downstream code uses to initialize the
controller. They set the following register values:

aux = 0x3e440000
prefetch_ctrl = 0x70000007

Their initialization code also unconditionally sets the flags
L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN, so encode those too

Signed-off-by: Alexey Charkov <[e-mail]>
Link: https://lore.kernel.org/r/[e-mail]
Signed-off-by: Krzysztof Kozlowski <[e-mail]>

arch/arm/boot/dts/vt8500/wm8850.dtsi

···
 			device_type = "cpu";
 			compatible = "arm,cortex-a9";
 			reg = <0x0>;
+			next-level-cache = <&l2_cache>;
 		};
 	};
 
···
 			reg = <0xd8004000 0x100>;
 			interrupts = <10>;
                 };
+
+		l2_cache: cache-controller@d9000000 {
+			compatible = "arm,pl310-cache";
+			reg = <0xd9000000 0x1000>;
+			arm,double-linefill = <1>;
+			arm,dynamic-clock-gating = <1>;
+			arm,shared-override;
+			arm,standby-mode = <1>;
+			cache-level = <2>;
+			cache-unified;
+			prefetch-data = <1>;
+			prefetch-instr = <1>;
+		};
 	};
 };