tjh.dev
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kernel
os
linux
dt-bindings: clock: Introduce QCOM Display clock bindings
Add device tree bindings for display clock controller for Qualcomm
Technology Inc's SDM845 SoCs.
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
authored by
Taniya Das
and committed by
Stephen Boyd
6c79d12e
da172d2b
+64
+19
Documentation/devicetree/bindings/clock/qcom,dispcc.txt
+19
Documentation/devicetree/bindings/clock/qcom,dispcc.txt
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Qualcomm Technologies, Inc. Display Clock Controller Binding
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------------------------------------------------------------
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Required properties :
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- compatible : shall contain "qcom,sdm845-dispcc"
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- reg : shall contain base register location and length.
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- #clock-cells : from common clock binding, shall contain 1.
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- #reset-cells : from common reset binding, shall contain 1.
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- #power-domain-cells : from generic power domain binding, shall contain 1.
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Example:
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dispcc: clock-controller@af00000 {
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compatible = "qcom,sdm845-dispcc";
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reg = <0xaf00000 0x100000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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};
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include/dt-bindings/clock/qcom,dispcc-sdm845.h
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include/dt-bindings/clock/qcom,dispcc-sdm845.h
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2018, The Linux Foundation. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_CLK_SDM_DISP_CC_SDM845_H
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#define _DT_BINDINGS_CLK_SDM_DISP_CC_SDM845_H
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/* DISP_CC clock registers */
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#define DISP_CC_MDSS_AHB_CLK 0
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#define DISP_CC_MDSS_AXI_CLK 1
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#define DISP_CC_MDSS_BYTE0_CLK 2
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#define DISP_CC_MDSS_BYTE0_CLK_SRC 3
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#define DISP_CC_MDSS_BYTE0_INTF_CLK 4
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#define DISP_CC_MDSS_BYTE1_CLK 5
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#define DISP_CC_MDSS_BYTE1_CLK_SRC 6
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#define DISP_CC_MDSS_BYTE1_INTF_CLK 7
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#define DISP_CC_MDSS_ESC0_CLK 8
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#define DISP_CC_MDSS_ESC0_CLK_SRC 9
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#define DISP_CC_MDSS_ESC1_CLK 10
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#define DISP_CC_MDSS_ESC1_CLK_SRC 11
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#define DISP_CC_MDSS_MDP_CLK 12
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#define DISP_CC_MDSS_MDP_CLK_SRC 13
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#define DISP_CC_MDSS_MDP_LUT_CLK 14
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#define DISP_CC_MDSS_PCLK0_CLK 15
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#define DISP_CC_MDSS_PCLK0_CLK_SRC 16
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#define DISP_CC_MDSS_PCLK1_CLK 17
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#define DISP_CC_MDSS_PCLK1_CLK_SRC 18
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#define DISP_CC_MDSS_ROT_CLK 19
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#define DISP_CC_MDSS_ROT_CLK_SRC 20
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#define DISP_CC_MDSS_RSCC_AHB_CLK 21
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#define DISP_CC_MDSS_RSCC_VSYNC_CLK 22
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#define DISP_CC_MDSS_VSYNC_CLK 23
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#define DISP_CC_MDSS_VSYNC_CLK_SRC 24
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#define DISP_CC_PLL0 25
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#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 26
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#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 27
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/* DISP_CC Reset */
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#define DISP_CC_MDSS_RSCC_BCR 0
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/* DISP_CC GDSCR */
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#define MDSS_GDSC 0
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#endif