Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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kernel
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linux
x86-64: clean up io-apic accesses
This is just commit 130fe05dbc0114609cfef9815c0c5580b42decfa ported to
x86-64, for all the same reasons. It cleans up the IO-APIC accesses in
order to then fix the ordering issues.
We move the accessor functions (that were only used by io_apic.c) out of
a header file, and use proper memory-mapped accesses rather than making
up our own "volatile" pointers.
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
+46
arch/x86_64/kernel/io_apic.c
+46
arch/x86_64/kernel/io_apic.c
···
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short apic, pin, next;
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} irq_2_pin[PIN_MAP_SIZE];
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struct io_apic {
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unsigned int index;
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unsigned int unused[3];
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unsigned int data;
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};
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+
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static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
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{
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return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
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+ (mp_ioapics[idx].mpc_apicaddr & ~PAGE_MASK);
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}
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+
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static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
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{
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struct io_apic __iomem *io_apic = io_apic_base(apic);
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writel(reg, &io_apic->index);
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return readl(&io_apic->data);
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}
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static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
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{
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struct io_apic __iomem *io_apic = io_apic_base(apic);
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writel(reg, &io_apic->index);
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writel(value, &io_apic->data);
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}
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/*
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* Re-write a value: to be used for read-modify-write
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* cycles where the read already set up the index register.
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*/
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static inline void io_apic_modify(unsigned int apic, unsigned int value)
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{
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struct io_apic __iomem *io_apic = io_apic_base(apic);
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writel(value, &io_apic->data);
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}
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/*
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* Synchronize the IO-APIC and the CPU by doing
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* a dummy read from the IO-APIC
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*/
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static inline void io_apic_sync(unsigned int apic)
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{
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struct io_apic __iomem *io_apic = io_apic_base(apic);
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readl(&io_apic->data);
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}
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+
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#define __DO_ACTION(R, ACTION, FINAL) \
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\
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{ \
-34
include/asm-x86_64/io_apic.h
-34
include/asm-x86_64/io_apic.h
···
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#define APIC_MISMATCH_DEBUG
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-
#define IO_APIC_BASE(idx) \
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((volatile int *)(__fix_to_virt(FIX_IO_APIC_BASE_0 + idx) \
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+ (mp_ioapics[idx].mpc_apicaddr & ~PAGE_MASK)))
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-
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/*
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* The structure of the IO-APIC:
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*/
···
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/* non-0 if default (table-less) MP configuration */
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extern int mpc_default_type;
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-
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static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
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{
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*IO_APIC_BASE(apic) = reg;
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return *(IO_APIC_BASE(apic)+4);
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}
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-
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static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
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{
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*IO_APIC_BASE(apic) = reg;
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*(IO_APIC_BASE(apic)+4) = value;
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}
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/*
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* Re-write a value: to be used for read-modify-write
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* cycles where the read already set up the index register.
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*/
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static inline void io_apic_modify(unsigned int apic, unsigned int value)
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{
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*(IO_APIC_BASE(apic)+4) = value;
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}
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-
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/*
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* Synchronize the IO-APIC and the CPU by doing
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* a dummy read from the IO-APIC
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*/
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static inline void io_apic_sync(unsigned int apic)
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{
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(void) *(IO_APIC_BASE(apic)+4);
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}
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/* 1 if "noapic" boot option passed */
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extern int skip_ioapic_setup;