···150150#define page_to_bus(page) (page_to_phys(page))151151#define bus_to_virt(addr) (phys_to_virt(addr))152152153153-extern void iounmap(void *addr);153153+extern void iounmap(void __iomem *addr);154154/*extern void *__ioremap(phys_addr_t address, unsigned long size,155155 unsigned long flags);*/156156extern void __iomem *ioremap(phys_addr_t address, unsigned long size);
+68-80
arch/microblaze/kernel/cpu/cache.c
···17171818static inline void __enable_icache_msr(void)1919{2020- __asm__ __volatile__ (" msrset r0, %0; \2121- nop; " \2020+ __asm__ __volatile__ (" msrset r0, %0;" \2121+ "nop;" \2222 : : "i" (MSR_ICE) : "memory");2323}24242525static inline void __disable_icache_msr(void)2626{2727- __asm__ __volatile__ (" msrclr r0, %0; \2828- nop; " \2727+ __asm__ __volatile__ (" msrclr r0, %0;" \2828+ "nop;" \2929 : : "i" (MSR_ICE) : "memory");3030}31313232static inline void __enable_dcache_msr(void)3333{3434- __asm__ __volatile__ (" msrset r0, %0; \3535- nop; " \3636- : \3737- : "i" (MSR_DCE) \3838- : "memory");3434+ __asm__ __volatile__ (" msrset r0, %0;" \3535+ "nop;" \3636+ : : "i" (MSR_DCE) : "memory");3937}40384139static inline void __disable_dcache_msr(void)4240{4343- __asm__ __volatile__ (" msrclr r0, %0; \4444- nop; " \4545- : \4646- : "i" (MSR_DCE) \4747- : "memory");4141+ __asm__ __volatile__ (" msrclr r0, %0;" \4242+ "nop; " \4343+ : : "i" (MSR_DCE) : "memory");4844}49455046static inline void __enable_icache_nomsr(void)5147{5252- __asm__ __volatile__ (" mfs r12, rmsr; \5353- nop; \5454- ori r12, r12, %0; \5555- mts rmsr, r12; \5656- nop; " \5757- : \5858- : "i" (MSR_ICE) \5959- : "memory", "r12");4848+ __asm__ __volatile__ (" mfs r12, rmsr;" \4949+ "nop;" \5050+ "ori r12, r12, %0;" \5151+ "mts rmsr, r12;" \5252+ "nop;" \5353+ : : "i" (MSR_ICE) : "memory", "r12");6054}61556256static inline void __disable_icache_nomsr(void)6357{6464- __asm__ __volatile__ (" mfs r12, rmsr; \6565- nop; \6666- andi r12, r12, ~%0; \6767- mts rmsr, r12; \6868- nop; " \6969- : \7070- : "i" (MSR_ICE) \7171- : "memory", "r12");5858+ __asm__ __volatile__ (" mfs r12, rmsr;" \5959+ "nop;" \6060+ "andi r12, r12, ~%0;" \6161+ "mts rmsr, r12;" \6262+ "nop;" \6363+ : : "i" (MSR_ICE) : "memory", "r12");7264}73657466static inline void __enable_dcache_nomsr(void)7567{7676- __asm__ __volatile__ (" mfs r12, rmsr; \7777- nop; \7878- ori r12, r12, %0; \7979- mts rmsr, r12; \8080- nop; " \8181- : \8282- : "i" (MSR_DCE) \8383- : "memory", "r12");6868+ __asm__ __volatile__ (" mfs r12, rmsr;" \6969+ "nop;" \7070+ "ori r12, r12, %0;" \7171+ "mts rmsr, r12;" \7272+ "nop;" \7373+ : : "i" (MSR_DCE) : "memory", "r12");8474}85758676static inline void __disable_dcache_nomsr(void)8777{8888- __asm__ __volatile__ (" mfs r12, rmsr; \8989- nop; \9090- andi r12, r12, ~%0; \9191- mts rmsr, r12; \9292- nop; " \9393- : \9494- : "i" (MSR_DCE) \9595- : "memory", "r12");7878+ __asm__ __volatile__ (" mfs r12, rmsr;" \7979+ "nop;" \8080+ "andi r12, r12, ~%0;" \8181+ "mts rmsr, r12;" \8282+ "nop;" \8383+ : : "i" (MSR_DCE) : "memory", "r12");9684}97859886···94106 int align = ~(cache_line_length - 1); \95107 end = min(start + cache_size, end); \96108 start &= align; \9797-} while (0);109109+} while (0)9811099111/*100112 * Helper macro to loop over the specified cache_size/line_length and···106118 int step = -line_length; \107119 WARN_ON(step >= 0); \108120 \109109- __asm__ __volatile__ (" 1: " #op " %0, r0; \110110- bgtid %0, 1b; \111111- addk %0, %0, %1; \112112- " : : "r" (len), "r" (step) \121121+ __asm__ __volatile__ (" 1: " #op " %0, r0;" \122122+ "bgtid %0, 1b;" \123123+ "addk %0, %0, %1;" \124124+ : : "r" (len), "r" (step) \113125 : "memory"); \114114-} while (0);126126+} while (0)115127116128/* Used for wdc.flush/clear which can use rB for offset which is not possible117129 * to use for simple wdc or wic.···130142 count = end - start; \131143 WARN_ON(count < 0); \132144 \133133- __asm__ __volatile__ (" 1: " #op " %0, %1; \134134- bgtid %1, 1b; \135135- addk %1, %1, %2; \136136- " : : "r" (start), "r" (count), \145145+ __asm__ __volatile__ (" 1: " #op " %0, %1;" \146146+ "bgtid %1, 1b;" \147147+ "addk %1, %1, %2;" \148148+ : : "r" (start), "r" (count), \137149 "r" (step) : "memory"); \138138-} while (0);150150+} while (0)139151140152/* It is used only first parameter for OP - for wic, wdc */141153#define CACHE_RANGE_LOOP_1(start, end, line_length, op) \···145157 end = ((end & align) == end) ? end - line_length : end & align; \146158 WARN_ON(end - start < 0); \147159 \148148- __asm__ __volatile__ (" 1: " #op " %1, r0; \149149- cmpu %0, %1, %2; \150150- bgtid %0, 1b; \151151- addk %1, %1, %3; \152152- " : : "r" (temp), "r" (start), "r" (end),\160160+ __asm__ __volatile__ (" 1: " #op " %1, r0;" \161161+ "cmpu %0, %1, %2;" \162162+ "bgtid %0, 1b;" \163163+ "addk %1, %1, %3;" \164164+ : : "r" (temp), "r" (start), "r" (end), \153165 "r" (line_length) : "memory"); \154154-} while (0);166166+} while (0)155167156168#define ASM_LOOP157169···340352#endif341353 pr_debug("%s\n", __func__);342354#ifdef ASM_LOOP343343- CACHE_ALL_LOOP(cpuinfo.dcache_size, cpuinfo.dcache_line_length, wdc)355355+ CACHE_ALL_LOOP(cpuinfo.dcache_size, cpuinfo.dcache_line_length, wdc);344356#else345357 for (i = 0; i < cpuinfo.dcache_size;346358 i += cpuinfo.dcache_line_length)···349361#endif350362}351363352352-/* FIXME It is blindly invalidation as is expected364364+/*365365+ * FIXME It is blindly invalidation as is expected353366 * but can't be called on noMMU in microblaze_cache_init below354367 *355368 * MS: noMMU kernel won't boot if simple wdc is used···364375 pr_debug("%s\n", __func__);365376#ifdef ASM_LOOP366377 CACHE_ALL_LOOP(cpuinfo.dcache_size, cpuinfo.dcache_line_length,367367- wdc)378378+ wdc);368379#else369380 for (i = 0; i < cpuinfo.dcache_size;370381 i += cpuinfo.dcache_line_length)···605616#define CPUVER_7_20_A 0x0c606617#define CPUVER_7_20_D 0x0f607618608608-#define INFO(s) printk(KERN_INFO "cache: " s "\n");609609-610619void microblaze_cache_init(void)611620{612621 if (cpuinfo.use_instr & PVR2_USE_MSR_INSTR) {613622 if (cpuinfo.dcache_wb) {614614- INFO("wb_msr");623623+ pr_info("wb_msr\n");615624 mbc = (struct scache *)&wb_msr;616625 if (cpuinfo.ver_code <= CPUVER_7_20_D) {617626 /* MS: problem with signal handling - hw bug */618618- INFO("WB won't work properly");627627+ pr_info("WB won't work properly\n");619628 }620629 } else {621630 if (cpuinfo.ver_code >= CPUVER_7_20_A) {622622- INFO("wt_msr_noirq");631631+ pr_info("wt_msr_noirq\n");623632 mbc = (struct scache *)&wt_msr_noirq;624633 } else {625625- INFO("wt_msr");634634+ pr_info("wt_msr\n");626635 mbc = (struct scache *)&wt_msr;627636 }628637 }629638 } else {630639 if (cpuinfo.dcache_wb) {631631- INFO("wb_nomsr");640640+ pr_info("wb_nomsr\n");632641 mbc = (struct scache *)&wb_nomsr;633642 if (cpuinfo.ver_code <= CPUVER_7_20_D) {634643 /* MS: problem with signal handling - hw bug */635635- INFO("WB won't work properly");644644+ pr_info("WB won't work properly\n");636645 }637646 } else {638647 if (cpuinfo.ver_code >= CPUVER_7_20_A) {639639- INFO("wt_nomsr_noirq");648648+ pr_info("wt_nomsr_noirq\n");640649 mbc = (struct scache *)&wt_nomsr_noirq;641650 } else {642642- INFO("wt_nomsr");651651+ pr_info("wt_nomsr\n");643652 mbc = (struct scache *)&wt_nomsr;644653 }645654 }646655 }647647-/* FIXME Invalidation is done in U-BOOT648648- * WT cache: Data is already written to main memory649649- * WB cache: Discard data on noMMU which caused that kernel doesn't boot650650- */656656+ /*657657+ * FIXME Invalidation is done in U-BOOT658658+ * WT cache: Data is already written to main memory659659+ * WB cache: Discard data on noMMU which caused that kernel doesn't boot660660+ */651661 /* invalidate_dcache(); */652662 enable_dcache();653663
+10-11
arch/microblaze/kernel/cpu/cpuinfo-pvr-full.c
···2727 early_printk("ERROR: Microblaze " x "-different for PVR and DTS\n");2828#else2929#define err_printk(x) \3030- printk(KERN_INFO "ERROR: Microblaze " x "-different for PVR and DTS\n");3030+ pr_info("ERROR: Microblaze " x "-different for PVR and DTS\n");3131#endif32323333void set_cpuinfo_pvr_full(struct cpuinfo *ci, struct device_node *cpu)···38383939 CI(ver_code, VERSION);4040 if (!ci->ver_code) {4141- printk(KERN_ERR "ERROR: MB has broken PVR regs "4242- "-> use DTS setting\n");4141+ pr_err("ERROR: MB has broken PVR regs -> use DTS setting\n");4342 return;4443 }45444646- temp = PVR_USE_BARREL(pvr) | PVR_USE_MSR_INSTR(pvr) |\4545+ temp = PVR_USE_BARREL(pvr) | PVR_USE_MSR_INSTR(pvr) |4746 PVR_USE_PCMP_INSTR(pvr) | PVR_USE_DIV(pvr);4847 if (ci->use_instr != temp)4948 err_printk("BARREL, MSR, PCMP or DIV");···5859 err_printk("HW_FPU");5960 ci->use_fpu = temp;60616161- ci->use_exc = PVR_OPCODE_0x0_ILLEGAL(pvr) |\6262- PVR_UNALIGNED_EXCEPTION(pvr) |\6363- PVR_ILL_OPCODE_EXCEPTION(pvr) |\6464- PVR_IOPB_BUS_EXCEPTION(pvr) |\6565- PVR_DOPB_BUS_EXCEPTION(pvr) |\6666- PVR_DIV_ZERO_EXCEPTION(pvr) |\6767- PVR_FPU_EXCEPTION(pvr) |\6262+ ci->use_exc = PVR_OPCODE_0x0_ILLEGAL(pvr) |6363+ PVR_UNALIGNED_EXCEPTION(pvr) |6464+ PVR_ILL_OPCODE_EXCEPTION(pvr) |6565+ PVR_IOPB_BUS_EXCEPTION(pvr) |6666+ PVR_DOPB_BUS_EXCEPTION(pvr) |6767+ PVR_DIV_ZERO_EXCEPTION(pvr) |6868+ PVR_FPU_EXCEPTION(pvr) |6869 PVR_FSL_EXCEPTION(pvr);69707071 CI(pvr_user1, USER1);
+6-7
arch/microblaze/kernel/cpu/cpuinfo.c
···68686969 cpu = (struct device_node *) of_find_node_by_type(NULL, "cpu");7070 if (!cpu)7171- printk(KERN_ERR "You don't have cpu!!!\n");7171+ pr_err("You don't have cpu!!!\n");72727373- printk(KERN_INFO "%s: initialising\n", __func__);7373+ pr_info("%s: initialising\n", __func__);74747575 switch (cpu_has_pvr()) {7676 case 0:7777- printk(KERN_WARNING7878- "%s: No PVR support. Using static CPU info from FDT\n",7777+ pr_warn("%s: No PVR support. Using static CPU info from FDT\n",7978 __func__);8079 set_cpuinfo_static(&cpuinfo, cpu);8180 break;8281/* FIXME I found weird behavior with MB 7.00.a/b 7.10.a8382 * please do not use FULL PVR with MMU */8483 case 1:8585- printk(KERN_INFO "%s: Using full CPU PVR support\n",8484+ pr_info("%s: Using full CPU PVR support\n",8685 __func__);8786 set_cpuinfo_static(&cpuinfo, cpu);8887 set_cpuinfo_pvr_full(&cpuinfo, cpu);8988 break;9089 default:9191- printk(KERN_WARNING "%s: Unsupported PVR setting\n", __func__);9090+ pr_warn("%s: Unsupported PVR setting\n", __func__);9291 set_cpuinfo_static(&cpuinfo, cpu);9392 }94939594 if (cpuinfo.mmu_privins)9696- printk(KERN_WARNING "%s: Stream instructions enabled"9595+ pr_warn("%s: Stream instructions enabled"9796 " - USERSPACE CAN LOCK THIS KERNEL!\n", __func__);9897}
···4040#include <asm/asm-offsets.h>4141#include <asm/cacheflush.h>4242#include <asm/syscall.h>4343-#include <asm/io.h>4343+#include <linux/io.h>44444545/* Returns the address where the register at REG_OFFS in P is stashed away. */4646static microblaze_reg_t *reg_save_addr(unsigned reg_offs,
+15-13
arch/microblaze/kernel/setup.c
···150150 /* printk("TLB1 0x%08x, TLB0 0x%08x, tlb 0x%x\n", tlb0,151151 tlb1, kernel_tlb); */152152153153- printk("Ramdisk addr 0x%08x, ", ram);153153+ pr_info("Ramdisk addr 0x%08x, ", ram);154154 if (fdt)155155- printk("FDT at 0x%08x\n", fdt);155155+ pr_info("FDT at 0x%08x\n", fdt);156156 else157157- printk("Compiled-in FDT at 0x%08x\n",157157+ pr_info("Compiled-in FDT at 0x%08x\n",158158 (unsigned int)_fdt_start);159159160160#ifdef CONFIG_MTD_UCLINUX161161- printk("Found romfs @ 0x%08x (0x%08x)\n",161161+ pr_info("Found romfs @ 0x%08x (0x%08x)\n",162162 romfs_base, romfs_size);163163- printk("#### klimit %p ####\n", old_klimit);163163+ pr_info("#### klimit %p ####\n", old_klimit);164164 BUG_ON(romfs_size < 0); /* What else can we do? */165165166166- printk("Moved 0x%08x bytes from 0x%08x to 0x%08x\n",166166+ pr_info("Moved 0x%08x bytes from 0x%08x to 0x%08x\n",167167 romfs_size, romfs_base, (unsigned)&__bss_stop);168168169169- printk("New klimit: 0x%08x\n", (unsigned)klimit);169169+ pr_info("New klimit: 0x%08x\n", (unsigned)klimit);170170#endif171171172172#if CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR173173- if (msr)174174- printk("!!!Your kernel has setup MSR instruction but "175175- "CPU don't have it %x\n", msr);173173+ if (msr) {174174+ pr_info("!!!Your kernel has setup MSR instruction but ");175175+ pr_cont("CPU don't have it %x\n", msr);176176+ }176177#else177177- if (!msr)178178- printk("!!!Your kernel not setup MSR instruction but "179179- "CPU have it %x\n", msr);178178+ if (!msr) {179179+ pr_info("!!!Your kernel not setup MSR instruction but ");180180+ pr_cont"CPU have it %x\n", msr);181181+ }180182#endif181183182184 /* Do not copy reset vectors. offset = 0x2 means skip the first
···3131#include <linux/uaccess.h>3232#include <linux/unistd.h>3333#include <linux/slab.h>3434-3534#include <asm/syscalls.h>36353736asmlinkage long sys_mmap(unsigned long addr, unsigned long len,
···129129130130 for (; c >= 4; c -= 4) {131131 value = *--i_src;132132- *--i_dst = buf_hold | ((value & 0xFFFFFF00)>>8);132132+ *--i_dst = buf_hold |133133+ ((value & 0xFFFFFF00) >> 8);133134 buf_hold = (value & 0xFF) << 24;134135 }135136#endif···156155157156 for (; c >= 4; c -= 4) {158157 value = *--i_src;159159- *--i_dst = buf_hold | ((value & 0xFFFF0000)>>16);158158+ *--i_dst = buf_hold |159159+ ((value & 0xFFFF0000) >> 16);160160 buf_hold = (value & 0xFFFF) << 16;161161 }162162#endif···183181184182 for (; c >= 4; c -= 4) {185183 value = *--i_src;186186- *--i_dst = buf_hold | ((value & 0xFF000000)>> 24);184184+ *--i_dst = buf_hold |185185+ ((value & 0xFF000000) >> 24);187186 buf_hold = (value & 0xFFFFFF) << 8;188187 }189188#endif
+2-3
arch/microblaze/mm/consistent.c
···3737#include <asm/pgalloc.h>3838#include <linux/io.h>3939#include <linux/hardirq.h>4040-#include <asm/mmu_context.h>4040+#include <linux/mmu_context.h>4141#include <asm/mmu.h>4242#include <linux/uaccess.h>4343#include <asm/pgtable.h>···102102# endif103103 if ((unsigned int)ret > cpuinfo.dcache_base &&104104 (unsigned int)ret < cpuinfo.dcache_high)105105- printk(KERN_WARNING106106- "ERROR: Your cache coherent area is CACHED!!!\n");105105+ pr_warn("ERROR: Your cache coherent area is CACHED!!!\n");107106108107 /* dma_handle is same as physical (shadowed) address */109108 *dma_handle = (dma_addr_t)ret;
+5-5
arch/microblaze/mm/fault.c
···3232#include <asm/page.h>3333#include <asm/pgtable.h>3434#include <asm/mmu.h>3535-#include <asm/mmu_context.h>3535+#include <linux/mmu_context.h>3636#include <linux/uaccess.h>3737#include <asm/exceptions.h>3838···100100101101 /* On a kernel SLB miss we can only check for a valid exception entry */102102 if (unlikely(kernel_mode(regs) && (address >= TASK_SIZE))) {103103- printk(KERN_WARNING "kernel task_size exceed");103103+ pr_warn("kernel task_size exceed");104104 _exception(SIGSEGV, regs, code, address);105105 }106106···114114115115 /* in_atomic() in user mode is really bad,116116 as is current->mm == NULL. */117117- printk(KERN_EMERG "Page fault in user mode with "118118- "in_atomic(), mm = %p\n", mm);119119- printk(KERN_EMERG "r15 = %lx MSR = %lx\n",117117+ pr_emerg("Page fault in user mode with in_atomic(), mm = %p\n",118118+ mm);119119+ pr_emerg("r15 = %lx MSR = %lx\n",120120 regs->r15, regs->msr);121121 die("Weird page fault", regs, SIGSEGV);122122 }