Merge branch 'topic/emu10k1-fix' into for-next

+6 -2

include/sound/emu10k1.h

··· 1692 1692 unsigned int clock_fallback; 1693 1693 unsigned int optical_in; /* 0:SPDIF, 1:ADAT */ 1694 1694 unsigned int optical_out; /* 0:SPDIF, 1:ADAT */ 1695 - struct work_struct firmware_work; 1696 - struct work_struct clock_work; 1695 + struct work_struct work; 1696 + struct mutex lock; 1697 1697 }; 1698 1698 1699 1699 struct snd_emu10k1 { ··· 1842 1842 void snd_emu10k1_ptr20_write(struct snd_emu10k1 *emu, unsigned int reg, unsigned int chn, unsigned int data); 1843 1843 int snd_emu10k1_spi_write(struct snd_emu10k1 * emu, unsigned int data); 1844 1844 int snd_emu10k1_i2c_write(struct snd_emu10k1 *emu, u32 reg, u32 value); 1845 + static inline void snd_emu1010_fpga_lock(struct snd_emu10k1 *emu) { mutex_lock(&emu->emu1010.lock); }; 1846 + static inline void snd_emu1010_fpga_unlock(struct snd_emu10k1 *emu) { mutex_unlock(&emu->emu1010.lock); }; 1847 + void snd_emu1010_fpga_write_lock(struct snd_emu10k1 *emu, u32 reg, u32 value); 1845 1848 void snd_emu1010_fpga_write(struct snd_emu10k1 *emu, u32 reg, u32 value); 1846 1849 void snd_emu1010_fpga_read(struct snd_emu10k1 *emu, u32 reg, u32 *value); 1847 1850 void snd_emu1010_fpga_link_dst_src_write(struct snd_emu10k1 *emu, u32 dst, u32 src); 1848 1851 u32 snd_emu1010_fpga_link_dst_src_read(struct snd_emu10k1 *emu, u32 dst); 1849 1852 int snd_emu1010_get_raw_rate(struct snd_emu10k1 *emu, u8 src); 1850 1853 void snd_emu1010_update_clock(struct snd_emu10k1 *emu); 1854 + void snd_emu1010_load_firmware_entry(struct snd_emu10k1 *emu, int dock, const struct firmware *fw_entry); 1851 1855 unsigned int snd_emu10k1_efx_read(struct snd_emu10k1 *emu, unsigned int pc); 1852 1856 void snd_emu10k1_intr_enable(struct snd_emu10k1 *emu, unsigned int intrenb); 1853 1857 void snd_emu10k1_intr_disable(struct snd_emu10k1 *emu, unsigned int intrenb);

+1 -1

sound/core/seq/seq_ump_convert.c

··· 428 428 midi1->note.group = midi2->note.group; 429 429 midi1->note.status = midi2->note.status; 430 430 midi1->note.channel = midi2->note.channel; 431 - switch (midi2->note.status << 4) { 431 + switch (midi2->note.status) { 432 432 case UMP_MSG_STATUS_NOTE_ON: 433 433 case UMP_MSG_STATUS_NOTE_OFF: 434 434 midi1->note.note = midi2->note.note;

+1 -2

sound/pci/emu10k1/emu10k1.c

··· 189 189 190 190 emu->suspend = 1; 191 191 192 - cancel_work_sync(&emu->emu1010.firmware_work); 193 - cancel_work_sync(&emu->emu1010.clock_work); 192 + cancel_work_sync(&emu->emu1010.work); 194 193 195 194 snd_ac97_suspend(emu->ac97); 196 195

+91 -134

sound/pci/emu10k1/emu10k1_main.c

··· 652 652 return 0; 653 653 } 654 654 655 - static int snd_emu1010_load_firmware_entry(struct snd_emu10k1 *emu, 656 - const struct firmware *fw_entry) 657 - { 658 - int n, i; 659 - u16 reg; 660 - u8 value; 661 - __always_unused u16 write_post; 662 - 663 - if (!fw_entry) 664 - return -EIO; 665 - 666 - /* The FPGA is a Xilinx Spartan IIE XC2S50E */ 667 - /* On E-MU 0404b it is a Xilinx Spartan III XC3S50 */ 668 - /* GPIO7 -> FPGA PGMN 669 - * GPIO6 -> FPGA CCLK 670 - * GPIO5 -> FPGA DIN 671 - * FPGA CONFIG OFF -> FPGA PGMN 672 - */ 673 - spin_lock_irq(&emu->emu_lock); 674 - outw(0x00, emu->port + A_GPIO); /* Set PGMN low for 100uS. */ 675 - write_post = inw(emu->port + A_GPIO); 676 - udelay(100); 677 - outw(0x80, emu->port + A_GPIO); /* Leave bit 7 set during netlist setup. */ 678 - write_post = inw(emu->port + A_GPIO); 679 - udelay(100); /* Allow FPGA memory to clean */ 680 - for (n = 0; n < fw_entry->size; n++) { 681 - value = fw_entry->data[n]; 682 - for (i = 0; i < 8; i++) { 683 - reg = 0x80; 684 - if (value & 0x1) 685 - reg = reg | 0x20; 686 - value = value >> 1; 687 - outw(reg, emu->port + A_GPIO); 688 - write_post = inw(emu->port + A_GPIO); 689 - outw(reg | 0x40, emu->port + A_GPIO); 690 - write_post = inw(emu->port + A_GPIO); 691 - } 692 - } 693 - /* After programming, set GPIO bit 4 high again. */ 694 - outw(0x10, emu->port + A_GPIO); 695 - write_post = inw(emu->port + A_GPIO); 696 - spin_unlock_irq(&emu->emu_lock); 697 - 698 - return 0; 699 - } 700 - 701 655 /* firmware file names, per model, init-fw and dock-fw (optional) */ 702 656 static const char * const firmware_names[5][2] = { 703 657 [EMU_MODEL_EMU1010] = { ··· 683 729 return err; 684 730 } 685 731 686 - return snd_emu1010_load_firmware_entry(emu, *fw); 732 + snd_emu1010_load_firmware_entry(emu, dock, *fw); 733 + return 0; 687 734 } 688 735 689 - static void emu1010_firmware_work(struct work_struct *work) 736 + static void snd_emu1010_load_dock_firmware(struct snd_emu10k1 *emu) 690 737 { 691 - struct snd_emu10k1 *emu; 692 - u32 tmp, tmp2, reg; 738 + u32 tmp, tmp2; 693 739 int err; 694 740 695 - emu = container_of(work, struct snd_emu10k1, 696 - emu1010.firmware_work); 697 - if (emu->card->shutdown) 741 + // The docking events clearly arrive prematurely - while the 742 + // Dock's FPGA seems to be successfully programmed, the Dock 743 + // fails to initialize subsequently if we don't give it some 744 + // time to "warm up" here. 745 + msleep(200); 746 + 747 + dev_info(emu->card->dev, "emu1010: Loading Audio Dock Firmware\n"); 748 + err = snd_emu1010_load_firmware(emu, 1, &emu->dock_fw); 749 + if (err < 0) 698 750 return; 699 - #ifdef CONFIG_PM_SLEEP 700 - if (emu->suspend) 751 + snd_emu1010_fpga_write(emu, EMU_HANA_FPGA_CONFIG, 0); 752 + 753 + snd_emu1010_fpga_read(emu, EMU_HANA_ID, &tmp); 754 + dev_dbg(emu->card->dev, "emu1010: EMU_HANA+DOCK_ID = 0x%x\n", tmp); 755 + if ((tmp & 0x1f) != 0x15) { 756 + /* FPGA failed to be programmed */ 757 + dev_err(emu->card->dev, 758 + "emu1010: Loading Audio Dock Firmware failed, reg = 0x%x\n", 759 + tmp); 701 760 return; 702 - #endif 761 + } 762 + dev_info(emu->card->dev, "emu1010: Audio Dock Firmware loaded\n"); 763 + 764 + snd_emu1010_fpga_read(emu, EMU_DOCK_MAJOR_REV, &tmp); 765 + snd_emu1010_fpga_read(emu, EMU_DOCK_MINOR_REV, &tmp2); 766 + dev_info(emu->card->dev, "Audio Dock ver: %u.%u\n", tmp, tmp2); 767 + 768 + /* Allow DLL to settle, to sync clocking between 1010 and Dock */ 769 + msleep(10); 770 + } 771 + 772 + static void emu1010_dock_event(struct snd_emu10k1 *emu) 773 + { 774 + u32 reg; 775 + 703 776 snd_emu1010_fpga_read(emu, EMU_HANA_OPTION_CARDS, &reg); /* OPTIONS: Which cards are attached to the EMU */ 704 777 if (reg & EMU_HANA_OPTION_DOCK_OFFLINE) { 705 778 /* Audio Dock attached */ 706 - /* Return to Audio Dock programming mode */ 707 - dev_info(emu->card->dev, 708 - "emu1010: Loading Audio Dock Firmware\n"); 709 - snd_emu1010_fpga_write(emu, EMU_HANA_FPGA_CONFIG, 710 - EMU_HANA_FPGA_CONFIG_AUDIODOCK); 711 - err = snd_emu1010_load_firmware(emu, 1, &emu->dock_fw); 712 - if (err < 0) 713 - return; 714 - snd_emu1010_fpga_write(emu, EMU_HANA_FPGA_CONFIG, 0); 715 - snd_emu1010_fpga_read(emu, EMU_HANA_ID, &tmp); 716 - dev_info(emu->card->dev, 717 - "emu1010: EMU_HANA+DOCK_ID = 0x%x\n", tmp); 718 - if ((tmp & 0x1f) != 0x15) { 719 - /* FPGA failed to be programmed */ 720 - dev_info(emu->card->dev, 721 - "emu1010: Loading Audio Dock Firmware file failed, reg = 0x%x\n", 722 - tmp); 723 - return; 724 - } 725 - dev_info(emu->card->dev, 726 - "emu1010: Audio Dock Firmware loaded\n"); 727 - snd_emu1010_fpga_read(emu, EMU_DOCK_MAJOR_REV, &tmp); 728 - snd_emu1010_fpga_read(emu, EMU_DOCK_MINOR_REV, &tmp2); 729 - dev_info(emu->card->dev, "Audio Dock ver: %u.%u\n", tmp, tmp2); 730 - /* Sync clocking between 1010 and Dock */ 731 - /* Allow DLL to settle */ 732 - msleep(10); 779 + snd_emu1010_load_dock_firmware(emu); 733 780 /* Unmute all. Default is muted after a firmware load */ 781 + snd_emu1010_fpga_write(emu, EMU_HANA_UNMUTE, EMU_UNMUTE); 782 + } else if (!(reg & EMU_HANA_OPTION_DOCK_ONLINE)) { 783 + /* Audio Dock removed */ 784 + dev_info(emu->card->dev, "emu1010: Audio Dock detached\n"); 785 + /* The hardware auto-mutes all, so we unmute again */ 734 786 snd_emu1010_fpga_write(emu, EMU_HANA_UNMUTE, EMU_UNMUTE); 735 787 } 736 788 } 737 789 738 - static void emu1010_clock_work(struct work_struct *work) 790 + static void emu1010_clock_event(struct snd_emu10k1 *emu) 739 791 { 740 - struct snd_emu10k1 *emu; 741 792 struct snd_ctl_elem_id id; 742 - 743 - emu = container_of(work, struct snd_emu10k1, 744 - emu1010.clock_work); 745 - if (emu->card->shutdown) 746 - return; 747 - #ifdef CONFIG_PM_SLEEP 748 - if (emu->suspend) 749 - return; 750 - #endif 751 793 752 794 spin_lock_irq(&emu->reg_lock); 753 795 // This is the only thing that can actually happen. ··· 755 805 snd_ctl_notify(emu->card, SNDRV_CTL_EVENT_MASK_VALUE, &id); 756 806 } 757 807 758 - static void emu1010_interrupt(struct snd_emu10k1 *emu) 808 + static void emu1010_work(struct work_struct *work) 759 809 { 810 + struct snd_emu10k1 *emu; 760 811 u32 sts; 761 812 813 + emu = container_of(work, struct snd_emu10k1, emu1010.work); 814 + if (emu->card->shutdown) 815 + return; 816 + #ifdef CONFIG_PM_SLEEP 817 + if (emu->suspend) 818 + return; 819 + #endif 820 + 821 + snd_emu1010_fpga_lock(emu); 822 + 762 823 snd_emu1010_fpga_read(emu, EMU_HANA_IRQ_STATUS, &sts); 763 - if (sts & EMU_HANA_IRQ_DOCK_LOST) { 764 - /* Audio Dock removed */ 765 - dev_info(emu->card->dev, "emu1010: Audio Dock detached\n"); 766 - /* The hardware auto-mutes all, so we unmute again */ 767 - snd_emu1010_fpga_write(emu, EMU_HANA_UNMUTE, EMU_UNMUTE); 768 - } else if (sts & EMU_HANA_IRQ_DOCK) { 769 - schedule_work(&emu->emu1010.firmware_work); 770 - } 824 + 825 + // The distinction of the IRQ status bits is unreliable, 826 + // so we dispatch later based on option card status. 827 + if (sts & (EMU_HANA_IRQ_DOCK | EMU_HANA_IRQ_DOCK_LOST)) 828 + emu1010_dock_event(emu); 829 + 771 830 if (sts & EMU_HANA_IRQ_WCLK_CHANGED) 772 - schedule_work(&emu->emu1010.clock_work); 831 + emu1010_clock_event(emu); 832 + 833 + snd_emu1010_fpga_unlock(emu); 834 + } 835 + 836 + static void emu1010_interrupt(struct snd_emu10k1 *emu) 837 + { 838 + // We get an interrupt on each GPIO input pin change, but we 839 + // care only about the ones triggered by the dedicated pin. 840 + u16 sts = inw(emu->port + A_GPIO); 841 + u16 bit = emu->card_capabilities->ca0108_chip ? 0x2000 : 0x8000; 842 + if (!(sts & bit)) 843 + return; 844 + 845 + schedule_work(&emu->emu1010.work); 773 846 } 774 847 775 848 /* ··· 814 841 * Proper init follows in snd_emu10k1_init(). */ 815 842 outl(HCFG_LOCKSOUNDCACHE | HCFG_LOCKTANKCACHE_MASK, emu->port + HCFG); 816 843 817 - /* Disable 48Volt power to Audio Dock */ 818 - snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_PWR, 0); 844 + snd_emu1010_fpga_lock(emu); 819 845 820 - /* ID, should read & 0x7f = 0x55. (Bit 7 is the IRQ bit) */ 821 - snd_emu1010_fpga_read(emu, EMU_HANA_ID, &reg); 822 - dev_dbg(emu->card->dev, "reg1 = 0x%x\n", reg); 823 - if ((reg & 0x3f) == 0x15) { 824 - /* FPGA netlist already present so clear it */ 825 - /* Return to programming mode */ 826 - 827 - snd_emu1010_fpga_write(emu, EMU_HANA_FPGA_CONFIG, EMU_HANA_FPGA_CONFIG_HANA); 828 - } 829 - snd_emu1010_fpga_read(emu, EMU_HANA_ID, &reg); 830 - dev_dbg(emu->card->dev, "reg2 = 0x%x\n", reg); 831 - if ((reg & 0x3f) == 0x15) { 832 - /* FPGA failed to return to programming mode */ 833 - dev_info(emu->card->dev, 834 - "emu1010: FPGA failed to return to programming mode\n"); 835 - return -ENODEV; 836 - } 837 - dev_info(emu->card->dev, "emu1010: EMU_HANA_ID = 0x%x\n", reg); 838 - 846 + dev_info(emu->card->dev, "emu1010: Loading Hana Firmware\n"); 839 847 err = snd_emu1010_load_firmware(emu, 0, &emu->firmware); 840 848 if (err < 0) { 841 849 dev_info(emu->card->dev, "emu1010: Loading Firmware failed\n"); 842 - return err; 850 + goto fail; 843 851 } 844 852 845 853 /* ID, should read & 0x7f = 0x55 when FPGA programmed. */ ··· 830 876 dev_info(emu->card->dev, 831 877 "emu1010: Loading Hana Firmware file failed, reg = 0x%x\n", 832 878 reg); 833 - return -ENODEV; 879 + err = -ENODEV; 880 + goto fail; 834 881 } 835 882 836 883 dev_info(emu->card->dev, "emu1010: Hana Firmware loaded\n"); ··· 844 889 snd_emu1010_fpga_read(emu, EMU_HANA_OPTION_CARDS, &reg); 845 890 dev_info(emu->card->dev, "emu1010: Card options = 0x%x\n", reg); 846 891 if (reg & EMU_HANA_OPTION_DOCK_OFFLINE) 847 - schedule_work(&emu->emu1010.firmware_work); 892 + snd_emu1010_load_dock_firmware(emu); 848 893 if (emu->card_capabilities->no_adat) { 849 894 emu->emu1010.optical_in = 0; /* IN_SPDIF */ 850 895 emu->emu1010.optical_out = 0; /* OUT_SPDIF */ ··· 891 936 // so it is safe to simply enable the outputs. 892 937 snd_emu1010_fpga_write(emu, EMU_HANA_UNMUTE, EMU_UNMUTE); 893 938 894 - return 0; 939 + fail: 940 + snd_emu1010_fpga_unlock(emu); 941 + return err; 895 942 } 896 943 /* 897 944 * Create the EMU10K1 instance ··· 915 958 } 916 959 if (emu->card_capabilities->emu_model == EMU_MODEL_EMU1010) { 917 960 /* Disable 48Volt power to Audio Dock */ 918 - snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_PWR, 0); 961 + snd_emu1010_fpga_write_lock(emu, EMU_HANA_DOCK_PWR, 0); 919 962 } 920 - cancel_work_sync(&emu->emu1010.firmware_work); 921 - cancel_work_sync(&emu->emu1010.clock_work); 963 + cancel_work_sync(&emu->emu1010.work); 964 + mutex_destroy(&emu->emu1010.lock); 922 965 release_firmware(emu->firmware); 923 966 release_firmware(emu->dock_fw); 924 967 snd_util_memhdr_free(emu->memhdr); ··· 1497 1540 emu->irq = -1; 1498 1541 emu->synth = NULL; 1499 1542 emu->get_synth_voice = NULL; 1500 - INIT_WORK(&emu->emu1010.firmware_work, emu1010_firmware_work); 1501 - INIT_WORK(&emu->emu1010.clock_work, emu1010_clock_work); 1543 + INIT_WORK(&emu->emu1010.work, emu1010_work); 1544 + mutex_init(&emu->emu1010.lock); 1502 1545 /* read revision & serial */ 1503 1546 emu->revision = pci->revision; 1504 1547 pci_read_config_dword(pci, PCI_SUBSYSTEM_VENDOR_ID, &emu->serial);

+13 -5

sound/pci/emu10k1/emumixer.c

··· 661 661 change = (emu->emu1010.output_source[channel] != val); 662 662 if (change) { 663 663 emu->emu1010.output_source[channel] = val; 664 + snd_emu1010_fpga_lock(emu); 664 665 snd_emu1010_output_source_apply(emu, channel, val); 666 + snd_emu1010_fpga_unlock(emu); 665 667 } 666 668 return change; 667 669 } ··· 707 705 change = (emu->emu1010.input_source[channel] != val); 708 706 if (change) { 709 707 emu->emu1010.input_source[channel] = val; 708 + snd_emu1010_fpga_lock(emu); 710 709 snd_emu1010_input_source_apply(emu, channel, val); 710 + snd_emu1010_fpga_unlock(emu); 711 711 } 712 712 return change; 713 713 } ··· 778 774 cache = cache & ~mask; 779 775 change = (cache != emu->emu1010.adc_pads); 780 776 if (change) { 781 - snd_emu1010_fpga_write(emu, EMU_HANA_ADC_PADS, cache ); 777 + snd_emu1010_fpga_write_lock(emu, EMU_HANA_ADC_PADS, cache ); 782 778 emu->emu1010.adc_pads = cache; 783 779 } 784 780 ··· 836 832 cache = cache & ~mask; 837 833 change = (cache != emu->emu1010.dac_pads); 838 834 if (change) { 839 - snd_emu1010_fpga_write(emu, EMU_HANA_DAC_PADS, cache ); 835 + snd_emu1010_fpga_write_lock(emu, EMU_HANA_DAC_PADS, cache ); 840 836 emu->emu1010.dac_pads = cache; 841 837 } 842 838 ··· 984 980 val = ucontrol->value.enumerated.item[0] ; 985 981 if (val >= emu_ci->num) 986 982 return -EINVAL; 983 + snd_emu1010_fpga_lock(emu); 987 984 spin_lock_irq(&emu->reg_lock); 988 985 change = (emu->emu1010.clock_source != val); 989 986 if (change) { ··· 1001 996 } else { 1002 997 spin_unlock_irq(&emu->reg_lock); 1003 998 } 999 + snd_emu1010_fpga_unlock(emu); 1004 1000 return change; 1005 1001 } 1006 1002 ··· 1047 1041 change = (emu->emu1010.clock_fallback != val); 1048 1042 if (change) { 1049 1043 emu->emu1010.clock_fallback = val; 1050 - snd_emu1010_fpga_write(emu, EMU_HANA_DEFCLOCK, 1 - val); 1044 + snd_emu1010_fpga_write_lock(emu, EMU_HANA_DEFCLOCK, 1 - val); 1051 1045 } 1052 1046 return change; 1053 1047 } ··· 1099 1093 emu->emu1010.optical_out = val; 1100 1094 tmp = (emu->emu1010.optical_in ? EMU_HANA_OPTICAL_IN_ADAT : EMU_HANA_OPTICAL_IN_SPDIF) | 1101 1095 (emu->emu1010.optical_out ? EMU_HANA_OPTICAL_OUT_ADAT : EMU_HANA_OPTICAL_OUT_SPDIF); 1102 - snd_emu1010_fpga_write(emu, EMU_HANA_OPTICAL_TYPE, tmp); 1096 + snd_emu1010_fpga_write_lock(emu, EMU_HANA_OPTICAL_TYPE, tmp); 1103 1097 } 1104 1098 return change; 1105 1099 } ··· 1150 1144 emu->emu1010.optical_in = val; 1151 1145 tmp = (emu->emu1010.optical_in ? EMU_HANA_OPTICAL_IN_ADAT : EMU_HANA_OPTICAL_IN_SPDIF) | 1152 1146 (emu->emu1010.optical_out ? EMU_HANA_OPTICAL_OUT_ADAT : EMU_HANA_OPTICAL_OUT_SPDIF); 1153 - snd_emu1010_fpga_write(emu, EMU_HANA_OPTICAL_TYPE, tmp); 1147 + snd_emu1010_fpga_write_lock(emu, EMU_HANA_OPTICAL_TYPE, tmp); 1154 1148 } 1155 1149 return change; 1156 1150 } ··· 2329 2323 for (i = 0; i < emu_ri->n_outs; i++) 2330 2324 emu->emu1010.output_source[i] = 2331 2325 emu1010_map_source(emu_ri, emu_ri->out_dflts[i]); 2326 + snd_emu1010_fpga_lock(emu); 2332 2327 snd_emu1010_apply_sources(emu); 2328 + snd_emu1010_fpga_unlock(emu); 2333 2329 2334 2330 kctl = emu->ctl_clock_source = snd_ctl_new1(&snd_emu1010_clock_source, emu); 2335 2331 err = snd_ctl_add(card, kctl);

+9

sound/pci/emu10k1/emuproc.c

··· 165 165 u32 value2; 166 166 167 167 if (emu->card_capabilities->emu_model) { 168 + snd_emu1010_fpga_lock(emu); 169 + 168 170 // This represents the S/PDIF lock status on 0404b, which is 169 171 // kinda weird and unhelpful, because monitoring it via IRQ is 170 172 // impractical (one gets an IRQ flood as long as it is desynced). ··· 199 197 snd_iprintf(buffer, "\nS/PDIF mode: %s%s\n", 200 198 value & EMU_HANA_SPDIF_MODE_RX_PRO ? "professional" : "consumer", 201 199 value & EMU_HANA_SPDIF_MODE_RX_NOCOPY ? ", no copy" : ""); 200 + 201 + snd_emu1010_fpga_unlock(emu); 202 202 } else { 203 203 snd_emu10k1_proc_spdif_status(emu, buffer, "CD-ROM S/PDIF In", CDCS, CDSRCS); 204 204 snd_emu10k1_proc_spdif_status(emu, buffer, "Optical or Coax S/PDIF In", GPSCS, GPSRCS); ··· 462 458 struct snd_emu10k1 *emu = entry->private_data; 463 459 u32 value; 464 460 int i; 461 + 462 + snd_emu1010_fpga_lock(emu); 463 + 465 464 snd_iprintf(buffer, "EMU1010 Registers:\n\n"); 466 465 467 466 for(i = 0; i < 0x40; i+=1) { ··· 503 496 snd_emu_proc_emu1010_link_read(emu, buffer, 0x701); 504 497 } 505 498 } 499 + 500 + snd_emu1010_fpga_unlock(emu); 506 501 } 507 502 508 503 static void snd_emu_proc_io_reg_read(struct snd_info_entry *entry,

+75 -29

sound/pci/emu10k1/io.c

··· 285 285 outw(value, emu->port + A_GPIO); 286 286 udelay(10); 287 287 outw(value | 0x80 , emu->port + A_GPIO); /* High bit clocks the value into the fpga. */ 288 + udelay(10); 288 289 } 289 290 290 291 void snd_emu1010_fpga_write(struct snd_emu10k1 *emu, u32 reg, u32 value) 291 292 { 292 - unsigned long flags; 293 - 294 - spin_lock_irqsave(&emu->emu_lock, flags); 293 + if (snd_BUG_ON(!mutex_is_locked(&emu->emu1010.lock))) 294 + return; 295 295 snd_emu1010_fpga_write_locked(emu, reg, value); 296 - spin_unlock_irqrestore(&emu->emu_lock, flags); 297 296 } 298 297 299 - static void snd_emu1010_fpga_read_locked(struct snd_emu10k1 *emu, u32 reg, u32 *value) 298 + void snd_emu1010_fpga_write_lock(struct snd_emu10k1 *emu, u32 reg, u32 value) 299 + { 300 + snd_emu1010_fpga_lock(emu); 301 + snd_emu1010_fpga_write_locked(emu, reg, value); 302 + snd_emu1010_fpga_unlock(emu); 303 + } 304 + 305 + void snd_emu1010_fpga_read(struct snd_emu10k1 *emu, u32 reg, u32 *value) 300 306 { 301 307 // The higest input pin is used as the designated interrupt trigger, 302 308 // so it needs to be masked out. 303 309 // But note that any other input pin change will also cause an IRQ, 304 310 // so using this function often causes an IRQ as a side effect. 305 311 u32 mask = emu->card_capabilities->ca0108_chip ? 0x1f : 0x7f; 312 + 313 + if (snd_BUG_ON(!mutex_is_locked(&emu->emu1010.lock))) 314 + return; 306 315 if (snd_BUG_ON(reg > 0x3f)) 307 316 return; 308 317 reg += 0x40; /* 0x40 upwards are registers. */ ··· 322 313 *value = ((inw(emu->port + A_GPIO) >> 8) & mask); 323 314 } 324 315 325 - void snd_emu1010_fpga_read(struct snd_emu10k1 *emu, u32 reg, u32 *value) 326 - { 327 - unsigned long flags; 328 - 329 - spin_lock_irqsave(&emu->emu_lock, flags); 330 - snd_emu1010_fpga_read_locked(emu, reg, value); 331 - spin_unlock_irqrestore(&emu->emu_lock, flags); 332 - } 333 - 334 316 /* Each Destination has one and only one Source, 335 317 * but one Source can feed any number of Destinations simultaneously. 336 318 */ 337 319 void snd_emu1010_fpga_link_dst_src_write(struct snd_emu10k1 *emu, u32 dst, u32 src) 338 320 { 339 - unsigned long flags; 340 - 341 321 if (snd_BUG_ON(dst & ~0x71f)) 342 322 return; 343 323 if (snd_BUG_ON(src & ~0x71f)) 344 324 return; 345 - spin_lock_irqsave(&emu->emu_lock, flags); 346 - snd_emu1010_fpga_write_locked(emu, EMU_HANA_DESTHI, dst >> 8); 347 - snd_emu1010_fpga_write_locked(emu, EMU_HANA_DESTLO, dst & 0x1f); 348 - snd_emu1010_fpga_write_locked(emu, EMU_HANA_SRCHI, src >> 8); 349 - snd_emu1010_fpga_write_locked(emu, EMU_HANA_SRCLO, src & 0x1f); 350 - spin_unlock_irqrestore(&emu->emu_lock, flags); 325 + snd_emu1010_fpga_write(emu, EMU_HANA_DESTHI, dst >> 8); 326 + snd_emu1010_fpga_write(emu, EMU_HANA_DESTLO, dst & 0x1f); 327 + snd_emu1010_fpga_write(emu, EMU_HANA_SRCHI, src >> 8); 328 + snd_emu1010_fpga_write(emu, EMU_HANA_SRCLO, src & 0x1f); 351 329 } 352 330 353 331 u32 snd_emu1010_fpga_link_dst_src_read(struct snd_emu10k1 *emu, u32 dst) 354 332 { 355 - unsigned long flags; 356 333 u32 hi, lo; 357 334 358 335 if (snd_BUG_ON(dst & ~0x71f)) 359 336 return 0; 360 - spin_lock_irqsave(&emu->emu_lock, flags); 361 - snd_emu1010_fpga_write_locked(emu, EMU_HANA_DESTHI, dst >> 8); 362 - snd_emu1010_fpga_write_locked(emu, EMU_HANA_DESTLO, dst & 0x1f); 363 - snd_emu1010_fpga_read_locked(emu, EMU_HANA_SRCHI, &hi); 364 - snd_emu1010_fpga_read_locked(emu, EMU_HANA_SRCLO, &lo); 365 - spin_unlock_irqrestore(&emu->emu_lock, flags); 337 + snd_emu1010_fpga_write(emu, EMU_HANA_DESTHI, dst >> 8); 338 + snd_emu1010_fpga_write(emu, EMU_HANA_DESTLO, dst & 0x1f); 339 + snd_emu1010_fpga_read(emu, EMU_HANA_SRCHI, &hi); 340 + snd_emu1010_fpga_read(emu, EMU_HANA_SRCLO, &lo); 366 341 return (hi << 8) | lo; 367 342 } 368 343 ··· 420 427 leds |= EMU_HANA_DOCK_LEDS_2_LOCK; 421 428 422 429 snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_LEDS_2, leds); 430 + } 431 + 432 + void snd_emu1010_load_firmware_entry(struct snd_emu10k1 *emu, int dock, 433 + const struct firmware *fw_entry) 434 + { 435 + __always_unused u16 write_post; 436 + 437 + // On E-MU 1010 rev1 the FPGA is a Xilinx Spartan IIE XC2S50E. 438 + // On E-MU 0404b it is a Xilinx Spartan III XC3S50. 439 + // The wiring is as follows: 440 + // GPO7 -> FPGA input & 1K resistor -> FPGA /PGMN <- FPGA output 441 + // In normal operation, the active low reset line is held up by 442 + // an FPGA output, while the GPO pin performs its duty as control 443 + // register access strobe signal. Writing the respective bit to 444 + // EMU_HANA_FPGA_CONFIG puts the FPGA output into high-Z mode, at 445 + // which point the GPO pin can control the reset line through the 446 + // resistor. 447 + // GPO6 -> FPGA CCLK & FPGA input 448 + // GPO5 -> FPGA DIN (dual function) 449 + 450 + // If the FPGA is already programmed, return it to programming mode 451 + snd_emu1010_fpga_write(emu, EMU_HANA_FPGA_CONFIG, 452 + dock ? EMU_HANA_FPGA_CONFIG_AUDIODOCK : 453 + EMU_HANA_FPGA_CONFIG_HANA); 454 + 455 + // Assert reset line for 100uS 456 + outw(0x00, emu->port + A_GPIO); 457 + write_post = inw(emu->port + A_GPIO); 458 + udelay(100); 459 + outw(0x80, emu->port + A_GPIO); 460 + write_post = inw(emu->port + A_GPIO); 461 + udelay(100); // Allow FPGA memory to clean 462 + 463 + // Upload the netlist. Keep reset line high! 464 + for (int n = 0; n < fw_entry->size; n++) { 465 + u8 value = fw_entry->data[n]; 466 + for (int i = 0; i < 8; i++) { 467 + u16 reg = 0x80; 468 + if (value & 1) 469 + reg |= 0x20; 470 + value >>= 1; 471 + outw(reg, emu->port + A_GPIO); 472 + write_post = inw(emu->port + A_GPIO); 473 + outw(reg | 0x40, emu->port + A_GPIO); 474 + write_post = inw(emu->port + A_GPIO); 475 + } 476 + } 477 + 478 + // After programming, set GPIO bit 4 high again. 479 + // This appears to be a config word that the rev1 Hana 480 + // firmware reads; weird things happen without this. 481 + outw(0x10, emu->port + A_GPIO); 482 + write_post = inw(emu->port + A_GPIO); 423 483 } 424 484 425 485 void snd_emu10k1_intr_enable(struct snd_emu10k1 *emu, unsigned int intrenb)

+43 -4

sound/pci/hda/patch_realtek.c

··· 7467 7467 ALC285_FIXUP_CS35L56_I2C_2, 7468 7468 ALC285_FIXUP_CS35L56_I2C_4, 7469 7469 ALC285_FIXUP_ASUS_GA403U, 7470 + ALC285_FIXUP_ASUS_GA403U_HEADSET_MIC, 7471 + ALC285_FIXUP_ASUS_GA403U_I2C_SPEAKER2_TO_DAC1, 7472 + ALC285_FIXUP_ASUS_GU605_SPI_2_HEADSET_MIC, 7473 + ALC285_FIXUP_ASUS_GU605_SPI_SPEAKER2_TO_DAC1 7470 7474 }; 7471 7475 7472 7476 /* A special fixup for Lenovo C940 and Yoga Duet 7; ··· 9694 9690 .type = HDA_FIXUP_FUNC, 9695 9691 .v.func = alc285_fixup_asus_ga403u, 9696 9692 }, 9693 + [ALC285_FIXUP_ASUS_GA403U_HEADSET_MIC] = { 9694 + .type = HDA_FIXUP_PINS, 9695 + .v.pins = (const struct hda_pintbl[]) { 9696 + { 0x19, 0x03a11050 }, 9697 + { 0x1b, 0x03a11c30 }, 9698 + { } 9699 + }, 9700 + .chained = true, 9701 + .chain_id = ALC285_FIXUP_ASUS_GA403U_I2C_SPEAKER2_TO_DAC1 9702 + }, 9703 + [ALC285_FIXUP_ASUS_GU605_SPI_SPEAKER2_TO_DAC1] = { 9704 + .type = HDA_FIXUP_FUNC, 9705 + .v.func = alc285_fixup_speaker2_to_dac1, 9706 + .chained = true, 9707 + .chain_id = ALC285_FIXUP_ASUS_GU605_SPI_2_HEADSET_MIC, 9708 + }, 9709 + [ALC285_FIXUP_ASUS_GU605_SPI_2_HEADSET_MIC] = { 9710 + .type = HDA_FIXUP_PINS, 9711 + .v.pins = (const struct hda_pintbl[]) { 9712 + { 0x19, 0x03a11050 }, 9713 + { 0x1b, 0x03a11c30 }, 9714 + { } 9715 + }, 9716 + .chained = true, 9717 + .chain_id = ALC285_FIXUP_CS35L56_SPI_2 9718 + }, 9719 + [ALC285_FIXUP_ASUS_GA403U_I2C_SPEAKER2_TO_DAC1] = { 9720 + .type = HDA_FIXUP_FUNC, 9721 + .v.func = alc285_fixup_speaker2_to_dac1, 9722 + .chained = true, 9723 + .chain_id = ALC285_FIXUP_ASUS_GA403U, 9724 + }, 9697 9725 }; 9698 9726 9699 9727 static const struct snd_pci_quirk alc269_fixup_tbl[] = { ··· 10185 10149 SND_PCI_QUIRK(0x1043, 0x1a83, "ASUS UM5302LA", ALC294_FIXUP_CS35L41_I2C_2), 10186 10150 SND_PCI_QUIRK(0x1043, 0x1a8f, "ASUS UX582ZS", ALC245_FIXUP_CS35L41_SPI_2), 10187 10151 SND_PCI_QUIRK(0x1043, 0x1b11, "ASUS UX431DA", ALC294_FIXUP_ASUS_COEF_1B), 10188 - SND_PCI_QUIRK(0x1043, 0x1b13, "ASUS U41SV/GA403U", ALC285_FIXUP_ASUS_GA403U), 10152 + SND_PCI_QUIRK(0x1043, 0x1b13, "ASUS U41SV/GA403U", ALC285_FIXUP_ASUS_GA403U_HEADSET_MIC), 10189 10153 SND_PCI_QUIRK(0x1043, 0x1b93, "ASUS G614JVR/JIR", ALC245_FIXUP_CS35L41_SPI_2), 10190 10154 SND_PCI_QUIRK(0x1043, 0x1bbd, "ASUS Z550MA", ALC255_FIXUP_ASUS_MIC_NO_PRESENCE), 10191 10155 SND_PCI_QUIRK(0x1043, 0x1c03, "ASUS UM3406HA", ALC287_FIXUP_CS35L41_I2C_2), ··· 10193 10157 SND_PCI_QUIRK(0x1043, 0x1c33, "ASUS UX5304MA", ALC245_FIXUP_CS35L41_SPI_2), 10194 10158 SND_PCI_QUIRK(0x1043, 0x1c43, "ASUS UX8406MA", ALC245_FIXUP_CS35L41_SPI_2), 10195 10159 SND_PCI_QUIRK(0x1043, 0x1c62, "ASUS GU603", ALC289_FIXUP_ASUS_GA401), 10196 - SND_PCI_QUIRK(0x1043, 0x1c63, "ASUS GU605M", ALC285_FIXUP_CS35L56_SPI_2), 10160 + SND_PCI_QUIRK(0x1043, 0x1c63, "ASUS GU605M", ALC285_FIXUP_ASUS_GU605_SPI_SPEAKER2_TO_DAC1), 10197 10161 SND_PCI_QUIRK(0x1043, 0x1c92, "ASUS ROG Strix G15", ALC285_FIXUP_ASUS_G533Z_PINS), 10198 10162 SND_PCI_QUIRK(0x1043, 0x1c9f, "ASUS G614JU/JV/JI", ALC285_FIXUP_ASUS_HEADSET_MIC), 10199 10163 SND_PCI_QUIRK(0x1043, 0x1caf, "ASUS G634JY/JZ/JI/JG", ALC285_FIXUP_ASUS_SPI_REAR_SPEAKERS), ··· 10270 10234 SND_PCI_QUIRK(0x1462, 0xb120, "MSI Cubi MS-B120", ALC283_FIXUP_HEADSET_MIC), 10271 10235 SND_PCI_QUIRK(0x1462, 0xb171, "Cubi N 8GL (MS-B171)", ALC283_FIXUP_HEADSET_MIC), 10272 10236 SND_PCI_QUIRK(0x152d, 0x1082, "Quanta NL3", ALC269_FIXUP_LIFEBOOK), 10237 + SND_PCI_QUIRK(0x152d, 0x1262, "Huawei NBLB-WAX9N", ALC2XX_FIXUP_HEADSET_MIC), 10273 10238 SND_PCI_QUIRK(0x1558, 0x0353, "Clevo V35[05]SN[CDE]Q", ALC256_FIXUP_SYSTEM76_MIC_NO_PRESENCE), 10274 10239 SND_PCI_QUIRK(0x1558, 0x1323, "Clevo N130ZU", ALC293_FIXUP_SYSTEM76_MIC_NO_PRESENCE), 10275 10240 SND_PCI_QUIRK(0x1558, 0x1325, "Clevo N15[01][CW]U", ALC293_FIXUP_SYSTEM76_MIC_NO_PRESENCE), ··· 10376 10339 SND_PCI_QUIRK(0x17aa, 0x222e, "Thinkpad", ALC298_FIXUP_TPT470_DOCK), 10377 10340 SND_PCI_QUIRK(0x17aa, 0x2231, "Thinkpad T560", ALC292_FIXUP_TPT460), 10378 10341 SND_PCI_QUIRK(0x17aa, 0x2233, "Thinkpad", ALC292_FIXUP_TPT460), 10342 + SND_PCI_QUIRK(0x17aa, 0x2234, "Thinkpad ICE-1", ALC287_FIXUP_TAS2781_I2C), 10379 10343 SND_PCI_QUIRK(0x17aa, 0x2245, "Thinkpad T470", ALC298_FIXUP_TPT470_DOCK), 10380 10344 SND_PCI_QUIRK(0x17aa, 0x2246, "Thinkpad", ALC298_FIXUP_TPT470_DOCK), 10381 10345 SND_PCI_QUIRK(0x17aa, 0x2247, "Thinkpad", ALC298_FIXUP_TPT470_DOCK), ··· 10440 10402 SND_PCI_QUIRK(0x17aa, 0x3886, "Y780 VECO DUAL", ALC287_FIXUP_TAS2781_I2C), 10441 10403 SND_PCI_QUIRK(0x17aa, 0x38a7, "Y780P AMD YG dual", ALC287_FIXUP_TAS2781_I2C), 10442 10404 SND_PCI_QUIRK(0x17aa, 0x38a8, "Y780P AMD VECO dual", ALC287_FIXUP_TAS2781_I2C), 10443 - SND_PCI_QUIRK(0x17aa, 0x38a9, "Thinkbook 16P", ALC287_FIXUP_CS35L41_I2C_2), 10444 - SND_PCI_QUIRK(0x17aa, 0x38ab, "Thinkbook 16P", ALC287_FIXUP_CS35L41_I2C_2), 10405 + SND_PCI_QUIRK(0x17aa, 0x38a9, "Thinkbook 16P", ALC287_FIXUP_MG_RTKC_CSAMP_CS35L41_I2C_THINKPAD), 10406 + SND_PCI_QUIRK(0x17aa, 0x38ab, "Thinkbook 16P", ALC287_FIXUP_MG_RTKC_CSAMP_CS35L41_I2C_THINKPAD), 10445 10407 SND_PCI_QUIRK(0x17aa, 0x38b4, "Legion Slim 7 16IRH8", ALC287_FIXUP_CS35L41_I2C_2), 10446 10408 SND_PCI_QUIRK(0x17aa, 0x38b5, "Legion Slim 7 16IRH8", ALC287_FIXUP_CS35L41_I2C_2), 10447 10409 SND_PCI_QUIRK(0x17aa, 0x38b6, "Legion Slim 7 16APH8", ALC287_FIXUP_CS35L41_I2C_2), ··· 10503 10465 SND_PCI_QUIRK(0x1d05, 0x115c, "TongFang GMxTGxx", ALC269_FIXUP_NO_SHUTUP), 10504 10466 SND_PCI_QUIRK(0x1d05, 0x121b, "TongFang GMxAGxx", ALC269_FIXUP_NO_SHUTUP), 10505 10467 SND_PCI_QUIRK(0x1d05, 0x1387, "TongFang GMxIXxx", ALC2XX_FIXUP_HEADSET_MIC), 10468 + SND_PCI_QUIRK(0x1d17, 0x3288, "Haier Boyue G42", ALC269VC_FIXUP_ACER_VCOPPERBOX_PINS), 10506 10469 SND_PCI_QUIRK(0x1d72, 0x1602, "RedmiBook", ALC255_FIXUP_XIAOMI_HEADSET_MIC), 10507 10470 SND_PCI_QUIRK(0x1d72, 0x1701, "XiaomiNotebook Pro", ALC298_FIXUP_DELL1_MIC_NO_PRESENCE), 10508 10471 SND_PCI_QUIRK(0x1d72, 0x1901, "RedmiBook 14", ALC256_FIXUP_ASUS_HEADSET_MIC),