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ARM: OMAP: DRA7: powerdomain data: Remove unused pwrsts_mem_ret
As per the latest revision F of public TRM for DRA7/AM57xx SoCs
SPRUHZ6F[1] (April 2016), with the exception of MPU power domain, all
other power domains do not have memories capable of retention since
they all operate in either "ON" or "OFF" mode. For these power states,
the retention state for memories are basically ignored by PRCM and does
not require to be programmed.
[1] http://www.ti.com/lit/pdf/spruhz6
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
authored by
Nishanth Menon
and committed by
Tony Lindgren
6b41d448
9ffb668f
-65
-65
arch/arm/mach-omap2/powerdomains7xx_data.c
-65
arch/arm/mach-omap2/powerdomains7xx_data.c
···
37
37
.prcm_partition = DRA7XX_PRM_PARTITION,
38
38
.pwrsts = PWRSTS_OFF_ON,
39
39
.banks = 4,
40
-
.pwrsts_mem_ret = {
41
-
[0] = PWRSTS_OFF_RET, /* hwa_mem */
42
-
[1] = PWRSTS_OFF_RET, /* sl2_mem */
43
-
[2] = PWRSTS_OFF_RET, /* tcm1_mem */
44
-
[3] = PWRSTS_OFF_RET, /* tcm2_mem */
45
-
},
46
40
.pwrsts_mem_on = {
47
41
[0] = PWRSTS_ON, /* hwa_mem */
48
42
[1] = PWRSTS_ON, /* sl2_mem */
···
70
76
.prcm_partition = DRA7XX_PRM_PARTITION,
71
77
.pwrsts = PWRSTS_OFF_ON,
72
78
.banks = 2,
73
-
.pwrsts_mem_ret = {
74
-
[0] = PWRSTS_OFF_RET, /* aessmem */
75
-
[1] = PWRSTS_OFF_RET, /* periphmem */
76
-
},
77
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.pwrsts_mem_on = {
78
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[0] = PWRSTS_ON, /* aessmem */
79
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[1] = PWRSTS_ON, /* periphmem */
···
84
94
.prcm_partition = DRA7XX_PRM_PARTITION,
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.pwrsts = PWRSTS_OFF_ON,
86
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.banks = 1,
87
-
.pwrsts_mem_ret = {
88
-
[0] = PWRSTS_OFF_RET, /* dss_mem */
89
-
},
90
97
.pwrsts_mem_on = {
91
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[0] = PWRSTS_ON, /* dss_mem */
92
99
},
···
97
110
.prcm_partition = DRA7XX_PRM_PARTITION,
98
111
.pwrsts = PWRSTS_ON,
99
112
.banks = 2,
100
-
.pwrsts_mem_ret = {
101
-
[0] = PWRSTS_OFF_RET, /* nonretained_bank */
102
-
[1] = PWRSTS_OFF_RET, /* retained_bank */
103
-
},
104
113
.pwrsts_mem_on = {
105
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[0] = PWRSTS_ON, /* nonretained_bank */
106
115
[1] = PWRSTS_ON, /* retained_bank */
···
111
128
.prcm_partition = DRA7XX_PRM_PARTITION,
112
129
.pwrsts = PWRSTS_OFF_ON,
113
130
.banks = 1,
114
-
.pwrsts_mem_ret = {
115
-
[0] = PWRSTS_OFF_RET, /* gpu_mem */
116
-
},
117
131
.pwrsts_mem_on = {
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[0] = PWRSTS_ON, /* gpu_mem */
119
133
},
···
124
144
.prcm_partition = DRA7XX_PRM_PARTITION,
125
145
.pwrsts = PWRSTS_ON,
126
146
.banks = 1,
127
-
.pwrsts_mem_ret = {
128
-
},
129
147
.pwrsts_mem_on = {
130
148
[0] = PWRSTS_ON, /* wkup_bank */
131
149
},
···
136
158
.prcm_partition = DRA7XX_PRM_PARTITION,
137
159
.pwrsts = PWRSTS_ON,
138
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.banks = 5,
139
-
.pwrsts_mem_ret = {
140
-
[0] = PWRSTS_OFF_RET, /* core_nret_bank */
141
-
[1] = PWRSTS_OFF_RET, /* core_ocmram */
142
-
[2] = PWRSTS_OFF_RET, /* core_other_bank */
143
-
[3] = PWRSTS_OFF_RET, /* ipu_l2ram */
144
-
[4] = PWRSTS_OFF_RET, /* ipu_unicache */
145
-
},
146
161
.pwrsts_mem_on = {
147
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[0] = PWRSTS_ON, /* core_nret_bank */
148
163
[1] = PWRSTS_ON, /* core_ocmram */
···
193
222
.prcm_partition = DRA7XX_PRM_PARTITION,
194
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.pwrsts = PWRSTS_OFF_ON,
195
224
.banks = 1,
196
-
.pwrsts_mem_ret = {
197
-
[0] = PWRSTS_OFF_RET, /* vpe_bank */
198
-
},
199
225
.pwrsts_mem_on = {
200
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[0] = PWRSTS_ON, /* vpe_bank */
201
227
},
···
224
256
.prcm_partition = DRA7XX_PRM_PARTITION,
225
257
.pwrsts = PWRSTS_ON,
226
258
.banks = 3,
227
-
.pwrsts_mem_ret = {
228
-
[0] = PWRSTS_OFF_RET, /* gmac_bank */
229
-
[1] = PWRSTS_OFF_RET, /* l3init_bank1 */
230
-
[2] = PWRSTS_OFF_RET, /* l3init_bank2 */
231
-
},
232
259
.pwrsts_mem_on = {
233
260
[0] = PWRSTS_ON, /* gmac_bank */
234
261
[1] = PWRSTS_ON, /* l3init_bank1 */
···
239
276
.prcm_partition = DRA7XX_PRM_PARTITION,
240
277
.pwrsts = PWRSTS_OFF_ON,
241
278
.banks = 1,
242
-
.pwrsts_mem_ret = {
243
-
[0] = PWRSTS_OFF_RET, /* eve3_bank */
244
-
},
245
279
.pwrsts_mem_on = {
246
280
[0] = PWRSTS_ON, /* eve3_bank */
247
281
},
···
252
292
.prcm_partition = DRA7XX_PRM_PARTITION,
253
293
.pwrsts = PWRSTS_OFF_ON,
254
294
.banks = 1,
255
-
.pwrsts_mem_ret = {
256
-
[0] = PWRSTS_OFF_RET, /* emu_bank */
257
-
},
258
295
.pwrsts_mem_on = {
259
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[0] = PWRSTS_ON, /* emu_bank */
260
297
},
···
264
307
.prcm_partition = DRA7XX_PRM_PARTITION,
265
308
.pwrsts = PWRSTS_OFF_ON,
266
309
.banks = 3,
267
-
.pwrsts_mem_ret = {
268
-
[0] = PWRSTS_OFF_RET, /* dsp2_edma */
269
-
[1] = PWRSTS_OFF_RET, /* dsp2_l1 */
270
-
[2] = PWRSTS_OFF_RET, /* dsp2_l2 */
271
-
},
272
310
.pwrsts_mem_on = {
273
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[0] = PWRSTS_ON, /* dsp2_edma */
274
312
[1] = PWRSTS_ON, /* dsp2_l1 */
···
279
327
.prcm_partition = DRA7XX_PRM_PARTITION,
280
328
.pwrsts = PWRSTS_OFF_ON,
281
329
.banks = 3,
282
-
.pwrsts_mem_ret = {
283
-
[0] = PWRSTS_OFF_RET, /* dsp1_edma */
284
-
[1] = PWRSTS_OFF_RET, /* dsp1_l1 */
285
-
[2] = PWRSTS_OFF_RET, /* dsp1_l2 */
286
-
},
287
330
.pwrsts_mem_on = {
288
331
[0] = PWRSTS_ON, /* dsp1_edma */
289
332
[1] = PWRSTS_ON, /* dsp1_l1 */
···
294
347
.prcm_partition = DRA7XX_PRM_PARTITION,
295
348
.pwrsts = PWRSTS_OFF_ON,
296
349
.banks = 1,
297
-
.pwrsts_mem_ret = {
298
-
[0] = PWRSTS_OFF_RET, /* vip_bank */
299
-
},
300
350
.pwrsts_mem_on = {
301
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[0] = PWRSTS_ON, /* vip_bank */
302
352
},
···
307
363
.prcm_partition = DRA7XX_PRM_PARTITION,
308
364
.pwrsts = PWRSTS_OFF_ON,
309
365
.banks = 1,
310
-
.pwrsts_mem_ret = {
311
-
[0] = PWRSTS_OFF_RET, /* eve4_bank */
312
-
},
313
366
.pwrsts_mem_on = {
314
367
[0] = PWRSTS_ON, /* eve4_bank */
315
368
},
···
320
379
.prcm_partition = DRA7XX_PRM_PARTITION,
321
380
.pwrsts = PWRSTS_OFF_ON,
322
381
.banks = 1,
323
-
.pwrsts_mem_ret = {
324
-
[0] = PWRSTS_OFF_RET, /* eve2_bank */
325
-
},
326
382
.pwrsts_mem_on = {
327
383
[0] = PWRSTS_ON, /* eve2_bank */
328
384
},
···
333
395
.prcm_partition = DRA7XX_PRM_PARTITION,
334
396
.pwrsts = PWRSTS_OFF_ON,
335
397
.banks = 1,
336
-
.pwrsts_mem_ret = {
337
-
[0] = PWRSTS_OFF_RET, /* eve1_bank */
338
-
},
339
398
.pwrsts_mem_on = {
340
399
[0] = PWRSTS_ON, /* eve1_bank */
341
400
},