Merge tag 'mfd-extcon-regulator-v3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd into extcon-next

+18 -17

drivers/extcon/extcon-max77693.c

··· 255 255 case ADC_DEBOUNCE_TIME_10MS: 256 256 case ADC_DEBOUNCE_TIME_25MS: 257 257 case ADC_DEBOUNCE_TIME_38_62MS: 258 - ret = max77693_update_reg(info->max77693->regmap_muic, 258 + ret = regmap_update_bits(info->max77693->regmap_muic, 259 259 MAX77693_MUIC_REG_CTRL3, 260 - time << CONTROL3_ADCDBSET_SHIFT, 261 - CONTROL3_ADCDBSET_MASK); 260 + CONTROL3_ADCDBSET_MASK, 261 + time << CONTROL3_ADCDBSET_SHIFT); 262 262 if (ret) { 263 263 dev_err(info->dev, "failed to set ADC debounce time\n"); 264 264 return ret; ··· 286 286 u8 val, bool attached) 287 287 { 288 288 int ret = 0; 289 - u8 ctrl1, ctrl2 = 0; 289 + unsigned int ctrl1, ctrl2 = 0; 290 290 291 291 if (attached) 292 292 ctrl1 = val; 293 293 else 294 294 ctrl1 = CONTROL1_SW_OPEN; 295 295 296 - ret = max77693_update_reg(info->max77693->regmap_muic, 297 - MAX77693_MUIC_REG_CTRL1, ctrl1, COMP_SW_MASK); 296 + ret = regmap_update_bits(info->max77693->regmap_muic, 297 + MAX77693_MUIC_REG_CTRL1, COMP_SW_MASK, ctrl1); 298 298 if (ret < 0) { 299 299 dev_err(info->dev, "failed to update MUIC register\n"); 300 300 return ret; ··· 305 305 else 306 306 ctrl2 |= CONTROL2_LOWPWR_MASK; /* LowPwr=1, CPEn=0 */ 307 307 308 - ret = max77693_update_reg(info->max77693->regmap_muic, 309 - MAX77693_MUIC_REG_CTRL2, ctrl2, 310 - CONTROL2_LOWPWR_MASK | CONTROL2_CPEN_MASK); 308 + ret = regmap_update_bits(info->max77693->regmap_muic, 309 + MAX77693_MUIC_REG_CTRL2, 310 + CONTROL2_LOWPWR_MASK | CONTROL2_CPEN_MASK, ctrl2); 311 311 if (ret < 0) { 312 312 dev_err(info->dev, "failed to update MUIC register\n"); 313 313 return ret; ··· 969 969 if (info->irq == muic_irqs[i].virq) 970 970 irq_type = muic_irqs[i].irq; 971 971 972 - ret = max77693_bulk_read(info->max77693->regmap_muic, 973 - MAX77693_MUIC_REG_STATUS1, 2, info->status); 972 + ret = regmap_bulk_read(info->max77693->regmap_muic, 973 + MAX77693_MUIC_REG_STATUS1, info->status, 2); 974 974 if (ret) { 975 975 dev_err(info->dev, "failed to read MUIC register\n"); 976 976 mutex_unlock(&info->mutex); ··· 1042 1042 mutex_lock(&info->mutex); 1043 1043 1044 1044 /* Read STATUSx register to detect accessory */ 1045 - ret = max77693_bulk_read(info->max77693->regmap_muic, 1046 - MAX77693_MUIC_REG_STATUS1, 2, info->status); 1045 + ret = regmap_bulk_read(info->max77693->regmap_muic, 1046 + MAX77693_MUIC_REG_STATUS1, info->status, 2); 1047 1047 if (ret) { 1048 1048 dev_err(info->dev, "failed to read MUIC register\n"); 1049 1049 mutex_unlock(&info->mutex); ··· 1095 1095 int delay_jiffies; 1096 1096 int ret; 1097 1097 int i; 1098 - u8 id; 1098 + unsigned int id; 1099 1099 1100 1100 info = devm_kzalloc(&pdev->dev, sizeof(struct max77693_muic_info), 1101 1101 GFP_KERNEL); ··· 1154 1154 struct max77693_muic_irq *muic_irq = &muic_irqs[i]; 1155 1155 unsigned int virq = 0; 1156 1156 1157 - virq = irq_create_mapping(max77693->irq_domain, muic_irq->irq); 1157 + virq = regmap_irq_get_virq(max77693->irq_data_muic, 1158 + muic_irq->irq); 1158 1159 if (!virq) { 1159 1160 ret = -EINVAL; 1160 1161 goto err_irq; ··· 1204 1203 enum max77693_irq_source irq_src 1205 1204 = MAX77693_IRQ_GROUP_NR; 1206 1205 1207 - max77693_write_reg(info->max77693->regmap_muic, 1206 + regmap_write(info->max77693->regmap_muic, 1208 1207 init_data[i].addr, 1209 1208 init_data[i].data); 1210 1209 ··· 1262 1261 max77693_muic_set_path(info, info->path_uart, true); 1263 1262 1264 1263 /* Check revision number of MUIC device*/ 1265 - ret = max77693_read_reg(info->max77693->regmap_muic, 1264 + ret = regmap_read(info->max77693->regmap_muic, 1266 1265 MAX77693_MUIC_REG_ID, &id); 1267 1266 if (ret < 0) { 1268 1267 dev_err(&pdev->dev, "failed to read revision number\n");

+1

drivers/mfd/Kconfig

··· 384 384 depends on I2C=y 385 385 select MFD_CORE 386 386 select REGMAP_I2C 387 + select REGMAP_IRQ 387 388 help 388 389 Say yes here to add support for Maxim Semiconductor MAX77693. 389 390 This is a companion Power Management IC with Flash, Haptic, Charger,

+1 -1

drivers/mfd/Makefile

··· 116 116 117 117 obj-$(CONFIG_MFD_MAX14577) += max14577.o 118 118 obj-$(CONFIG_MFD_MAX77686) += max77686.o max77686-irq.o 119 - obj-$(CONFIG_MFD_MAX77693) += max77693.o max77693-irq.o 119 + obj-$(CONFIG_MFD_MAX77693) += max77693.o 120 120 obj-$(CONFIG_MFD_MAX8907) += max8907.o 121 121 max8925-objs := max8925-core.o max8925-i2c.o 122 122 obj-$(CONFIG_MFD_MAX8925) += max8925.o

-336

drivers/mfd/max77693-irq.c

··· 1 - /* 2 - * max77693-irq.c - Interrupt controller support for MAX77693 3 - * 4 - * Copyright (C) 2012 Samsung Electronics Co.Ltd 5 - * SangYoung Son <hello.son@samsung.com> 6 - * 7 - * This program is not provided / owned by Maxim Integrated Products. 8 - * 9 - * This program is free software; you can redistribute it and/or modify 10 - * it under the terms of the GNU General Public License as published by 11 - * the Free Software Foundation; either version 2 of the License, or 12 - * (at your option) any later version. 13 - * 14 - * This program is distributed in the hope that it will be useful, 15 - * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 - * GNU General Public License for more details. 18 - * 19 - * You should have received a copy of the GNU General Public License 20 - * along with this program; if not, write to the Free Software 21 - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 22 - * 23 - * This driver is based on max8997-irq.c 24 - */ 25 - 26 - #include <linux/err.h> 27 - #include <linux/irq.h> 28 - #include <linux/interrupt.h> 29 - #include <linux/module.h> 30 - #include <linux/irqdomain.h> 31 - #include <linux/mfd/max77693.h> 32 - #include <linux/mfd/max77693-private.h> 33 - 34 - static const u8 max77693_mask_reg[] = { 35 - [LED_INT] = MAX77693_LED_REG_FLASH_INT_MASK, 36 - [TOPSYS_INT] = MAX77693_PMIC_REG_TOPSYS_INT_MASK, 37 - [CHG_INT] = MAX77693_CHG_REG_CHG_INT_MASK, 38 - [MUIC_INT1] = MAX77693_MUIC_REG_INTMASK1, 39 - [MUIC_INT2] = MAX77693_MUIC_REG_INTMASK2, 40 - [MUIC_INT3] = MAX77693_MUIC_REG_INTMASK3, 41 - }; 42 - 43 - static struct regmap *max77693_get_regmap(struct max77693_dev *max77693, 44 - enum max77693_irq_source src) 45 - { 46 - switch (src) { 47 - case LED_INT ... CHG_INT: 48 - return max77693->regmap; 49 - case MUIC_INT1 ... MUIC_INT3: 50 - return max77693->regmap_muic; 51 - default: 52 - return ERR_PTR(-EINVAL); 53 - } 54 - } 55 - 56 - struct max77693_irq_data { 57 - int mask; 58 - enum max77693_irq_source group; 59 - }; 60 - 61 - #define DECLARE_IRQ(idx, _group, _mask) \ 62 - [(idx)] = { .group = (_group), .mask = (_mask) } 63 - static const struct max77693_irq_data max77693_irqs[] = { 64 - DECLARE_IRQ(MAX77693_LED_IRQ_FLED2_OPEN, LED_INT, 1 << 0), 65 - DECLARE_IRQ(MAX77693_LED_IRQ_FLED2_SHORT, LED_INT, 1 << 1), 66 - DECLARE_IRQ(MAX77693_LED_IRQ_FLED1_OPEN, LED_INT, 1 << 2), 67 - DECLARE_IRQ(MAX77693_LED_IRQ_FLED1_SHORT, LED_INT, 1 << 3), 68 - DECLARE_IRQ(MAX77693_LED_IRQ_MAX_FLASH, LED_INT, 1 << 4), 69 - 70 - DECLARE_IRQ(MAX77693_TOPSYS_IRQ_T120C_INT, TOPSYS_INT, 1 << 0), 71 - DECLARE_IRQ(MAX77693_TOPSYS_IRQ_T140C_INT, TOPSYS_INT, 1 << 1), 72 - DECLARE_IRQ(MAX77693_TOPSYS_IRQ_LOWSYS_INT, TOPSYS_INT, 1 << 3), 73 - 74 - DECLARE_IRQ(MAX77693_CHG_IRQ_BYP_I, CHG_INT, 1 << 0), 75 - DECLARE_IRQ(MAX77693_CHG_IRQ_THM_I, CHG_INT, 1 << 2), 76 - DECLARE_IRQ(MAX77693_CHG_IRQ_BAT_I, CHG_INT, 1 << 3), 77 - DECLARE_IRQ(MAX77693_CHG_IRQ_CHG_I, CHG_INT, 1 << 4), 78 - DECLARE_IRQ(MAX77693_CHG_IRQ_CHGIN_I, CHG_INT, 1 << 6), 79 - 80 - DECLARE_IRQ(MAX77693_MUIC_IRQ_INT1_ADC, MUIC_INT1, 1 << 0), 81 - DECLARE_IRQ(MAX77693_MUIC_IRQ_INT1_ADC_LOW, MUIC_INT1, 1 << 1), 82 - DECLARE_IRQ(MAX77693_MUIC_IRQ_INT1_ADC_ERR, MUIC_INT1, 1 << 2), 83 - DECLARE_IRQ(MAX77693_MUIC_IRQ_INT1_ADC1K, MUIC_INT1, 1 << 3), 84 - 85 - DECLARE_IRQ(MAX77693_MUIC_IRQ_INT2_CHGTYP, MUIC_INT2, 1 << 0), 86 - DECLARE_IRQ(MAX77693_MUIC_IRQ_INT2_CHGDETREUN, MUIC_INT2, 1 << 1), 87 - DECLARE_IRQ(MAX77693_MUIC_IRQ_INT2_DCDTMR, MUIC_INT2, 1 << 2), 88 - DECLARE_IRQ(MAX77693_MUIC_IRQ_INT2_DXOVP, MUIC_INT2, 1 << 3), 89 - DECLARE_IRQ(MAX77693_MUIC_IRQ_INT2_VBVOLT, MUIC_INT2, 1 << 4), 90 - DECLARE_IRQ(MAX77693_MUIC_IRQ_INT2_VIDRM, MUIC_INT2, 1 << 5), 91 - 92 - DECLARE_IRQ(MAX77693_MUIC_IRQ_INT3_EOC, MUIC_INT3, 1 << 0), 93 - DECLARE_IRQ(MAX77693_MUIC_IRQ_INT3_CGMBC, MUIC_INT3, 1 << 1), 94 - DECLARE_IRQ(MAX77693_MUIC_IRQ_INT3_OVP, MUIC_INT3, 1 << 2), 95 - DECLARE_IRQ(MAX77693_MUIC_IRQ_INT3_MBCCHG_ERR, MUIC_INT3, 1 << 3), 96 - DECLARE_IRQ(MAX77693_MUIC_IRQ_INT3_CHG_ENABLED, MUIC_INT3, 1 << 4), 97 - DECLARE_IRQ(MAX77693_MUIC_IRQ_INT3_BAT_DET, MUIC_INT3, 1 << 5), 98 - }; 99 - 100 - static void max77693_irq_lock(struct irq_data *data) 101 - { 102 - struct max77693_dev *max77693 = irq_get_chip_data(data->irq); 103 - 104 - mutex_lock(&max77693->irqlock); 105 - } 106 - 107 - static void max77693_irq_sync_unlock(struct irq_data *data) 108 - { 109 - struct max77693_dev *max77693 = irq_get_chip_data(data->irq); 110 - int i; 111 - 112 - for (i = 0; i < MAX77693_IRQ_GROUP_NR; i++) { 113 - u8 mask_reg = max77693_mask_reg[i]; 114 - struct regmap *map = max77693_get_regmap(max77693, i); 115 - 116 - if (mask_reg == MAX77693_REG_INVALID || 117 - IS_ERR_OR_NULL(map)) 118 - continue; 119 - max77693->irq_masks_cache[i] = max77693->irq_masks_cur[i]; 120 - 121 - max77693_write_reg(map, max77693_mask_reg[i], 122 - max77693->irq_masks_cur[i]); 123 - } 124 - 125 - mutex_unlock(&max77693->irqlock); 126 - } 127 - 128 - static const inline struct max77693_irq_data * 129 - irq_to_max77693_irq(struct max77693_dev *max77693, int irq) 130 - { 131 - struct irq_data *data = irq_get_irq_data(irq); 132 - return &max77693_irqs[data->hwirq]; 133 - } 134 - 135 - static void max77693_irq_mask(struct irq_data *data) 136 - { 137 - struct max77693_dev *max77693 = irq_get_chip_data(data->irq); 138 - const struct max77693_irq_data *irq_data = 139 - irq_to_max77693_irq(max77693, data->irq); 140 - 141 - if (irq_data->group >= MAX77693_IRQ_GROUP_NR) 142 - return; 143 - 144 - if (irq_data->group >= MUIC_INT1 && irq_data->group <= MUIC_INT3) 145 - max77693->irq_masks_cur[irq_data->group] &= ~irq_data->mask; 146 - else 147 - max77693->irq_masks_cur[irq_data->group] |= irq_data->mask; 148 - } 149 - 150 - static void max77693_irq_unmask(struct irq_data *data) 151 - { 152 - struct max77693_dev *max77693 = irq_get_chip_data(data->irq); 153 - const struct max77693_irq_data *irq_data = 154 - irq_to_max77693_irq(max77693, data->irq); 155 - 156 - if (irq_data->group >= MAX77693_IRQ_GROUP_NR) 157 - return; 158 - 159 - if (irq_data->group >= MUIC_INT1 && irq_data->group <= MUIC_INT3) 160 - max77693->irq_masks_cur[irq_data->group] |= irq_data->mask; 161 - else 162 - max77693->irq_masks_cur[irq_data->group] &= ~irq_data->mask; 163 - } 164 - 165 - static struct irq_chip max77693_irq_chip = { 166 - .name = "max77693", 167 - .irq_bus_lock = max77693_irq_lock, 168 - .irq_bus_sync_unlock = max77693_irq_sync_unlock, 169 - .irq_mask = max77693_irq_mask, 170 - .irq_unmask = max77693_irq_unmask, 171 - }; 172 - 173 - #define MAX77693_IRQSRC_CHG (1 << 0) 174 - #define MAX77693_IRQSRC_TOP (1 << 1) 175 - #define MAX77693_IRQSRC_FLASH (1 << 2) 176 - #define MAX77693_IRQSRC_MUIC (1 << 3) 177 - static irqreturn_t max77693_irq_thread(int irq, void *data) 178 - { 179 - struct max77693_dev *max77693 = data; 180 - u8 irq_reg[MAX77693_IRQ_GROUP_NR] = {}; 181 - u8 irq_src; 182 - int ret; 183 - int i, cur_irq; 184 - 185 - ret = max77693_read_reg(max77693->regmap, MAX77693_PMIC_REG_INTSRC, 186 - &irq_src); 187 - if (ret < 0) { 188 - dev_err(max77693->dev, "Failed to read interrupt source: %d\n", 189 - ret); 190 - return IRQ_NONE; 191 - } 192 - 193 - if (irq_src & MAX77693_IRQSRC_CHG) 194 - /* CHG_INT */ 195 - ret = max77693_read_reg(max77693->regmap, MAX77693_CHG_REG_CHG_INT, 196 - &irq_reg[CHG_INT]); 197 - 198 - if (irq_src & MAX77693_IRQSRC_TOP) 199 - /* TOPSYS_INT */ 200 - ret = max77693_read_reg(max77693->regmap, 201 - MAX77693_PMIC_REG_TOPSYS_INT, &irq_reg[TOPSYS_INT]); 202 - 203 - if (irq_src & MAX77693_IRQSRC_FLASH) 204 - /* LED_INT */ 205 - ret = max77693_read_reg(max77693->regmap, 206 - MAX77693_LED_REG_FLASH_INT, &irq_reg[LED_INT]); 207 - 208 - if (irq_src & MAX77693_IRQSRC_MUIC) 209 - /* MUIC INT1 ~ INT3 */ 210 - max77693_bulk_read(max77693->regmap_muic, MAX77693_MUIC_REG_INT1, 211 - MAX77693_NUM_IRQ_MUIC_REGS, &irq_reg[MUIC_INT1]); 212 - 213 - /* Apply masking */ 214 - for (i = 0; i < MAX77693_IRQ_GROUP_NR; i++) { 215 - if (i >= MUIC_INT1 && i <= MUIC_INT3) 216 - irq_reg[i] &= max77693->irq_masks_cur[i]; 217 - else 218 - irq_reg[i] &= ~max77693->irq_masks_cur[i]; 219 - } 220 - 221 - /* Report */ 222 - for (i = 0; i < MAX77693_IRQ_NR; i++) { 223 - if (irq_reg[max77693_irqs[i].group] & max77693_irqs[i].mask) { 224 - cur_irq = irq_find_mapping(max77693->irq_domain, i); 225 - if (cur_irq) 226 - handle_nested_irq(cur_irq); 227 - } 228 - } 229 - 230 - return IRQ_HANDLED; 231 - } 232 - 233 - int max77693_irq_resume(struct max77693_dev *max77693) 234 - { 235 - if (max77693->irq) 236 - max77693_irq_thread(0, max77693); 237 - 238 - return 0; 239 - } 240 - 241 - static int max77693_irq_domain_map(struct irq_domain *d, unsigned int irq, 242 - irq_hw_number_t hw) 243 - { 244 - struct max77693_dev *max77693 = d->host_data; 245 - 246 - irq_set_chip_data(irq, max77693); 247 - irq_set_chip_and_handler(irq, &max77693_irq_chip, handle_edge_irq); 248 - irq_set_nested_thread(irq, 1); 249 - #ifdef CONFIG_ARM 250 - set_irq_flags(irq, IRQF_VALID); 251 - #else 252 - irq_set_noprobe(irq); 253 - #endif 254 - return 0; 255 - } 256 - 257 - static struct irq_domain_ops max77693_irq_domain_ops = { 258 - .map = max77693_irq_domain_map, 259 - }; 260 - 261 - int max77693_irq_init(struct max77693_dev *max77693) 262 - { 263 - struct irq_domain *domain; 264 - int i; 265 - int ret = 0; 266 - u8 intsrc_mask; 267 - 268 - mutex_init(&max77693->irqlock); 269 - 270 - /* Mask individual interrupt sources */ 271 - for (i = 0; i < MAX77693_IRQ_GROUP_NR; i++) { 272 - struct regmap *map; 273 - /* MUIC IRQ 0:MASK 1:NOT MASK */ 274 - /* Other IRQ 1:MASK 0:NOT MASK */ 275 - if (i >= MUIC_INT1 && i <= MUIC_INT3) { 276 - max77693->irq_masks_cur[i] = 0x00; 277 - max77693->irq_masks_cache[i] = 0x00; 278 - } else { 279 - max77693->irq_masks_cur[i] = 0xff; 280 - max77693->irq_masks_cache[i] = 0xff; 281 - } 282 - map = max77693_get_regmap(max77693, i); 283 - 284 - if (IS_ERR_OR_NULL(map)) 285 - continue; 286 - if (max77693_mask_reg[i] == MAX77693_REG_INVALID) 287 - continue; 288 - if (i >= MUIC_INT1 && i <= MUIC_INT3) 289 - max77693_write_reg(map, max77693_mask_reg[i], 0x00); 290 - else 291 - max77693_write_reg(map, max77693_mask_reg[i], 0xff); 292 - } 293 - 294 - domain = irq_domain_add_linear(NULL, MAX77693_IRQ_NR, 295 - &max77693_irq_domain_ops, max77693); 296 - if (!domain) { 297 - dev_err(max77693->dev, "could not create irq domain\n"); 298 - ret = -ENODEV; 299 - goto err_irq; 300 - } 301 - max77693->irq_domain = domain; 302 - 303 - /* Unmask max77693 interrupt */ 304 - ret = max77693_read_reg(max77693->regmap, 305 - MAX77693_PMIC_REG_INTSRC_MASK, &intsrc_mask); 306 - if (ret < 0) { 307 - dev_err(max77693->dev, "fail to read PMIC register\n"); 308 - goto err_irq; 309 - } 310 - 311 - intsrc_mask &= ~(MAX77693_IRQSRC_CHG); 312 - intsrc_mask &= ~(MAX77693_IRQSRC_FLASH); 313 - intsrc_mask &= ~(MAX77693_IRQSRC_MUIC); 314 - ret = max77693_write_reg(max77693->regmap, 315 - MAX77693_PMIC_REG_INTSRC_MASK, intsrc_mask); 316 - if (ret < 0) { 317 - dev_err(max77693->dev, "fail to write PMIC register\n"); 318 - goto err_irq; 319 - } 320 - 321 - ret = request_threaded_irq(max77693->irq, NULL, max77693_irq_thread, 322 - IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 323 - "max77693-irq", max77693); 324 - if (ret) 325 - dev_err(max77693->dev, "Failed to request IRQ %d: %d\n", 326 - max77693->irq, ret); 327 - 328 - err_irq: 329 - return ret; 330 - } 331 - 332 - void max77693_irq_exit(struct max77693_dev *max77693) 333 - { 334 - if (max77693->irq) 335 - free_irq(max77693->irq, max77693); 336 - }

+149 -65

drivers/mfd/max77693.c

··· 49 49 { .name = "max77693-haptic", }, 50 50 }; 51 51 52 - int max77693_read_reg(struct regmap *map, u8 reg, u8 *dest) 53 - { 54 - unsigned int val; 55 - int ret; 56 - 57 - ret = regmap_read(map, reg, &val); 58 - *dest = val; 59 - 60 - return ret; 61 - } 62 - EXPORT_SYMBOL_GPL(max77693_read_reg); 63 - 64 - int max77693_bulk_read(struct regmap *map, u8 reg, int count, u8 *buf) 65 - { 66 - int ret; 67 - 68 - ret = regmap_bulk_read(map, reg, buf, count); 69 - 70 - return ret; 71 - } 72 - EXPORT_SYMBOL_GPL(max77693_bulk_read); 73 - 74 - int max77693_write_reg(struct regmap *map, u8 reg, u8 value) 75 - { 76 - int ret; 77 - 78 - ret = regmap_write(map, reg, value); 79 - 80 - return ret; 81 - } 82 - EXPORT_SYMBOL_GPL(max77693_write_reg); 83 - 84 - int max77693_bulk_write(struct regmap *map, u8 reg, int count, u8 *buf) 85 - { 86 - int ret; 87 - 88 - ret = regmap_bulk_write(map, reg, buf, count); 89 - 90 - return ret; 91 - } 92 - EXPORT_SYMBOL_GPL(max77693_bulk_write); 93 - 94 - int max77693_update_reg(struct regmap *map, u8 reg, u8 val, u8 mask) 95 - { 96 - int ret; 97 - 98 - ret = regmap_update_bits(map, reg, mask, val); 99 - 100 - return ret; 101 - } 102 - EXPORT_SYMBOL_GPL(max77693_update_reg); 103 - 104 52 static const struct regmap_config max77693_regmap_config = { 105 53 .reg_bits = 8, 106 54 .val_bits = 8, 107 55 .max_register = MAX77693_PMIC_REG_END, 56 + }; 57 + 58 + static const struct regmap_irq max77693_led_irqs[] = { 59 + { .mask = LED_IRQ_FLED2_OPEN, }, 60 + { .mask = LED_IRQ_FLED2_SHORT, }, 61 + { .mask = LED_IRQ_FLED1_OPEN, }, 62 + { .mask = LED_IRQ_FLED1_SHORT, }, 63 + { .mask = LED_IRQ_MAX_FLASH, }, 64 + }; 65 + 66 + static const struct regmap_irq_chip max77693_led_irq_chip = { 67 + .name = "max77693-led", 68 + .status_base = MAX77693_LED_REG_FLASH_INT, 69 + .mask_base = MAX77693_LED_REG_FLASH_INT_MASK, 70 + .mask_invert = false, 71 + .num_regs = 1, 72 + .irqs = max77693_led_irqs, 73 + .num_irqs = ARRAY_SIZE(max77693_led_irqs), 74 + }; 75 + 76 + static const struct regmap_irq max77693_topsys_irqs[] = { 77 + { .mask = TOPSYS_IRQ_T120C_INT, }, 78 + { .mask = TOPSYS_IRQ_T140C_INT, }, 79 + { .mask = TOPSYS_IRQ_LOWSYS_INT, }, 80 + }; 81 + 82 + static const struct regmap_irq_chip max77693_topsys_irq_chip = { 83 + .name = "max77693-topsys", 84 + .status_base = MAX77693_PMIC_REG_TOPSYS_INT, 85 + .mask_base = MAX77693_PMIC_REG_TOPSYS_INT_MASK, 86 + .mask_invert = false, 87 + .num_regs = 1, 88 + .irqs = max77693_topsys_irqs, 89 + .num_irqs = ARRAY_SIZE(max77693_topsys_irqs), 90 + }; 91 + 92 + static const struct regmap_irq max77693_charger_irqs[] = { 93 + { .mask = CHG_IRQ_BYP_I, }, 94 + { .mask = CHG_IRQ_THM_I, }, 95 + { .mask = CHG_IRQ_BAT_I, }, 96 + { .mask = CHG_IRQ_CHG_I, }, 97 + { .mask = CHG_IRQ_CHGIN_I, }, 98 + }; 99 + 100 + static const struct regmap_irq_chip max77693_charger_irq_chip = { 101 + .name = "max77693-charger", 102 + .status_base = MAX77693_CHG_REG_CHG_INT, 103 + .mask_base = MAX77693_CHG_REG_CHG_INT_MASK, 104 + .mask_invert = false, 105 + .num_regs = 1, 106 + .irqs = max77693_charger_irqs, 107 + .num_irqs = ARRAY_SIZE(max77693_charger_irqs), 108 108 }; 109 109 110 110 static const struct regmap_config max77693_regmap_muic_config = { ··· 113 113 .max_register = MAX77693_MUIC_REG_END, 114 114 }; 115 115 116 + static const struct regmap_irq max77693_muic_irqs[] = { 117 + { .reg_offset = 0, .mask = MUIC_IRQ_INT1_ADC, }, 118 + { .reg_offset = 0, .mask = MUIC_IRQ_INT1_ADC_LOW, }, 119 + { .reg_offset = 0, .mask = MUIC_IRQ_INT1_ADC_ERR, }, 120 + { .reg_offset = 0, .mask = MUIC_IRQ_INT1_ADC1K, }, 121 + 122 + { .reg_offset = 1, .mask = MUIC_IRQ_INT2_CHGTYP, }, 123 + { .reg_offset = 1, .mask = MUIC_IRQ_INT2_CHGDETREUN, }, 124 + { .reg_offset = 1, .mask = MUIC_IRQ_INT2_DCDTMR, }, 125 + { .reg_offset = 1, .mask = MUIC_IRQ_INT2_DXOVP, }, 126 + { .reg_offset = 1, .mask = MUIC_IRQ_INT2_VBVOLT, }, 127 + { .reg_offset = 1, .mask = MUIC_IRQ_INT2_VIDRM, }, 128 + 129 + { .reg_offset = 2, .mask = MUIC_IRQ_INT3_EOC, }, 130 + { .reg_offset = 2, .mask = MUIC_IRQ_INT3_CGMBC, }, 131 + { .reg_offset = 2, .mask = MUIC_IRQ_INT3_OVP, }, 132 + { .reg_offset = 2, .mask = MUIC_IRQ_INT3_MBCCHG_ERR, }, 133 + { .reg_offset = 2, .mask = MUIC_IRQ_INT3_CHG_ENABLED, }, 134 + { .reg_offset = 2, .mask = MUIC_IRQ_INT3_BAT_DET, }, 135 + }; 136 + 137 + static const struct regmap_irq_chip max77693_muic_irq_chip = { 138 + .name = "max77693-muic", 139 + .status_base = MAX77693_MUIC_REG_INT1, 140 + .mask_base = MAX77693_MUIC_REG_INTMASK1, 141 + .mask_invert = true, 142 + .num_regs = 3, 143 + .irqs = max77693_muic_irqs, 144 + .num_irqs = ARRAY_SIZE(max77693_muic_irqs), 145 + }; 146 + 116 147 static int max77693_i2c_probe(struct i2c_client *i2c, 117 148 const struct i2c_device_id *id) 118 149 { 119 150 struct max77693_dev *max77693; 120 - u8 reg_data; 151 + unsigned int reg_data; 121 152 int ret = 0; 122 153 123 154 max77693 = devm_kzalloc(&i2c->dev, ··· 170 139 return ret; 171 140 } 172 141 173 - ret = max77693_read_reg(max77693->regmap, MAX77693_PMIC_REG_PMIC_ID2, 142 + ret = regmap_read(max77693->regmap, MAX77693_PMIC_REG_PMIC_ID2, 174 143 &reg_data); 175 144 if (ret < 0) { 176 145 dev_err(max77693->dev, "device not found on this channel\n"); ··· 207 176 goto err_regmap_muic; 208 177 } 209 178 210 - ret = max77693_irq_init(max77693); 211 - if (ret < 0) 212 - goto err_irq; 179 + ret = regmap_add_irq_chip(max77693->regmap, max77693->irq, 180 + IRQF_ONESHOT | IRQF_SHARED | 181 + IRQF_TRIGGER_FALLING, 0, 182 + &max77693_led_irq_chip, 183 + &max77693->irq_data_led); 184 + if (ret) { 185 + dev_err(max77693->dev, "failed to add irq chip: %d\n", ret); 186 + goto err_regmap_muic; 187 + } 188 + 189 + ret = regmap_add_irq_chip(max77693->regmap, max77693->irq, 190 + IRQF_ONESHOT | IRQF_SHARED | 191 + IRQF_TRIGGER_FALLING, 0, 192 + &max77693_topsys_irq_chip, 193 + &max77693->irq_data_topsys); 194 + if (ret) { 195 + dev_err(max77693->dev, "failed to add irq chip: %d\n", ret); 196 + goto err_irq_topsys; 197 + } 198 + 199 + ret = regmap_add_irq_chip(max77693->regmap, max77693->irq, 200 + IRQF_ONESHOT | IRQF_SHARED | 201 + IRQF_TRIGGER_FALLING, 0, 202 + &max77693_charger_irq_chip, 203 + &max77693->irq_data_charger); 204 + if (ret) { 205 + dev_err(max77693->dev, "failed to add irq chip: %d\n", ret); 206 + goto err_irq_charger; 207 + } 208 + 209 + ret = regmap_add_irq_chip(max77693->regmap, max77693->irq, 210 + IRQF_ONESHOT | IRQF_SHARED | 211 + IRQF_TRIGGER_FALLING, 0, 212 + &max77693_muic_irq_chip, 213 + &max77693->irq_data_muic); 214 + if (ret) { 215 + dev_err(max77693->dev, "failed to add irq chip: %d\n", ret); 216 + goto err_irq_muic; 217 + } 213 218 214 219 pm_runtime_set_active(max77693->dev); 215 220 ··· 257 190 return ret; 258 191 259 192 err_mfd: 260 - max77693_irq_exit(max77693); 261 - err_irq: 193 + mfd_remove_devices(max77693->dev); 194 + regmap_del_irq_chip(max77693->irq, max77693->irq_data_muic); 195 + err_irq_muic: 196 + regmap_del_irq_chip(max77693->irq, max77693->irq_data_charger); 197 + err_irq_charger: 198 + regmap_del_irq_chip(max77693->irq, max77693->irq_data_topsys); 199 + err_irq_topsys: 200 + regmap_del_irq_chip(max77693->irq, max77693->irq_data_led); 262 201 err_regmap_muic: 263 202 i2c_unregister_device(max77693->haptic); 264 203 err_i2c_haptic: ··· 277 204 struct max77693_dev *max77693 = i2c_get_clientdata(i2c); 278 205 279 206 mfd_remove_devices(max77693->dev); 280 - max77693_irq_exit(max77693); 207 + 208 + regmap_del_irq_chip(max77693->irq, max77693->irq_data_muic); 209 + regmap_del_irq_chip(max77693->irq, max77693->irq_data_charger); 210 + regmap_del_irq_chip(max77693->irq, max77693->irq_data_topsys); 211 + regmap_del_irq_chip(max77693->irq, max77693->irq_data_led); 212 + 281 213 i2c_unregister_device(max77693->muic); 282 214 i2c_unregister_device(max77693->haptic); 283 215 ··· 300 222 struct i2c_client *i2c = container_of(dev, struct i2c_client, dev); 301 223 struct max77693_dev *max77693 = i2c_get_clientdata(i2c); 302 224 303 - if (device_may_wakeup(dev)) 304 - irq_set_irq_wake(max77693->irq, 1); 225 + if (device_may_wakeup(dev)) { 226 + enable_irq_wake(max77693->irq); 227 + disable_irq(max77693->irq); 228 + } 229 + 305 230 return 0; 306 231 } 307 232 ··· 313 232 struct i2c_client *i2c = container_of(dev, struct i2c_client, dev); 314 233 struct max77693_dev *max77693 = i2c_get_clientdata(i2c); 315 234 316 - if (device_may_wakeup(dev)) 317 - irq_set_irq_wake(max77693->irq, 0); 318 - return max77693_irq_resume(max77693); 235 + if (device_may_wakeup(dev)) { 236 + disable_irq_wake(max77693->irq); 237 + enable_irq(max77693->irq); 238 + } 239 + 240 + return 0; 319 241 } 320 242 321 243 static const struct dev_pm_ops max77693_pm = {

+6 -6

drivers/regulator/max77693.c

··· 31 31 #include <linux/mfd/max77693.h> 32 32 #include <linux/mfd/max77693-private.h> 33 33 #include <linux/regulator/of_regulator.h> 34 + #include <linux/regmap.h> 34 35 35 36 #define CHGIN_ILIM_STEP_20mA 20000 36 37 ··· 40 39 static int max77693_chg_is_enabled(struct regulator_dev *rdev) 41 40 { 42 41 int ret; 43 - u8 val; 42 + unsigned int val; 44 43 45 - ret = max77693_read_reg(rdev->regmap, rdev->desc->enable_reg, &val); 44 + ret = regmap_read(rdev->regmap, rdev->desc->enable_reg, &val); 46 45 if (ret) 47 46 return ret; 48 47 ··· 58 57 { 59 58 unsigned int chg_min_uA = rdev->constraints->min_uA; 60 59 unsigned int chg_max_uA = rdev->constraints->max_uA; 61 - u8 reg, sel; 60 + unsigned int reg, sel; 62 61 unsigned int val; 63 62 int ret; 64 63 65 - ret = max77693_read_reg(rdev->regmap, 66 - MAX77693_CHG_REG_CHG_CNFG_09, &reg); 64 + ret = regmap_read(rdev->regmap, MAX77693_CHG_REG_CHG_CNFG_09, &reg); 67 65 if (ret < 0) 68 66 return ret; 69 67 ··· 96 96 /* the first four codes for charger current are all 60mA */ 97 97 sel += 3; 98 98 99 - return max77693_write_reg(rdev->regmap, 99 + return regmap_write(rdev->regmap, 100 100 MAX77693_CHG_REG_CHG_CNFG_09, sel); 101 101 } 102 102 /* end of CHARGER regulator ops */

+44 -10

include/linux/mfd/max77693-private.h

··· 262 262 MAX77693_IRQ_GROUP_NR, 263 263 }; 264 264 265 + #define LED_IRQ_FLED2_OPEN BIT(0) 266 + #define LED_IRQ_FLED2_SHORT BIT(1) 267 + #define LED_IRQ_FLED1_OPEN BIT(2) 268 + #define LED_IRQ_FLED1_SHORT BIT(3) 269 + #define LED_IRQ_MAX_FLASH BIT(4) 270 + 271 + #define TOPSYS_IRQ_T120C_INT BIT(0) 272 + #define TOPSYS_IRQ_T140C_INT BIT(1) 273 + #define TOPSYS_IRQ_LOWSYS_INT BIT(3) 274 + 275 + #define CHG_IRQ_BYP_I BIT(0) 276 + #define CHG_IRQ_THM_I BIT(2) 277 + #define CHG_IRQ_BAT_I BIT(3) 278 + #define CHG_IRQ_CHG_I BIT(4) 279 + #define CHG_IRQ_CHGIN_I BIT(6) 280 + 281 + #define MUIC_IRQ_INT1_ADC BIT(0) 282 + #define MUIC_IRQ_INT1_ADC_LOW BIT(1) 283 + #define MUIC_IRQ_INT1_ADC_ERR BIT(2) 284 + #define MUIC_IRQ_INT1_ADC1K BIT(3) 285 + 286 + #define MUIC_IRQ_INT2_CHGTYP BIT(0) 287 + #define MUIC_IRQ_INT2_CHGDETREUN BIT(1) 288 + #define MUIC_IRQ_INT2_DCDTMR BIT(2) 289 + #define MUIC_IRQ_INT2_DXOVP BIT(3) 290 + #define MUIC_IRQ_INT2_VBVOLT BIT(4) 291 + #define MUIC_IRQ_INT2_VIDRM BIT(5) 292 + 293 + #define MUIC_IRQ_INT3_EOC BIT(0) 294 + #define MUIC_IRQ_INT3_CGMBC BIT(1) 295 + #define MUIC_IRQ_INT3_OVP BIT(2) 296 + #define MUIC_IRQ_INT3_MBCCHG_ERR BIT(3) 297 + #define MUIC_IRQ_INT3_CHG_ENABLED BIT(4) 298 + #define MUIC_IRQ_INT3_BAT_DET BIT(5) 299 + 265 300 enum max77693_irq { 266 301 /* PMIC - FLASH */ 267 302 MAX77693_LED_IRQ_FLED2_OPEN, ··· 317 282 MAX77693_CHG_IRQ_CHG_I, 318 283 MAX77693_CHG_IRQ_CHGIN_I, 319 284 285 + MAX77693_IRQ_NR, 286 + }; 287 + 288 + enum max77693_irq_muic { 320 289 /* MUIC INT1 */ 321 290 MAX77693_MUIC_IRQ_INT1_ADC, 322 291 MAX77693_MUIC_IRQ_INT1_ADC_LOW, ··· 343 304 MAX77693_MUIC_IRQ_INT3_CHG_ENABLED, 344 305 MAX77693_MUIC_IRQ_INT3_BAT_DET, 345 306 346 - MAX77693_IRQ_NR, 307 + MAX77693_MUIC_IRQ_NR, 347 308 }; 348 309 349 310 struct max77693_dev { ··· 358 319 struct regmap *regmap_muic; 359 320 struct regmap *regmap_haptic; 360 321 361 - struct irq_domain *irq_domain; 322 + struct regmap_irq_chip_data *irq_data_led; 323 + struct regmap_irq_chip_data *irq_data_topsys; 324 + struct regmap_irq_chip_data *irq_data_charger; 325 + struct regmap_irq_chip_data *irq_data_muic; 362 326 363 327 int irq; 364 328 int irq_gpio; ··· 373 331 enum max77693_types { 374 332 TYPE_MAX77693, 375 333 }; 376 - 377 - extern int max77693_read_reg(struct regmap *map, u8 reg, u8 *dest); 378 - extern int max77693_bulk_read(struct regmap *map, u8 reg, int count, 379 - u8 *buf); 380 - extern int max77693_write_reg(struct regmap *map, u8 reg, u8 value); 381 - extern int max77693_bulk_write(struct regmap *map, u8 reg, int count, 382 - u8 *buf); 383 - extern int max77693_update_reg(struct regmap *map, u8 reg, u8 val, u8 mask); 384 334 385 335 extern int max77693_irq_init(struct max77693_dev *max77686); 386 336 extern void max77693_irq_exit(struct max77693_dev *max77686);