tjh.dev / kernel
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ARM: mm: use inner-shareable barriers for TLB and user cache operations

System-wide barriers aren't required for situations where we only need
to make visibility and ordering guarantees in the inner-shareable domain
(i.e. we are not dealing with devices or potentially incoherent CPUs).

This patch changes the v7 TLB operations, coherent_user_range and
dcache_clean_area functions to user inner-shareable barriers. For cache
maintenance, only the store access type is required to ensure completion.

Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>

Will Deacon 6abdd491 62cbbc42

+7 -7
+2 -2
arch/arm/mm/cache-v7.S
··· 282 282 add r12, r12, r2 283 283 cmp r12, r1 284 284 blo 1b 285 - dsb 285 + dsb ishst 286 286 icache_line_size r2, r3 287 287 sub r3, r2, #1 288 288 bic r12, r0, r3 ··· 294 294 mov r0, #0 295 295 ALT_SMP(mcr p15, 0, r0, c7, c1, 6) @ invalidate BTB Inner Shareable 296 296 ALT_UP(mcr p15, 0, r0, c7, c5, 6) @ invalidate BTB 297 - dsb 297 + dsb ishst 298 298 isb 299 299 mov pc, lr 300 300
+1 -1
arch/arm/mm/proc-v7.S
··· 83 83 add r0, r0, r2 84 84 subs r1, r1, r2 85 85 bhi 2b 86 - dsb 86 + dsb ishst 87 87 mov pc, lr 88 88 ENDPROC(cpu_v7_dcache_clean_area) 89 89
+4 -4
arch/arm/mm/tlb-v7.S
··· 35 35 ENTRY(v7wbi_flush_user_tlb_range) 36 36 vma_vm_mm r3, r2 @ get vma->vm_mm 37 37 mmid r3, r3 @ get vm_mm->context.id 38 - dsb 38 + dsb ish 39 39 mov r0, r0, lsr #PAGE_SHIFT @ align address 40 40 mov r1, r1, lsr #PAGE_SHIFT 41 41 asid r3, r3 @ mask ASID ··· 56 56 add r0, r0, #PAGE_SZ 57 57 cmp r0, r1 58 58 blo 1b 59 - dsb 59 + dsb ish 60 60 mov pc, lr 61 61 ENDPROC(v7wbi_flush_user_tlb_range) 62 62 ··· 69 69 * - end - end address (exclusive, may not be aligned) 70 70 */ 71 71 ENTRY(v7wbi_flush_kern_tlb_range) 72 - dsb 72 + dsb ish 73 73 mov r0, r0, lsr #PAGE_SHIFT @ align address 74 74 mov r1, r1, lsr #PAGE_SHIFT 75 75 mov r0, r0, lsl #PAGE_SHIFT ··· 84 84 add r0, r0, #PAGE_SZ 85 85 cmp r0, r1 86 86 blo 1b 87 - dsb 87 + dsb ish 88 88 isb 89 89 mov pc, lr 90 90 ENDPROC(v7wbi_flush_kern_tlb_range)