[AGPGART] Lots of CodingStyle/whitespace cleanups.

Eliminate trailing whitespace.
s/if(/if (/
s/for(/for (/

Signed-off-by: Dave Jones <[e-mail]>

drivers/char/agp/Kconfig

···
 	tristate "Serverworks LE/HE chipset support"
 	depends on AGP && X86_32
 	help
-	  Say Y here to support the Serverworks AGP card.  See 
+	  Say Y here to support the Serverworks AGP card.  See
 	  <http://www.serverworks.com/> for product descriptions and images.
 
 config AGP_VIA

drivers/char/agp/agp.h

···
  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * JEFF HARTMANN, OR ANY OTHER CONTRIBUTORS BE LIABLE FOR ANY CLAIM, 
- * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 
- * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE 
+ * JEFF HARTMANN, OR ANY OTHER CONTRIBUTORS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
  * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  *
  */
···
 struct gatt_mask {
 	unsigned long mask;
 	u32 type;
-	/* totally device specific, for integrated chipsets that 
+	/* totally device specific, for integrated chipsets that
 	 * might have different types of memory masks.  For other
 	 * devices this will probably be ignored */
 };
···
 	void (*agp_enable)(struct agp_bridge_data *, u32);
 	void (*cleanup)(void);
 	void (*tlb_flush)(struct agp_memory *);
-	unsigned long (*mask_memory)(struct agp_bridge_data *,
-		unsigned long, int);
+	unsigned long (*mask_memory)(struct agp_bridge_data *, unsigned long, int);
 	void (*cache_flush)(void);
 	int (*create_gatt_table)(struct agp_bridge_data *);
 	int (*free_gatt_table)(struct agp_bridge_data *);

drivers/char/agp/ali-agp.c

···
 
 	if (!addr)
 		return NULL;
-	
+
 	pci_read_config_dword(agp_bridge->dev, ALI_CACHE_FLUSH_CTRL, &temp);
 	pci_write_config_dword(agp_bridge->dev, ALI_CACHE_FLUSH_CTRL,
 			(((temp & ALI_CACHE_FLUSH_ADDR_MASK) |

drivers/char/agp/alpha-agp.c

···
 	dma_addr = address - vma->vm_start + agp->aperture.bus_base;
 	pa = agp->ops->translate(agp, dma_addr);
 
-	if (pa == (unsigned long)-EINVAL) return NULL;	/* no translation */
-	
+	if (pa == (unsigned long)-EINVAL)
+		return NULL;	/* no translation */
+
 	/*
 	 * Get the page, inc the use count, and return it
 	 */
···
 	agp_device_command(agp->mode.lw, 0);
 }
 
-static int alpha_core_agp_insert_memory(struct agp_memory *mem, off_t pg_start, 
+static int alpha_core_agp_insert_memory(struct agp_memory *mem, off_t pg_start,
 					int type)
 {
 	alpha_agp_info *agp = agp_bridge->dev_private_data;
···
 
 	temp = agp_bridge->current_size;
 	num_entries = A_SIZE_FIX(temp)->num_entries;
-	if ((pg_start + mem->page_count) > num_entries) return -EINVAL;
+	if ((pg_start + mem->page_count) > num_entries)
+		return -EINVAL;
 
 	status = agp->ops->bind(agp, pg_start, mem);
 	mb();
···
 	return status;
 }
 
-static int alpha_core_agp_remove_memory(struct agp_memory *mem, off_t pg_start, 
+static int alpha_core_agp_remove_memory(struct agp_memory *mem, off_t pg_start,
 					int type)
 {
 	alpha_agp_info *agp = agp_bridge->dev_private_data;
···
 	.size_type		= FIXED_APER_SIZE,
 	.cant_use_aperture	= 1,
 	.masks			= NULL,
-	
+
 	.fetch_size		= alpha_core_agp_fetch_size,
 	.configure		= alpha_core_agp_configure,
 	.agp_enable		= alpha_core_agp_enable,

drivers/char/agp/amd64-agp.c

···
 	{256,  65536,  6, 0x00000700 },	/* 1 1 1 0 0 0 */
 	{128,  32768,  5, 0x00000720 },	/* 1 1 1 1 0 0 */
 	{64,   16384,  4, 0x00000730 },	/* 1 1 1 1 1 0 */
-	{32,   8192,   3, 0x00000738 } 	/* 1 1 1 1 1 1 */
+	{32,   8192,   3, 0x00000738 }	/* 1 1 1 1 1 1 */
 };
 
 static int amd_8151_configure(void)

drivers/char/agp/ati-agp.c

···
 	/*CACHE_FLUSH();*/
 	global_cache_flush();
 
-	for(i = 0; i < PAGE_SIZE / sizeof(unsigned long); i++) {
+	for (i = 0; i < PAGE_SIZE / sizeof(unsigned long); i++) {
 		writel(agp_bridge->scratch_page, page_map->remapped+i);
 		readl(page_map->remapped+i);	/* PCI Posting. */
 	}
···
 	ati_page_map *entry;
 
 	tables = ati_generic_private.gatt_pages;
-	for(i = 0; i < ati_generic_private.num_tables; i++) {
+	for (i = 0; i < ati_generic_private.num_tables; i++) {
 		entry = tables[i];
 		if (entry != NULL) {
 			if (entry->real != NULL)
···
 	agp_bridge->gart_bus_addr = addr;
 
 	/* Calculate the agp offset */
-	for(i = 0; i < value->num_entries / 1024; i++, addr += 0x00400000) {
+	for (i = 0; i < value->num_entries / 1024; i++, addr += 0x00400000) {
 		writel(virt_to_gart(ati_generic_private.gatt_pages[i]->real) | 1,
 			page_dir.remapped+GET_PAGE_DIR_OFF(addr));
 		readl(page_dir.remapped+GET_PAGE_DIR_OFF(addr));	/* PCI Posting. */

drivers/char/agp/backend.c

···
 struct agp_bridge_data *agp_alloc_bridge(void)
 {
 	struct agp_bridge_data *bridge;
-	
+
 	bridge = kzalloc(sizeof(*bridge), GFP_KERNEL);
 	if (!bridge)
 		return NULL;

drivers/char/agp/efficeon-agp.c

···
 /*
  * Transmeta's Efficeon AGPGART driver.
- * 
+ *
  * Based upon a diff by Linus around November '02.
  *
  * Ported to the 2.6 kernel by Carlos Puchol <[e-mail]>
···
 
 /*
  * NOTE-cpg-040217:
- * 
+ *
  *   - when compiled as a module, after loading the module,
  *     it will refuse to unload, indicating it is in use,
  *     when it is not.
···
  *      8: Present
  *    7:6: reserved, write as zero
  *    5:0: GATT directory index: which 1st-level entry
- * 
+ *
  * The Efficeon AGP spec requires pages to be WB-cacheable
  * but to be explicitly CLFLUSH'd after any changes.
  */
···
 	struct aper_size_info_lvl2 *current_size;
 
 	printk(KERN_DEBUG PFX "efficeon_configure()\n");
-	
+
 	current_size = A_SIZE_LVL2(agp_bridge->current_size);
 
 	/* aperture size */
···
 	const int present = EFFICEON_PRESENT;
 	const int clflush_chunk = ((cpuid_ebx(1) >> 8) & 0xff) << 3;
 	int num_entries, l1_pages;
-	
+
 	num_entries = A_SIZE_LVL2(agp_bridge->current_size)->num_entries;
 
 	printk(KERN_DEBUG PFX "efficeon_create_gatt_table(%d)\n", num_entries);
···
 
 		if (!page)
 			continue;
-		
+
 		page += (index & 0x3ff);
 		*page = insert;
 
 		/* clflush is slow, so don't clflush until we have to */
-		if ( last_page && 
+		if ( last_page &&
 		     ((unsigned long)page^(unsigned long)last_page) & clflush_mask )
 		    asm volatile("clflush %0" : : "m" (*last_page));
 
···
 	*/
 	r = &pdev->resource[0];
 	if (!r->start && r->end) {
-		if(pci_assign_resource(pdev, 0)) {
+		if (pci_assign_resource(pdev, 0)) {
 			printk(KERN_ERR PFX "could not assign resource 0\n");
 			return -ENODEV;
 		}

drivers/char/agp/frontend.c

···
 	if (agp_fe.current_controller != NULL)
 		return -EBUSY;
 
-	if(!agp_bridge)
+	if (!agp_bridge)
 		return -ENODEV;
 
         if (atomic_read(&agp_bridge->agp_in_use))

drivers/char/agp/generic.c

···
 /**
  *	agp_copy_info  -  copy bridge state information
  *
- *	@info:		agp_kern_info pointer.  The caller should insure that this pointer is valid. 
+ *	@info:		agp_kern_info pointer.  The caller should insure that this pointer is valid.
  *
  *	This function copies information about the agp bridge device and the state of
  *	the agp backend into an agp_kern_info pointer.

drivers/char/agp/hp-agp.c

···
 	/*
 	 * IOC already configured by sba_iommu module; just use
 	 * its setup.  We assume:
-	 * 	- IOVA space is 1Gb in size
-	 * 	- first 512Mb is IOMMU, second 512Mb is GART
+	 *	- IOVA space is 1Gb in size
+	 *	- first 512Mb is IOMMU, second 512Mb is GART
 	 */
 	hp->io_tlb_ps = readq(hp->ioc_regs+HP_ZX1_TCNFG);
 	switch (hp->io_tlb_ps) {
···
 
 	if (hp->gatt[0] != HP_ZX1_SBA_IOMMU_COOKIE) {
 		/* Normal case when no AGP device in system */
-	    	hp->gatt = NULL;
+		hp->gatt = NULL;
 		hp->gatt_entries = 0;
 		printk(KERN_ERR PFX "No reserved IO PDIR entry found; "
 		       "GART disabled\n");

drivers/char/agp/i460-agp.c

···
 	num_entries = A_SIZE_8(temp)->num_entries;
 
 	/* Figure out what pg_start means in terms of our large GART pages */
-	start	 	= &i460.lp_desc[pg_start / I460_KPAGES_PER_IOPAGE];
-	end 		= &i460.lp_desc[(pg_start + mem->page_count - 1) / I460_KPAGES_PER_IOPAGE];
-	start_offset 	= pg_start % I460_KPAGES_PER_IOPAGE;
-	end_offset 	= (pg_start + mem->page_count - 1) % I460_KPAGES_PER_IOPAGE;
+	start = &i460.lp_desc[pg_start / I460_KPAGES_PER_IOPAGE];
+	end = &i460.lp_desc[(pg_start + mem->page_count - 1) / I460_KPAGES_PER_IOPAGE];
+	start_offset = pg_start % I460_KPAGES_PER_IOPAGE;
+	end_offset = (pg_start + mem->page_count - 1) % I460_KPAGES_PER_IOPAGE;
 
 	if (end > i460.lp_desc + num_entries) {
 		printk(KERN_ERR PFX "Looks like we're out of AGP memory\n");
···
 	num_entries = A_SIZE_8(temp)->num_entries;
 
 	/* Figure out what pg_start means in terms of our large GART pages */
-	start	 	= &i460.lp_desc[pg_start / I460_KPAGES_PER_IOPAGE];
-	end 		= &i460.lp_desc[(pg_start + mem->page_count - 1) / I460_KPAGES_PER_IOPAGE];
-	start_offset 	= pg_start % I460_KPAGES_PER_IOPAGE;
-	end_offset 	= (pg_start + mem->page_count - 1) % I460_KPAGES_PER_IOPAGE;
+	start = &i460.lp_desc[pg_start / I460_KPAGES_PER_IOPAGE];
+	end = &i460.lp_desc[(pg_start + mem->page_count - 1) / I460_KPAGES_PER_IOPAGE];
+	start_offset = pg_start % I460_KPAGES_PER_IOPAGE;
+	end_offset = (pg_start + mem->page_count - 1) % I460_KPAGES_PER_IOPAGE;
 
 	for (i = 0, lp = start; lp <= end; ++lp) {
 		for (idx = ((lp == start) ? start_offset : 0);

drivers/char/agp/intel-agp.c

···
 	temp = agp_bridge->current_size;
 	num_entries = A_SIZE_FIX(temp)->num_entries;
 
-	if ((pg_start + mem->page_count) > num_entries) {
+	if ((pg_start + mem->page_count) > num_entries)
 		return -EINVAL;
-	}
+
 	for (j = pg_start; j < (pg_start + mem->page_count); j++) {
 		if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j)))
 			return -EBUSY;
···
 			agp_bridge->driver->tlb_flush(mem);
 			return 0;
 		}
-		if((type == AGP_PHYS_MEMORY) && (mem->type == AGP_PHYS_MEMORY))
+		if ((type == AGP_PHYS_MEMORY) && (mem->type == AGP_PHYS_MEMORY))
 			goto insert;
 		return -EINVAL;
 	}
···
 static void intel_i810_free_by_type(struct agp_memory *curr)
 {
 	agp_free_key(curr->key);
-	if(curr->type == AGP_PHYS_MEMORY) {
+	if (curr->type == AGP_PHYS_MEMORY) {
 		if (curr->page_count == 4)
 			i8xx_destroy_pages(gart_to_virt(curr->memory[0]));
 		else {
···
 		name = "i820";
 		break;
 	case PCI_DEVICE_ID_INTEL_82830_HB:
-		if (find_i830(PCI_DEVICE_ID_INTEL_82830_CGC)) {
+		if (find_i830(PCI_DEVICE_ID_INTEL_82830_CGC))
 			bridge->driver = &intel_830_driver;
-		} else {
+		else
 			bridge->driver = &intel_830mp_driver;
-		}
 		name = "830M";
 		break;
 	case PCI_DEVICE_ID_INTEL_82840_HB:
···
 		name = "i845";
 		break;
 	case PCI_DEVICE_ID_INTEL_82845G_HB:
-		if (find_i830(PCI_DEVICE_ID_INTEL_82845G_IG)) {
+		if (find_i830(PCI_DEVICE_ID_INTEL_82845G_IG))
 			bridge->driver = &intel_830_driver;
-		} else {
+		else
 			bridge->driver = &intel_845_driver;
-		}
 		name = "845G";
 		break;
 	case PCI_DEVICE_ID_INTEL_82850_HB:
···
 		name = "i860";
 		break;
 	case PCI_DEVICE_ID_INTEL_82865_HB:
-		if (find_i830(PCI_DEVICE_ID_INTEL_82865_IG)) {
+		if (find_i830(PCI_DEVICE_ID_INTEL_82865_IG))
 			bridge->driver = &intel_830_driver;
-		} else {
+		else
 			bridge->driver = &intel_845_driver;
-		}
 		name = "865";
 		break;
 	case PCI_DEVICE_ID_INTEL_82875_HB:
···
 		name = "i875";
 		break;
 	case PCI_DEVICE_ID_INTEL_82915G_HB:
-		if (find_i830(PCI_DEVICE_ID_INTEL_82915G_IG)) {
+		if (find_i830(PCI_DEVICE_ID_INTEL_82915G_IG))
 			bridge->driver = &intel_915_driver;
-		} else {
+		else
 			bridge->driver = &intel_845_driver;
-		}
 		name = "915G";
 		break;
 	case PCI_DEVICE_ID_INTEL_82915GM_HB:
-		if (find_i830(PCI_DEVICE_ID_INTEL_82915GM_IG)) {
+		if (find_i830(PCI_DEVICE_ID_INTEL_82915GM_IG))
 			bridge->driver = &intel_915_driver;
-		} else {
+		else
 			bridge->driver = &intel_845_driver;
-		}
 		name = "915GM";
 		break;
 	case PCI_DEVICE_ID_INTEL_82945G_HB:
-		if (find_i830(PCI_DEVICE_ID_INTEL_82945G_IG)) {
+		if (find_i830(PCI_DEVICE_ID_INTEL_82945G_IG))
 			bridge->driver = &intel_915_driver;
-		} else {
+		else
 			bridge->driver = &intel_845_driver;
-		}
 		name = "945G";
 		break;
 	case PCI_DEVICE_ID_INTEL_82945GM_HB:
-		if (find_i830(PCI_DEVICE_ID_INTEL_82945GM_IG)) {
+		if (find_i830(PCI_DEVICE_ID_INTEL_82945GM_IG))
 			bridge->driver = &intel_915_driver;
-		} else {
+		else
 			bridge->driver = &intel_845_driver;
-		}
 		name = "945GM";
 		break;
 	case PCI_DEVICE_ID_INTEL_7505_0:
···
 	*/
 	r = &pdev->resource[0];
 	if (!r->start && r->end) {
-		if(pci_assign_resource(pdev, 0)) {
+		if (pci_assign_resource(pdev, 0)) {
 			printk(KERN_ERR PFX "could not assign resource 0\n");
 			agp_put_bridge(bridge);
 			return -ENODEV;

drivers/char/agp/isoch.c

···
 
 	list_for_each(pos, head) {
 		cur = list_entry(pos, struct agp_3_5_dev, list);
-		if(cur->maxbw > n->maxbw)
+		if (cur->maxbw > n->maxbw)
 			break;
 	}
 	list_add_tail(new, pos);
···
 	}
 }
 
-/* 
- * Initialize all isochronous transfer parameters for an AGP 3.0 
- * node (i.e. a host bridge in combination with the adapters 
+/*
+ * Initialize all isochronous transfer parameters for an AGP 3.0
+ * node (i.e. a host bridge in combination with the adapters
  * lying behind it...)
  */
 
···
 	 * this to the hungriest device (as per the spec) */
 	rem  = target.n - tot_n;
 
-	/* 
+	/*
 	 * Calculate the minimum isochronous RQ depth needed by each master.
 	 * Along the way, distribute the extra ISOCH_N capability calculated
 	 * above.
···
 		 * many writes on the AGP bus).
 		 */
 		master[cdev].rq = master[cdev].n;
-		if(master[cdev].y > 0x1)
+		if (master[cdev].y > 0x1)
 			master[cdev].rq *= (1 << (master[cdev].y - 1));
 
 		tot_rq += master[cdev].rq;
···
 
 	arqsz     = (tstatus >> 13) & 0x7;
 
-	/* 
+	/*
 	 * Allocate a head for our AGP 3.5 device list
-	 * (multiple AGP v3 devices are allowed behind a single bridge). 
+	 * (multiple AGP v3 devices are allowed behind a single bridge).
 	 */
 	if ((dev_list = kmalloc(sizeof(*dev_list), GFP_KERNEL)) == NULL) {
 		ret = -ENOMEM;
···
 
 			case 0x0300:    /* Display controller */
 			case 0x0400:    /* Multimedia controller */
-				if((cur = kmalloc(sizeof(*cur), GFP_KERNEL)) == NULL) {
+				if ((cur = kmalloc(sizeof(*cur), GFP_KERNEL)) == NULL) {
 					ret = -ENOMEM;
 					goto free_and_exit;
 				}
···
 	list_for_each(pos, head) {
 		cur = list_entry(pos, struct agp_3_5_dev, list);
 		dev = cur->dev;
-		
+
 		pci_read_config_word(dev, PCI_STATUS, &mpstat);
 		if ((mpstat & PCI_STATUS_CAP_LIST) == 0)
 			continue;

drivers/char/agp/nvidia-agp.c

···
 	/* Find the iorr that is already used for the base */
 	/* If not found, determine the uppermost available iorr */
 	free_iorr_addr = AMD_K7_NUM_IORR;
-	for(iorr_addr = 0; iorr_addr < AMD_K7_NUM_IORR; iorr_addr++) {
+	for (iorr_addr = 0; iorr_addr < AMD_K7_NUM_IORR; iorr_addr++) {
 		rdmsr(IORR_BASE0 + 2 * iorr_addr, base_lo, base_hi);
 		rdmsr(IORR_MASK0 + 2 * iorr_addr, mask_lo, mask_hi);
 
···
 		if ((mask_lo & 0x00000800) == 0)
 			free_iorr_addr = iorr_addr;
 	}
-	
+
 	if (iorr_addr >= AMD_K7_NUM_IORR) {
 		iorr_addr = free_iorr_addr;
 		if (iorr_addr >= AMD_K7_NUM_IORR)
···
 	}
 
 	/* attbase */
-	for(i = 0; i < 8; i++) {
+	for (i = 0; i < 8; i++) {
 		pci_write_config_dword(nvidia_private.dev_2, NVIDIA_2_ATTBASE(i),
 			(agp_bridge->gatt_bus_addr + (i % num_dirs) * 64 * 1024) | 1);
 	}
···
 static int nvidia_insert_memory(struct agp_memory *mem, off_t pg_start, int type)
 {
 	int i, j;
-	
+
 	if ((type != 0) || (mem->type != 0))
 		return -EINVAL;
-	
+
 	if ((pg_start + mem->page_count) >
 		(nvidia_private.num_active_entries - agp_memory_reserved/PAGE_SIZE))
 		return -EINVAL;
-	
-	for(j = pg_start; j < (pg_start + mem->page_count); j++) {
+
+	for (j = pg_start; j < (pg_start + mem->page_count); j++) {
 		if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+nvidia_private.pg_offset+j)))
 			return -EBUSY;
 	}
···
 	}
 
 	/* flush TLB entries */
-	for(i = 0; i < 32 + 1; i++)
+	for (i = 0; i < 32 + 1; i++)
 		temp = readl(nvidia_private.aperture+(i * PAGE_SIZE / sizeof(u32)));
-	for(i = 0; i < 32 + 1; i++)
+	for (i = 0; i < 32 + 1; i++)
 		temp = readl(nvidia_private.aperture+(i * PAGE_SIZE / sizeof(u32)));
 }
 
···
 		pci_find_slot((unsigned int)pdev->bus->number, PCI_DEVFN(0, 2));
 	nvidia_private.dev_3 =
 		pci_find_slot((unsigned int)pdev->bus->number, PCI_DEVFN(30, 0));
-	
+
 	if (!nvidia_private.dev_1 || !nvidia_private.dev_2 || !nvidia_private.dev_3) {
 		printk(KERN_INFO PFX "Detected an NVIDIA nForce/nForce2 "
 			"chipset, but could not find the secondary devices.\n");

drivers/char/agp/sgi-agp.c

···
 
 static void __devexit agp_sgi_cleanup(void)
 {
-	if(sgi_tioca_agp_bridges)
+	if (sgi_tioca_agp_bridges)
 		kfree(sgi_tioca_agp_bridges);
 	sgi_tioca_agp_bridges=NULL;
 }

drivers/char/agp/sis-agp.c

···
 
 static struct agp_bridge_driver sis_driver = {
 	.owner			= THIS_MODULE,
-	.aperture_sizes 	= sis_generic_sizes,
+	.aperture_sizes		= sis_generic_sizes,
 	.size_type		= U8_APER_SIZE,
 	.num_aperture_sizes	= 7,
 	.configure		= sis_configure,
···
 {
 	int i;
 
-	for(i=0; sis_broken_chipsets[i]!=0; ++i)
-		if(bridge->dev->device==sis_broken_chipsets[i])
+	for (i=0; sis_broken_chipsets[i]!=0; ++i)
+		if (bridge->dev->device==sis_broken_chipsets[i])
 			break;
 
-	if(sis_broken_chipsets[i] || agp_sis_force_delay)
+	if (sis_broken_chipsets[i] || agp_sis_force_delay)
 		sis_driver.agp_enable=sis_delayed_enable;
 
 	// sis chipsets that indicate less than agp3.5

drivers/char/agp/sworks-agp.c

···
 	}
 	global_cache_flush();
 
-	for(i = 0; i < PAGE_SIZE / sizeof(unsigned long); i++)
+	for (i = 0; i < PAGE_SIZE / sizeof(unsigned long); i++)
 		writel(agp_bridge->scratch_page, page_map->remapped+i);
 
 	return 0;
···
 	struct serverworks_page_map *entry;
 
 	tables = serverworks_private.gatt_pages;
-	for(i = 0; i < serverworks_private.num_tables; i++) {
+	for (i = 0; i < serverworks_private.num_tables; i++) {
 		entry = tables[i];
 		if (entry != NULL) {
 			if (entry->real != NULL) {
···
 	int retval = 0;
 	int i;
 
-	tables = kzalloc((nr_tables + 1) * sizeof(struct serverworks_page_map *), 
+	tables = kzalloc((nr_tables + 1) * sizeof(struct serverworks_page_map *),
 			 GFP_KERNEL);
 	if (tables == NULL)
 		return -ENOMEM;
···
 		return retval;
 	}
 	/* Create a fake scratch directory */
-	for(i = 0; i < 1024; i++) {
+	for (i = 0; i < 1024; i++) {
 		writel(agp_bridge->scratch_page, serverworks_private.scratch_dir.remapped+i);
 		writel(virt_to_gart(serverworks_private.scratch_dir.real) | 1, page_dir.remapped+i);
 	}
···
 	pci_read_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs,&temp);
 	agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
 
-	/* Calculate the agp offset */	
-
-	for(i = 0; i < value->num_entries / 1024; i++)
+	/* Calculate the agp offset */
+	for (i = 0; i < value->num_entries / 1024; i++)
 		writel(virt_to_gart(serverworks_private.gatt_pages[i]->real)|1, page_dir.remapped+i);
 
 	return 0;
···
 static int serverworks_free_gatt_table(struct agp_bridge_data *bridge)
 {
 	struct serverworks_page_map page_dir;
-   
+
 	page_dir.real = (unsigned long *)agp_bridge->gatt_table_real;
 	page_dir.remapped = (unsigned long __iomem *)agp_bridge->gatt_table;
 

drivers/char/agp/uninorth-agp.c

···
 static int uninorth_configure(void)
 {
 	struct aper_size_info_32 *current_size;
-	
+
 	current_size = A_SIZE_32(agp_bridge->current_size);
 
 	printk(KERN_INFO PFX "configuring for size idx: %d\n",
 	       current_size->size_value);
-	
+
 	/* aperture size and gatt addr */
 	pci_write_config_dword(agp_bridge->dev,
 		UNI_N_CFG_GART_BASE,
···
 				       UNI_N_CFG_GART_DUMMY_PAGE,
 				       agp_bridge->scratch_page_real >> 12);
 	}
-	
+
 	return 0;
 }
 
···
 	}
 	(void)in_le32((volatile u32*)&agp_bridge->gatt_table[pg_start]);
 	mb();
-	flush_dcache_range((unsigned long)&agp_bridge->gatt_table[pg_start], 
+	flush_dcache_range((unsigned long)&agp_bridge->gatt_table[pg_start],
 		(unsigned long)&agp_bridge->gatt_table[pg_start + mem->page_count]);
 
 	uninorth_tlbflush(mem);
···
 
 	command = agp_collect_device_status(bridge, mode, status);
 	command |= PCI_AGP_COMMAND_AGP;
-	
+
 	if (uninorth_rev == 0x21) {
 		/*
 		 * Darwin disable AGP 4x on this revision, thus we
···
 	{256, 65536, 6, 64},
 	{128, 32768, 5, 32},
 	{64, 16384, 4, 16},
-#endif	
+#endif
 	{32, 8192, 3, 8},
 	{16, 4096, 2, 4},
 	{8, 2048, 1, 2},