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dt-bindings: ARM: Mediatek: Document bindings for MT2701

This patch adds the binding documentation for apmixedsys, bdpsys,
ethsys, hifsys, imgsys, infracfg, mmsys, pericfg, topckgen and
vdecsys for Mediatek MT2701.

Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
Signed-off-by: Erin Lo <erin.lo@mediatek.com>
Tested-by: John Crispin <blogic@openwrt.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

authored by

James Liao and committed by
Stephen Boyd
6a588703 2886c846

+82 -7
+2 -1
Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt
··· 5 5 6 6 Required Properties: 7 7 8 - - compatible: Should be: 8 + - compatible: Should be one of: 9 + - "mediatek,mt2701-apmixedsys" 9 10 - "mediatek,mt8135-apmixedsys" 10 11 - "mediatek,mt8173-apmixedsys" 11 12 - #clock-cells: Must be 1
+22
Documentation/devicetree/bindings/arm/mediatek/mediatek,bdpsys.txt
··· 1 + Mediatek bdpsys controller 2 + ============================ 3 + 4 + The Mediatek bdpsys controller provides various clocks to the system. 5 + 6 + Required Properties: 7 + 8 + - compatible: Should be: 9 + - "mediatek,mt2701-bdpsys", "syscon" 10 + - #clock-cells: Must be 1 11 + 12 + The bdpsys controller uses the common clk binding from 13 + Documentation/devicetree/bindings/clock/clock-bindings.txt 14 + The available clocks are defined in dt-bindings/clock/mt*-clk.h. 15 + 16 + Example: 17 + 18 + bdpsys: clock-controller@1c000000 { 19 + compatible = "mediatek,mt2701-bdpsys", "syscon"; 20 + reg = <0 0x1c000000 0 0x1000>; 21 + #clock-cells = <1>; 22 + };
+22
Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
··· 1 + Mediatek ethsys controller 2 + ============================ 3 + 4 + The Mediatek ethsys controller provides various clocks to the system. 5 + 6 + Required Properties: 7 + 8 + - compatible: Should be: 9 + - "mediatek,mt2701-ethsys", "syscon" 10 + - #clock-cells: Must be 1 11 + 12 + The ethsys controller uses the common clk binding from 13 + Documentation/devicetree/bindings/clock/clock-bindings.txt 14 + The available clocks are defined in dt-bindings/clock/mt*-clk.h. 15 + 16 + Example: 17 + 18 + ethsys: clock-controller@1b000000 { 19 + compatible = "mediatek,mt2701-ethsys", "syscon"; 20 + reg = <0 0x1b000000 0 0x1000>; 21 + #clock-cells = <1>; 22 + };
+24
Documentation/devicetree/bindings/arm/mediatek/mediatek,hifsys.txt
··· 1 + Mediatek hifsys controller 2 + ============================ 3 + 4 + The Mediatek hifsys controller provides various clocks and reset 5 + outputs to the system. 6 + 7 + Required Properties: 8 + 9 + - compatible: Should be: 10 + - "mediatek,mt2701-hifsys", "syscon" 11 + - #clock-cells: Must be 1 12 + 13 + The hifsys controller uses the common clk binding from 14 + Documentation/devicetree/bindings/clock/clock-bindings.txt 15 + The available clocks are defined in dt-bindings/clock/mt*-clk.h. 16 + 17 + Example: 18 + 19 + hifsys: clock-controller@1a000000 { 20 + compatible = "mediatek,mt2701-hifsys", "syscon"; 21 + reg = <0 0x1a000000 0 0x1000>; 22 + #clock-cells = <1>; 23 + #reset-cells = <1>; 24 + };
+2 -1
Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt
··· 5 5 6 6 Required Properties: 7 7 8 - - compatible: Should be: 8 + - compatible: Should be one of: 9 + - "mediatek,mt2701-imgsys", "syscon" 9 10 - "mediatek,mt8173-imgsys", "syscon" 10 11 - #clock-cells: Must be 1 11 12
+2 -1
Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt
··· 6 6 7 7 Required Properties: 8 8 9 - - compatible: Should be: 9 + - compatible: Should be one of: 10 + - "mediatek,mt2701-infracfg", "syscon" 10 11 - "mediatek,mt8135-infracfg", "syscon" 11 12 - "mediatek,mt8173-infracfg", "syscon" 12 13 - #clock-cells: Must be 1
+2 -1
Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt
··· 5 5 6 6 Required Properties: 7 7 8 - - compatible: Should be: 8 + - compatible: Should be one of: 9 + - "mediatek,mt2701-mmsys", "syscon" 9 10 - "mediatek,mt8173-mmsys", "syscon" 10 11 - #clock-cells: Must be 1 11 12
+2 -1
Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt
··· 6 6 7 7 Required Properties: 8 8 9 - - compatible: Should be: 9 + - compatible: Should be one of: 10 + - "mediatek,mt2701-pericfg", "syscon" 10 11 - "mediatek,mt8135-pericfg", "syscon" 11 12 - "mediatek,mt8173-pericfg", "syscon" 12 13 - #clock-cells: Must be 1
+2 -1
Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt
··· 5 5 6 6 Required Properties: 7 7 8 - - compatible: Should be: 8 + - compatible: Should be one of: 9 + - "mediatek,mt2701-topckgen" 9 10 - "mediatek,mt8135-topckgen" 10 11 - "mediatek,mt8173-topckgen" 11 12 - #clock-cells: Must be 1
+2 -1
Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys.txt
··· 5 5 6 6 Required Properties: 7 7 8 - - compatible: Should be: 8 + - compatible: Should be one of: 9 + - "mediatek,mt2701-vdecsys", "syscon" 9 10 - "mediatek,mt8173-vdecsys", "syscon" 10 11 - #clock-cells: Must be 1 11 12