drm/i915: Convert intel_cursor.c to struct intel_display

+1 -1

drivers/gpu/drm/i915/display/intel_crtc.c

··· 344 344 crtc->plane_ids_mask |= BIT(plane->id); 345 345 } 346 346 347 - cursor = intel_cursor_plane_create(dev_priv, pipe); 347 + cursor = intel_cursor_plane_create(display, pipe); 348 348 if (IS_ERR(cursor)) { 349 349 ret = PTR_ERR(cursor); 350 350 goto fail;

+63 -73

drivers/gpu/drm/i915/display/intel_cursor.c

··· 35 35 36 36 static u32 intel_cursor_base(const struct intel_plane_state *plane_state) 37 37 { 38 - struct drm_i915_private *dev_priv = 39 - to_i915(plane_state->uapi.plane->dev); 38 + struct intel_display *display = to_intel_display(plane_state); 40 39 u32 base; 41 40 42 - if (DISPLAY_INFO(dev_priv)->cursor_needs_physical) 41 + if (DISPLAY_INFO(display)->cursor_needs_physical) 43 42 base = plane_state->phys_dma_addr; 44 43 else 45 44 base = intel_plane_ggtt_offset(plane_state); ··· 91 92 92 93 static int intel_cursor_check_surface(struct intel_plane_state *plane_state) 93 94 { 94 - struct drm_i915_private *dev_priv = 95 - to_i915(plane_state->uapi.plane->dev); 95 + struct intel_display *display = to_intel_display(plane_state); 96 96 unsigned int rotation = plane_state->hw.rotation; 97 97 int src_x, src_y; 98 98 u32 offset; ··· 112 114 plane_state, 0); 113 115 114 116 if (src_x != 0 || src_y != 0) { 115 - drm_dbg_kms(&dev_priv->drm, 117 + drm_dbg_kms(display->drm, 116 118 "Arbitrary cursor panning not supported\n"); 117 119 return -EINVAL; 118 120 } ··· 125 127 src_x << 16, src_y << 16); 126 128 127 129 /* ILK+ do this automagically in hardware */ 128 - if (HAS_GMCH(dev_priv) && rotation & DRM_MODE_ROTATE_180) { 130 + if (HAS_GMCH(display) && rotation & DRM_MODE_ROTATE_180) { 129 131 const struct drm_framebuffer *fb = plane_state->hw.fb; 130 132 int src_w = drm_rect_width(&plane_state->uapi.src) >> 16; 131 133 int src_h = drm_rect_height(&plane_state->uapi.src) >> 16; ··· 143 145 static int intel_check_cursor(struct intel_crtc_state *crtc_state, 144 146 struct intel_plane_state *plane_state) 145 147 { 148 + struct intel_display *display = to_intel_display(plane_state); 146 149 const struct drm_framebuffer *fb = plane_state->hw.fb; 147 - struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); 148 150 const struct drm_rect src = plane_state->uapi.src; 149 151 const struct drm_rect dst = plane_state->uapi.dst; 150 152 int ret; 151 153 152 154 if (fb && fb->modifier != DRM_FORMAT_MOD_LINEAR) { 153 - drm_dbg_kms(&i915->drm, "cursor cannot be tiled\n"); 155 + drm_dbg_kms(display->drm, "cursor cannot be tiled\n"); 154 156 return -EINVAL; 155 157 } 156 158 ··· 231 233 static int i845_check_cursor(struct intel_crtc_state *crtc_state, 232 234 struct intel_plane_state *plane_state) 233 235 { 236 + struct intel_display *display = to_intel_display(plane_state); 234 237 const struct drm_framebuffer *fb = plane_state->hw.fb; 235 - struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); 236 238 int ret; 237 239 238 240 ret = intel_check_cursor(crtc_state, plane_state); ··· 245 247 246 248 /* Check for which cursor types we support */ 247 249 if (!i845_cursor_size_ok(plane_state)) { 248 - drm_dbg_kms(&i915->drm, 250 + drm_dbg_kms(display->drm, 249 251 "Cursor dimension %dx%d not supported\n", 250 252 drm_rect_width(&plane_state->uapi.dst), 251 253 drm_rect_height(&plane_state->uapi.dst)); 252 254 return -EINVAL; 253 255 } 254 256 255 - drm_WARN_ON(&i915->drm, plane_state->uapi.visible && 257 + drm_WARN_ON(display->drm, plane_state->uapi.visible && 256 258 plane_state->view.color_plane[0].mapping_stride != fb->pitches[0]); 257 259 258 260 switch (fb->pitches[0]) { ··· 262 264 case 2048: 263 265 break; 264 266 default: 265 - drm_dbg_kms(&i915->drm, "Invalid cursor stride (%u)\n", 267 + drm_dbg_kms(display->drm, "Invalid cursor stride (%u)\n", 266 268 fb->pitches[0]); 267 269 return -EINVAL; 268 270 } ··· 278 280 const struct intel_crtc_state *crtc_state, 279 281 const struct intel_plane_state *plane_state) 280 282 { 281 - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 283 + struct intel_display *display = to_intel_display(plane); 282 284 u32 cntl = 0, base = 0, pos = 0, size = 0; 283 285 284 286 if (plane_state && plane_state->uapi.visible) { ··· 300 302 if (plane->cursor.base != base || 301 303 plane->cursor.size != size || 302 304 plane->cursor.cntl != cntl) { 303 - intel_de_write_fw(dev_priv, CURCNTR(dev_priv, PIPE_A), 0); 304 - intel_de_write_fw(dev_priv, CURBASE(dev_priv, PIPE_A), base); 305 - intel_de_write_fw(dev_priv, CURSIZE(dev_priv, PIPE_A), size); 306 - intel_de_write_fw(dev_priv, CURPOS(dev_priv, PIPE_A), pos); 307 - intel_de_write_fw(dev_priv, CURCNTR(dev_priv, PIPE_A), cntl); 305 + intel_de_write_fw(display, CURCNTR(display, PIPE_A), 0); 306 + intel_de_write_fw(display, CURBASE(display, PIPE_A), base); 307 + intel_de_write_fw(display, CURSIZE(display, PIPE_A), size); 308 + intel_de_write_fw(display, CURPOS(display, PIPE_A), pos); 309 + intel_de_write_fw(display, CURCNTR(display, PIPE_A), cntl); 308 310 309 311 plane->cursor.base = base; 310 312 plane->cursor.size = size; 311 313 plane->cursor.cntl = cntl; 312 314 } else { 313 - intel_de_write_fw(dev_priv, CURPOS(dev_priv, PIPE_A), pos); 315 + intel_de_write_fw(display, CURPOS(display, PIPE_A), pos); 314 316 } 315 317 } 316 318 ··· 325 327 enum pipe *pipe) 326 328 { 327 329 struct intel_display *display = to_intel_display(plane); 328 - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 329 330 enum intel_display_power_domain power_domain; 330 331 intel_wakeref_t wakeref; 331 332 bool ret; ··· 334 337 if (!wakeref) 335 338 return false; 336 339 337 - ret = intel_de_read(dev_priv, CURCNTR(dev_priv, PIPE_A)) & CURSOR_ENABLE; 340 + ret = intel_de_read(display, CURCNTR(display, PIPE_A)) & CURSOR_ENABLE; 338 341 339 342 *pipe = PIPE_A; 340 343 ··· 380 383 381 384 static u32 i9xx_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state) 382 385 { 386 + struct intel_display *display = to_intel_display(crtc_state); 383 387 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 384 - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 385 388 u32 cntl = 0; 386 389 387 - if (DISPLAY_VER(dev_priv) >= 11) 390 + if (DISPLAY_VER(display) >= 11) 388 391 return cntl; 389 392 390 393 if (crtc_state->gamma_enable) ··· 393 396 if (crtc_state->csc_enable) 394 397 cntl |= MCURSOR_PIPE_CSC_ENABLE; 395 398 396 - if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv)) 399 + if (DISPLAY_VER(display) < 5 && !display->platform.g4x) 397 400 cntl |= MCURSOR_PIPE_SEL(crtc->pipe); 398 401 399 402 return cntl; ··· 402 405 static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state, 403 406 const struct intel_plane_state *plane_state) 404 407 { 405 - struct drm_i915_private *dev_priv = 406 - to_i915(plane_state->uapi.plane->dev); 408 + struct intel_display *display = to_intel_display(plane_state); 407 409 u32 cntl = 0; 408 410 409 - if (IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv)) 411 + if (display->platform.sandybridge || display->platform.ivybridge) 410 412 cntl |= MCURSOR_TRICKLE_FEED_DISABLE; 411 413 412 414 switch (drm_rect_width(&plane_state->uapi.dst)) { ··· 427 431 cntl |= MCURSOR_ROTATE_180; 428 432 429 433 /* Wa_22012358565:adl-p */ 430 - if (DISPLAY_VER(dev_priv) == 13) 434 + if (DISPLAY_VER(display) == 13) 431 435 cntl |= MCURSOR_ARB_SLOTS(1); 432 436 433 437 return cntl; ··· 435 439 436 440 static bool i9xx_cursor_size_ok(const struct intel_plane_state *plane_state) 437 441 { 438 - struct drm_i915_private *dev_priv = 439 - to_i915(plane_state->uapi.plane->dev); 442 + struct intel_display *display = to_intel_display(plane_state); 440 443 int width = drm_rect_width(&plane_state->uapi.dst); 441 444 int height = drm_rect_height(&plane_state->uapi.dst); 442 445 ··· 458 463 * cursor is not rotated. Everything else requires square 459 464 * cursors. 460 465 */ 461 - if (HAS_CUR_FBC(dev_priv) && 466 + if (HAS_CUR_FBC(display) && 462 467 plane_state->hw.rotation & DRM_MODE_ROTATE_0) { 463 468 if (height < 8 || height > width) 464 469 return false; ··· 473 478 static int i9xx_check_cursor(struct intel_crtc_state *crtc_state, 474 479 struct intel_plane_state *plane_state) 475 480 { 481 + struct intel_display *display = to_intel_display(plane_state); 476 482 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 477 - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 478 483 const struct drm_framebuffer *fb = plane_state->hw.fb; 479 484 enum pipe pipe = plane->pipe; 480 485 int ret; ··· 489 494 490 495 /* Check for which cursor types we support */ 491 496 if (!i9xx_cursor_size_ok(plane_state)) { 492 - drm_dbg(&dev_priv->drm, 497 + drm_dbg(display->drm, 493 498 "Cursor dimension %dx%d not supported\n", 494 499 drm_rect_width(&plane_state->uapi.dst), 495 500 drm_rect_height(&plane_state->uapi.dst)); 496 501 return -EINVAL; 497 502 } 498 503 499 - drm_WARN_ON(&dev_priv->drm, plane_state->uapi.visible && 504 + drm_WARN_ON(display->drm, plane_state->uapi.visible && 500 505 plane_state->view.color_plane[0].mapping_stride != fb->pitches[0]); 501 506 502 507 if (fb->pitches[0] != 503 508 drm_rect_width(&plane_state->uapi.dst) * fb->format->cpp[0]) { 504 - drm_dbg_kms(&dev_priv->drm, 509 + drm_dbg_kms(display->drm, 505 510 "Invalid cursor stride (%u) (cursor width %d)\n", 506 511 fb->pitches[0], 507 512 drm_rect_width(&plane_state->uapi.dst)); ··· 518 523 * display power well must be turned off and on again. 519 524 * Refuse the put the cursor into that compromised position. 520 525 */ 521 - if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_C && 526 + if (display->platform.cherryview && pipe == PIPE_C && 522 527 plane_state->uapi.visible && plane_state->uapi.dst.x1 < 0) { 523 - drm_dbg_kms(&dev_priv->drm, 528 + drm_dbg_kms(display->drm, 524 529 "CHV cursor C not allowed to straddle the left screen edge\n"); 525 530 return -EINVAL; 526 531 } ··· 534 539 struct intel_plane *plane, 535 540 const struct intel_crtc_state *crtc_state) 536 541 { 537 - struct intel_display *display = to_intel_display(plane->base.dev); 542 + struct intel_display *display = to_intel_display(plane); 538 543 enum pipe pipe = plane->pipe; 539 544 540 545 if (!crtc_state->enable_psr2_sel_fetch) ··· 548 553 const struct intel_crtc_state *crtc_state, 549 554 const struct intel_plane_state *plane_state) 550 555 { 551 - struct intel_display *display = to_intel_display(plane->base.dev); 552 - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 556 + struct intel_display *display = to_intel_display(plane); 553 557 u32 ctl = plane_state->ctl; 554 558 int et_y_position = drm_rect_height(&crtc_state->pipe_src) + 1; 555 559 enum pipe pipe = plane->pipe; ··· 558 564 559 565 intel_de_write_dsb(display, dsb, SEL_FETCH_CUR_CTL(pipe), ctl); 560 566 561 - intel_de_write_dsb(display, dsb, CURPOS_ERLY_TPT(dev_priv, pipe), 567 + intel_de_write_dsb(display, dsb, CURPOS_ERLY_TPT(display, pipe), 562 568 CURSOR_POS_Y(et_y_position)); 563 569 } 564 570 ··· 567 573 const struct intel_crtc_state *crtc_state, 568 574 const struct intel_plane_state *plane_state) 569 575 { 570 - struct intel_display *display = to_intel_display(plane->base.dev); 571 - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 576 + struct intel_display *display = to_intel_display(plane); 572 577 enum pipe pipe = plane->pipe; 573 578 574 579 if (!crtc_state->enable_psr2_sel_fetch) ··· 578 585 u32 val = intel_cursor_position(crtc_state, plane_state, 579 586 true); 580 587 581 - intel_de_write_dsb(display, dsb, CURPOS_ERLY_TPT(dev_priv, pipe), val); 588 + intel_de_write_dsb(display, dsb, CURPOS_ERLY_TPT(display, pipe), val); 582 589 } 583 590 584 591 intel_de_write_dsb(display, dsb, SEL_FETCH_CUR_CTL(pipe), plane_state->ctl); ··· 652 659 const struct intel_crtc_state *crtc_state, 653 660 const struct intel_plane_state *plane_state) 654 661 { 655 - struct intel_display *display = to_intel_display(plane->base.dev); 656 - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 662 + struct intel_display *display = to_intel_display(plane); 657 663 enum pipe pipe = plane->pipe; 658 664 u32 cntl = 0, base = 0, pos = 0, fbc_ctl = 0; 659 665 ··· 690 698 * the CURCNTR write arms the update. 691 699 */ 692 700 693 - if (DISPLAY_VER(dev_priv) >= 9) 701 + if (DISPLAY_VER(display) >= 9) 694 702 skl_write_cursor_wm(dsb, plane, crtc_state); 695 703 696 704 if (plane_state) ··· 701 709 if (plane->cursor.base != base || 702 710 plane->cursor.size != fbc_ctl || 703 711 plane->cursor.cntl != cntl) { 704 - if (HAS_CUR_FBC(dev_priv)) 705 - intel_de_write_dsb(display, dsb, CUR_FBC_CTL(dev_priv, pipe), fbc_ctl); 706 - intel_de_write_dsb(display, dsb, CURCNTR(dev_priv, pipe), cntl); 707 - intel_de_write_dsb(display, dsb, CURPOS(dev_priv, pipe), pos); 708 - intel_de_write_dsb(display, dsb, CURBASE(dev_priv, pipe), base); 712 + if (HAS_CUR_FBC(display)) 713 + intel_de_write_dsb(display, dsb, CUR_FBC_CTL(display, pipe), fbc_ctl); 714 + intel_de_write_dsb(display, dsb, CURCNTR(display, pipe), cntl); 715 + intel_de_write_dsb(display, dsb, CURPOS(display, pipe), pos); 716 + intel_de_write_dsb(display, dsb, CURBASE(display, pipe), base); 709 717 710 718 plane->cursor.base = base; 711 719 plane->cursor.size = fbc_ctl; 712 720 plane->cursor.cntl = cntl; 713 721 } else { 714 - intel_de_write_dsb(display, dsb, CURPOS(dev_priv, pipe), pos); 715 - intel_de_write_dsb(display, dsb, CURBASE(dev_priv, pipe), base); 722 + intel_de_write_dsb(display, dsb, CURPOS(display, pipe), pos); 723 + intel_de_write_dsb(display, dsb, CURBASE(display, pipe), base); 716 724 } 717 725 } 718 726 ··· 727 735 enum pipe *pipe) 728 736 { 729 737 struct intel_display *display = to_intel_display(plane); 730 - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 731 738 enum intel_display_power_domain power_domain; 732 739 intel_wakeref_t wakeref; 733 740 bool ret; ··· 742 751 if (!wakeref) 743 752 return false; 744 753 745 - val = intel_de_read(dev_priv, CURCNTR(dev_priv, plane->pipe)); 754 + val = intel_de_read(display, CURCNTR(display, plane->pipe)); 746 755 747 756 ret = val & MCURSOR_MODE_MASK; 748 757 749 - if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) 758 + if (DISPLAY_VER(display) >= 5 || display->platform.g4x) 750 759 *pipe = plane->pipe; 751 760 else 752 761 *pipe = REG_FIELD_GET(MCURSOR_PIPE_SEL_MASK, val); ··· 788 797 { 789 798 struct intel_plane *plane = to_intel_plane(_plane); 790 799 struct intel_crtc *crtc = to_intel_crtc(_crtc); 791 - struct drm_i915_private *i915 = to_i915(plane->base.dev); 800 + struct intel_display *display = to_intel_display(plane); 792 801 struct intel_plane_state *old_plane_state = 793 802 to_intel_plane_state(plane->base.state); 794 803 struct intel_plane_state *new_plane_state; ··· 892 901 893 902 intel_psr_lock(crtc_state); 894 903 895 - if (!drm_WARN_ON(&i915->drm, drm_crtc_vblank_get(&crtc->base))) { 904 + if (!drm_WARN_ON(display->drm, drm_crtc_vblank_get(&crtc->base))) { 896 905 /* 897 906 * TODO: maybe check if we're still in PSR 898 907 * and skip the vblank evasion entirely? ··· 958 967 959 968 static void intel_cursor_add_size_hints_property(struct intel_plane *plane) 960 969 { 961 - struct drm_i915_private *i915 = to_i915(plane->base.dev); 962 - const struct drm_mode_config *config = &i915->drm.mode_config; 970 + struct intel_display *display = to_intel_display(plane); 971 + const struct drm_mode_config *config = &display->drm->mode_config; 963 972 struct drm_plane_size_hint hints[4]; 964 973 int size, max_size, num_hints = 0; 965 974 ··· 967 976 968 977 /* for simplicity only enumerate the supported square+POT sizes */ 969 978 for (size = 64; size <= max_size; size *= 2) { 970 - if (drm_WARN_ON(&i915->drm, num_hints >= ARRAY_SIZE(hints))) 979 + if (drm_WARN_ON(display->drm, num_hints >= ARRAY_SIZE(hints))) 971 980 break; 972 981 973 982 hints[num_hints].width = size; ··· 979 988 } 980 989 981 990 struct intel_plane * 982 - intel_cursor_plane_create(struct drm_i915_private *dev_priv, 991 + intel_cursor_plane_create(struct intel_display *display, 983 992 enum pipe pipe) 984 993 { 985 - struct intel_display *display = &dev_priv->display; 986 994 struct intel_plane *cursor; 987 995 int ret, zpos; 988 996 u64 *modifiers; ··· 995 1005 cursor->id = PLANE_CURSOR; 996 1006 cursor->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, cursor->id); 997 1007 998 - if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) { 1008 + if (display->platform.i845g || display->platform.i865g) { 999 1009 cursor->max_stride = i845_cursor_max_stride; 1000 1010 cursor->min_alignment = i845_cursor_min_alignment; 1001 1011 cursor->update_arm = i845_cursor_update_arm; ··· 1005 1015 } else { 1006 1016 cursor->max_stride = i9xx_cursor_max_stride; 1007 1017 1008 - if (IS_I830(dev_priv)) 1018 + if (display->platform.i830) 1009 1019 cursor->min_alignment = i830_cursor_min_alignment; 1010 - else if (IS_I85X(dev_priv)) 1020 + else if (display->platform.i85x) 1011 1021 cursor->min_alignment = i85x_cursor_min_alignment; 1012 1022 else 1013 1023 cursor->min_alignment = i9xx_cursor_min_alignment; ··· 1024 1034 cursor->cursor.base = ~0; 1025 1035 cursor->cursor.cntl = ~0; 1026 1036 1027 - if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv)) 1037 + if (display->platform.i845g || display->platform.i865g || HAS_CUR_FBC(display)) 1028 1038 cursor->cursor.size = ~0; 1029 1039 1030 1040 modifiers = intel_fb_plane_get_modifiers(display, INTEL_PLANE_CAP_NONE); 1031 1041 1032 - ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base, 1042 + ret = drm_universal_plane_init(display->drm, &cursor->base, 1033 1043 0, &intel_cursor_plane_funcs, 1034 1044 intel_cursor_formats, 1035 1045 ARRAY_SIZE(intel_cursor_formats), ··· 1042 1052 if (ret) 1043 1053 goto fail; 1044 1054 1045 - if (DISPLAY_VER(dev_priv) >= 4) 1055 + if (DISPLAY_VER(display) >= 4) 1046 1056 drm_plane_create_rotation_property(&cursor->base, 1047 1057 DRM_MODE_ROTATE_0, 1048 1058 DRM_MODE_ROTATE_0 | ··· 1050 1060 1051 1061 intel_cursor_add_size_hints_property(cursor); 1052 1062 1053 - zpos = DISPLAY_RUNTIME_INFO(dev_priv)->num_sprites[pipe] + 1; 1063 + zpos = DISPLAY_RUNTIME_INFO(display)->num_sprites[pipe] + 1; 1054 1064 drm_plane_create_zpos_immutable_property(&cursor->base, zpos); 1055 1065 1056 - if (DISPLAY_VER(dev_priv) >= 12) 1066 + if (DISPLAY_VER(display) >= 12) 1057 1067 drm_plane_enable_fb_damage_clips(&cursor->base); 1058 1068 1059 1069 intel_plane_helper_add(cursor);

+2 -2

drivers/gpu/drm/i915/display/intel_cursor.h

··· 7 7 #define _INTEL_CURSOR_H_ 8 8 9 9 enum pipe; 10 - struct drm_i915_private; 10 + struct intel_display; 11 11 struct intel_plane; 12 12 struct kthread_work; 13 13 14 14 struct intel_plane * 15 - intel_cursor_plane_create(struct drm_i915_private *dev_priv, 15 + intel_cursor_plane_create(struct intel_display *display, 16 16 enum pipe pipe); 17 17 18 18 void intel_cursor_unpin_work(struct kthread_work *base);