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linux
iio: dac: ad7303: Fix alignment for DMA safety
____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1. Switch to the updated
IIO_DMA_MINALIGN definition.
Update the comment to include 'may'.
Fixes: f83478240e74 ("iio:dac: Add support for the AD7303")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Acked-by: Nuno Sá <nuno.sa@analog.com>
Link: https://lore.kernel.org/r/20220508175712.647246-58-jic23@kernel.org
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drivers/iio/dac/ad7303.c
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drivers/iio/dac/ad7303.c
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struct mutex lock;
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/*
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* DMA (thus cache coherency maintenance) requires the
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* DMA (thus cache coherency maintenance) may require the
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* transfer buffers to live in their own cache lines.
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*/
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__be16 data ____cacheline_aligned;
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__be16 data __aligned(IIO_DMA_MINALIGN);
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};
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static int ad7303_write(struct ad7303_state *st, unsigned int chan,