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ARM: dts: imx: Align L2 cache-controller nodename with dtschema

Fix dtschema validator warnings like:
l2-cache@a02000: $nodename:0:
'l2-cache@a02000' does not match '^(cache-controller|cpu)(@[0-9a-f,]+)*$'

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

authored by

Krzysztof Kozlowski and committed by
Shawn Guo 69cc1502 954809fb

+5 -5
+1 -1
arch/arm/boot/dts/imx35.dtsi
··· 59 59 interrupt-parent = <&avic>; 60 60 ranges; 61 61 62 - L2: l2-cache@30000000 { 62 + L2: cache-controller@30000000 { 63 63 compatible = "arm,l210-cache"; 64 64 reg = <0x30000000 0x1000>; 65 65 cache-unified;
+1 -1
arch/arm/boot/dts/imx6qdl.dtsi
··· 245 245 interrupt-parent = <&intc>; 246 246 }; 247 247 248 - L2: l2-cache@a02000 { 248 + L2: cache-controller@a02000 { 249 249 compatible = "arm,pl310-cache"; 250 250 reg = <0x00a02000 0x1000>; 251 251 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
+1 -1
arch/arm/boot/dts/imx6sl.dtsi
··· 126 126 interrupt-parent = <&intc>; 127 127 }; 128 128 129 - L2: l2-cache@a02000 { 129 + L2: cache-controller@a02000 { 130 130 compatible = "arm,pl310-cache"; 131 131 reg = <0x00a02000 0x1000>; 132 132 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
+1 -1
arch/arm/boot/dts/imx6sll.dtsi
··· 126 126 interrupt-parent = <&intc>; 127 127 }; 128 128 129 - L2: l2-cache@a02000 { 129 + L2: cache-controller@a02000 { 130 130 compatible = "arm,pl310-cache"; 131 131 reg = <0x00a02000 0x1000>; 132 132 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+1 -1
arch/arm/boot/dts/imx6sx.dtsi
··· 179 179 interrupt-parent = <&intc>; 180 180 }; 181 181 182 - L2: l2-cache@a02000 { 182 + L2: cache-controller@a02000 { 183 183 compatible = "arm,pl310-cache"; 184 184 reg = <0x00a02000 0x1000>; 185 185 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;