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Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
pinctrl: rockchip: Add rk3576 pinctrl support
Add support for the 5 rk3576 GPIO banks.
Signed-off-by: Steven Liu <steven.liu@rock-chips.com>
Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com>
Acked-by: Dragan Simic <dsimic@manjaro.org>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/20240822195706.920567-5-detlev.casanova@collabora.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
authored by
Steven Liu
and committed by
Linus Walleij
69c6343e
12330590
+208
+207
drivers/pinctrl/pinctrl-rockchip.c
+207
drivers/pinctrl/pinctrl-rockchip.c
···
84
84
}, \
85
85
}
86
86
87
+
#define PIN_BANK_IOMUX_FLAGS_OFFSET_PULL_FLAGS(id, pins, label, iom0, \
88
+
iom1, iom2, iom3, \
89
+
offset0, offset1, \
90
+
offset2, offset3, pull0, \
91
+
pull1, pull2, pull3) \
92
+
{ \
93
+
.bank_num = id, \
94
+
.nr_pins = pins, \
95
+
.name = label, \
96
+
.iomux = { \
97
+
{ .type = iom0, .offset = offset0 }, \
98
+
{ .type = iom1, .offset = offset1 }, \
99
+
{ .type = iom2, .offset = offset2 }, \
100
+
{ .type = iom3, .offset = offset3 }, \
101
+
}, \
102
+
.pull_type[0] = pull0, \
103
+
.pull_type[1] = pull1, \
104
+
.pull_type[2] = pull2, \
105
+
.pull_type[3] = pull3, \
106
+
}
107
+
87
108
#define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \
88
109
{ \
89
110
.bank_num = id, \
···
1141
1120
if (bank->recalced_mask & BIT(pin))
1142
1121
rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask);
1143
1122
1123
+
if (ctrl->type == RK3576) {
1124
+
if ((bank->bank_num == 0) && (pin >= RK_PB4) && (pin <= RK_PB7))
1125
+
reg += 0x1ff4; /* GPIO0_IOC_GPIO0B_IOMUX_SEL_H */
1126
+
}
1127
+
1144
1128
if (ctrl->type == RK3588) {
1145
1129
if (bank->bank_num == 0) {
1146
1130
if ((pin >= RK_PB4) && (pin <= RK_PD7)) {
···
1259
1233
1260
1234
if (bank->recalced_mask & BIT(pin))
1261
1235
rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask);
1236
+
1237
+
if (ctrl->type == RK3576) {
1238
+
if ((bank->bank_num == 0) && (pin >= RK_PB4) && (pin <= RK_PB7))
1239
+
reg += 0x1ff4; /* GPIO0_IOC_GPIO0B_IOMUX_SEL_H */
1240
+
}
1262
1241
1263
1242
if (ctrl->type == RK3588) {
1264
1243
if (bank->bank_num == 0) {
···
2069
2038
return 0;
2070
2039
}
2071
2040
2041
+
#define RK3576_DRV_BITS_PER_PIN 4
2042
+
#define RK3576_DRV_PINS_PER_REG 4
2043
+
#define RK3576_DRV_GPIO0_AL_OFFSET 0x10
2044
+
#define RK3576_DRV_GPIO0_BH_OFFSET 0x2014
2045
+
#define RK3576_DRV_GPIO1_OFFSET 0x6020
2046
+
#define RK3576_DRV_GPIO2_OFFSET 0x6040
2047
+
#define RK3576_DRV_GPIO3_OFFSET 0x6060
2048
+
#define RK3576_DRV_GPIO4_AL_OFFSET 0x6080
2049
+
#define RK3576_DRV_GPIO4_CL_OFFSET 0xA090
2050
+
#define RK3576_DRV_GPIO4_DL_OFFSET 0xB098
2051
+
2052
+
static int rk3576_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
2053
+
int pin_num, struct regmap **regmap,
2054
+
int *reg, u8 *bit)
2055
+
{
2056
+
struct rockchip_pinctrl *info = bank->drvdata;
2057
+
2058
+
*regmap = info->regmap_base;
2059
+
2060
+
if (bank->bank_num == 0 && pin_num < 12)
2061
+
*reg = RK3576_DRV_GPIO0_AL_OFFSET;
2062
+
else if (bank->bank_num == 0)
2063
+
*reg = RK3576_DRV_GPIO0_BH_OFFSET - 0xc;
2064
+
else if (bank->bank_num == 1)
2065
+
*reg = RK3576_DRV_GPIO1_OFFSET;
2066
+
else if (bank->bank_num == 2)
2067
+
*reg = RK3576_DRV_GPIO2_OFFSET;
2068
+
else if (bank->bank_num == 3)
2069
+
*reg = RK3576_DRV_GPIO3_OFFSET;
2070
+
else if (bank->bank_num == 4 && pin_num < 16)
2071
+
*reg = RK3576_DRV_GPIO4_AL_OFFSET;
2072
+
else if (bank->bank_num == 4 && pin_num < 24)
2073
+
*reg = RK3576_DRV_GPIO4_CL_OFFSET - 0x10;
2074
+
else if (bank->bank_num == 4)
2075
+
*reg = RK3576_DRV_GPIO4_DL_OFFSET - 0x18;
2076
+
else
2077
+
dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
2078
+
2079
+
*reg += ((pin_num / RK3576_DRV_PINS_PER_REG) * 4);
2080
+
*bit = pin_num % RK3576_DRV_PINS_PER_REG;
2081
+
*bit *= RK3576_DRV_BITS_PER_PIN;
2082
+
2083
+
return 0;
2084
+
}
2085
+
2086
+
#define RK3576_PULL_BITS_PER_PIN 2
2087
+
#define RK3576_PULL_PINS_PER_REG 8
2088
+
#define RK3576_PULL_GPIO0_AL_OFFSET 0x20
2089
+
#define RK3576_PULL_GPIO0_BH_OFFSET 0x2028
2090
+
#define RK3576_PULL_GPIO1_OFFSET 0x6110
2091
+
#define RK3576_PULL_GPIO2_OFFSET 0x6120
2092
+
#define RK3576_PULL_GPIO3_OFFSET 0x6130
2093
+
#define RK3576_PULL_GPIO4_AL_OFFSET 0x6140
2094
+
#define RK3576_PULL_GPIO4_CL_OFFSET 0xA148
2095
+
#define RK3576_PULL_GPIO4_DL_OFFSET 0xB14C
2096
+
2097
+
static int rk3576_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
2098
+
int pin_num, struct regmap **regmap,
2099
+
int *reg, u8 *bit)
2100
+
{
2101
+
struct rockchip_pinctrl *info = bank->drvdata;
2102
+
2103
+
*regmap = info->regmap_base;
2104
+
2105
+
if (bank->bank_num == 0 && pin_num < 12)
2106
+
*reg = RK3576_PULL_GPIO0_AL_OFFSET;
2107
+
else if (bank->bank_num == 0)
2108
+
*reg = RK3576_PULL_GPIO0_BH_OFFSET - 0x4;
2109
+
else if (bank->bank_num == 1)
2110
+
*reg = RK3576_PULL_GPIO1_OFFSET;
2111
+
else if (bank->bank_num == 2)
2112
+
*reg = RK3576_PULL_GPIO2_OFFSET;
2113
+
else if (bank->bank_num == 3)
2114
+
*reg = RK3576_PULL_GPIO3_OFFSET;
2115
+
else if (bank->bank_num == 4 && pin_num < 16)
2116
+
*reg = RK3576_PULL_GPIO4_AL_OFFSET;
2117
+
else if (bank->bank_num == 4 && pin_num < 24)
2118
+
*reg = RK3576_PULL_GPIO4_CL_OFFSET - 0x8;
2119
+
else if (bank->bank_num == 4)
2120
+
*reg = RK3576_PULL_GPIO4_DL_OFFSET - 0xc;
2121
+
else
2122
+
dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
2123
+
2124
+
*reg += ((pin_num / RK3576_PULL_PINS_PER_REG) * 4);
2125
+
*bit = pin_num % RK3576_PULL_PINS_PER_REG;
2126
+
*bit *= RK3576_PULL_BITS_PER_PIN;
2127
+
2128
+
return 0;
2129
+
}
2130
+
2131
+
#define RK3576_SMT_BITS_PER_PIN 1
2132
+
#define RK3576_SMT_PINS_PER_REG 8
2133
+
#define RK3576_SMT_GPIO0_AL_OFFSET 0x30
2134
+
#define RK3576_SMT_GPIO0_BH_OFFSET 0x2040
2135
+
#define RK3576_SMT_GPIO1_OFFSET 0x6210
2136
+
#define RK3576_SMT_GPIO2_OFFSET 0x6220
2137
+
#define RK3576_SMT_GPIO3_OFFSET 0x6230
2138
+
#define RK3576_SMT_GPIO4_AL_OFFSET 0x6240
2139
+
#define RK3576_SMT_GPIO4_CL_OFFSET 0xA248
2140
+
#define RK3576_SMT_GPIO4_DL_OFFSET 0xB24C
2141
+
2142
+
static int rk3576_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
2143
+
int pin_num,
2144
+
struct regmap **regmap,
2145
+
int *reg, u8 *bit)
2146
+
{
2147
+
struct rockchip_pinctrl *info = bank->drvdata;
2148
+
2149
+
*regmap = info->regmap_base;
2150
+
2151
+
if (bank->bank_num == 0 && pin_num < 12)
2152
+
*reg = RK3576_SMT_GPIO0_AL_OFFSET;
2153
+
else if (bank->bank_num == 0)
2154
+
*reg = RK3576_SMT_GPIO0_BH_OFFSET - 0x4;
2155
+
else if (bank->bank_num == 1)
2156
+
*reg = RK3576_SMT_GPIO1_OFFSET;
2157
+
else if (bank->bank_num == 2)
2158
+
*reg = RK3576_SMT_GPIO2_OFFSET;
2159
+
else if (bank->bank_num == 3)
2160
+
*reg = RK3576_SMT_GPIO3_OFFSET;
2161
+
else if (bank->bank_num == 4 && pin_num < 16)
2162
+
*reg = RK3576_SMT_GPIO4_AL_OFFSET;
2163
+
else if (bank->bank_num == 4 && pin_num < 24)
2164
+
*reg = RK3576_SMT_GPIO4_CL_OFFSET - 0x8;
2165
+
else if (bank->bank_num == 4)
2166
+
*reg = RK3576_SMT_GPIO4_DL_OFFSET - 0xc;
2167
+
else
2168
+
dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
2169
+
2170
+
*reg += ((pin_num / RK3576_SMT_PINS_PER_REG) * 4);
2171
+
*bit = pin_num % RK3576_SMT_PINS_PER_REG;
2172
+
*bit *= RK3576_SMT_BITS_PER_PIN;
2173
+
2174
+
return 0;
2175
+
}
2176
+
2072
2177
#define RK3588_PMU1_IOC_REG (0x0000)
2073
2178
#define RK3588_PMU2_IOC_REG (0x4000)
2074
2179
#define RK3588_BUS_IOC_REG (0x8000)
···
2499
2332
rmask_bits = RK3568_DRV_BITS_PER_PIN;
2500
2333
ret = (1 << (strength + 1)) - 1;
2501
2334
goto config;
2335
+
} else if (ctrl->type == RK3576) {
2336
+
rmask_bits = RK3576_DRV_BITS_PER_PIN;
2337
+
ret = ((strength & BIT(2)) >> 2) | ((strength & BIT(0)) << 2) | (strength & BIT(1));
2338
+
goto config;
2502
2339
}
2503
2340
2504
2341
if (ctrl->type == RV1126) {
···
2640
2469
case RK3368:
2641
2470
case RK3399:
2642
2471
case RK3568:
2472
+
case RK3576:
2643
2473
case RK3588:
2644
2474
pull_type = bank->pull_type[pin_num / 8];
2645
2475
data >>= bit;
···
2700
2528
case RK3368:
2701
2529
case RK3399:
2702
2530
case RK3568:
2531
+
case RK3576:
2703
2532
case RK3588:
2704
2533
pull_type = bank->pull_type[pin_num / 8];
2705
2534
ret = -EINVAL;
···
2966
2793
case RK3368:
2967
2794
case RK3399:
2968
2795
case RK3568:
2796
+
case RK3576:
2969
2797
case RK3588:
2970
2798
return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
2971
2799
}
···
4123
3949
.schmitt_calc_reg = rk3568_calc_schmitt_reg_and_bit,
4124
3950
};
4125
3951
3952
+
#define RK3576_PIN_BANK(ID, LABEL, OFFSET0, OFFSET1, OFFSET2, OFFSET3) \
3953
+
PIN_BANK_IOMUX_FLAGS_OFFSET_PULL_FLAGS(ID, 32, LABEL, \
3954
+
IOMUX_WIDTH_4BIT, \
3955
+
IOMUX_WIDTH_4BIT, \
3956
+
IOMUX_WIDTH_4BIT, \
3957
+
IOMUX_WIDTH_4BIT, \
3958
+
OFFSET0, OFFSET1, \
3959
+
OFFSET2, OFFSET3, \
3960
+
PULL_TYPE_IO_1V8_ONLY, \
3961
+
PULL_TYPE_IO_1V8_ONLY, \
3962
+
PULL_TYPE_IO_1V8_ONLY, \
3963
+
PULL_TYPE_IO_1V8_ONLY)
3964
+
3965
+
static struct rockchip_pin_bank rk3576_pin_banks[] = {
3966
+
RK3576_PIN_BANK(0, "gpio0", 0, 0x8, 0x2004, 0x200C),
3967
+
RK3576_PIN_BANK(1, "gpio1", 0x4020, 0x4028, 0x4030, 0x4038),
3968
+
RK3576_PIN_BANK(2, "gpio2", 0x4040, 0x4048, 0x4050, 0x4058),
3969
+
RK3576_PIN_BANK(3, "gpio3", 0x4060, 0x4068, 0x4070, 0x4078),
3970
+
RK3576_PIN_BANK(4, "gpio4", 0x4080, 0x4088, 0xA390, 0xB398),
3971
+
};
3972
+
3973
+
static struct rockchip_pin_ctrl rk3576_pin_ctrl __maybe_unused = {
3974
+
.pin_banks = rk3576_pin_banks,
3975
+
.nr_banks = ARRAY_SIZE(rk3576_pin_banks),
3976
+
.label = "RK3576-GPIO",
3977
+
.type = RK3576,
3978
+
.pull_calc_reg = rk3576_calc_pull_reg_and_bit,
3979
+
.drv_calc_reg = rk3576_calc_drv_reg_and_bit,
3980
+
.schmitt_calc_reg = rk3576_calc_schmitt_reg_and_bit,
3981
+
};
3982
+
4126
3983
static struct rockchip_pin_bank rk3588_pin_banks[] = {
4127
3984
RK3588_PIN_BANK_FLAGS(0, 32, "gpio0",
4128
3985
IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY),
···
4210
4005
.data = &rk3399_pin_ctrl },
4211
4006
{ .compatible = "rockchip,rk3568-pinctrl",
4212
4007
.data = &rk3568_pin_ctrl },
4008
+
{ .compatible = "rockchip,rk3576-pinctrl",
4009
+
.data = &rk3576_pin_ctrl },
4213
4010
{ .compatible = "rockchip,rk3588-pinctrl",
4214
4011
.data = &rk3588_pin_ctrl },
4215
4012
{},