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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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kernel
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linux
drm: fix radeon irq properly
After the previous fix in 2.6.12, this patch should properly fix the
radeon IRQ handling code.
From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Dave Airlie <airlied@linux.ie>
authored by Dave Airlie and committed by Dave Airlie 6921e331 bc54fd1a
+13
-14
drivers/char/drm/radeon_irq.c
+13
-14
drivers/char/drm/radeon_irq.c
···
35
#include "radeon_drm.h"
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#include "radeon_drv.h"
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/* Interrupts - Used for device synchronization and flushing in the
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* following circumstances:
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*
···
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/* Only consider the bits we're interested in - others could be used
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* outside the DRM
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*/
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-
stat = RADEON_READ(RADEON_GEN_INT_STATUS)
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-
& (RADEON_SW_INT_TEST | RADEON_CRTC_VBLANK_STAT);
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if (!stat)
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return IRQ_NONE;
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···
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drm_vbl_send_signals( dev );
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}
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-
/* Acknowledge interrupts we handle */
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-
RADEON_WRITE(RADEON_GEN_INT_STATUS, stat);
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return IRQ_HANDLED;
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-
}
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-
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-
static __inline__ void radeon_acknowledge_irqs(drm_radeon_private_t *dev_priv)
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-
{
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-
u32 tmp = RADEON_READ( RADEON_GEN_INT_STATUS )
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-
& (RADEON_SW_INT_TEST_ACK | RADEON_CRTC_VBLANK_STAT);
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-
if (tmp)
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-
RADEON_WRITE( RADEON_GEN_INT_STATUS, tmp );
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}
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static int radeon_emit_irq(drm_device_t *dev)
···
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return DRM_ERR(EINVAL);
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}
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-
radeon_acknowledge_irqs( dev_priv );
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dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
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···
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RADEON_WRITE( RADEON_GEN_INT_CNTL, 0 );
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/* Clear bits if they're already high */
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-
radeon_acknowledge_irqs( dev_priv );
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}
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void radeon_driver_irq_postinstall( drm_device_t *dev ) {
···
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#include "radeon_drm.h"
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#include "radeon_drv.h"
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+
static __inline__ u32 radeon_acknowledge_irqs(drm_radeon_private_t *dev_priv, u32 mask)
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+
{
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+
u32 irqs = RADEON_READ(RADEON_GEN_INT_STATUS) & mask;
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+
if (irqs)
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+
RADEON_WRITE(RADEON_GEN_INT_STATUS, irqs);
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+
return irqs;
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+
}
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+
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/* Interrupts - Used for device synchronization and flushing in the
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* following circumstances:
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*
···
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/* Only consider the bits we're interested in - others could be used
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* outside the DRM
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*/
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+
stat = radeon_acknowledge_irqs(dev_priv, (RADEON_SW_INT_TEST_ACK |
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+
RADEON_CRTC_VBLANK_STAT));
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if (!stat)
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return IRQ_NONE;
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···
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drm_vbl_send_signals( dev );
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}
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return IRQ_HANDLED;
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}
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static int radeon_emit_irq(drm_device_t *dev)
···
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return DRM_ERR(EINVAL);
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}
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+
radeon_acknowledge_irqs(dev_priv, RADEON_CRTC_VBLANK_STAT);
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dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
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···
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RADEON_WRITE( RADEON_GEN_INT_CNTL, 0 );
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/* Clear bits if they're already high */
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+
radeon_acknowledge_irqs(dev_priv, (RADEON_SW_INT_TEST_ACK |
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+
RADEON_CRTC_VBLANK_STAT));
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}
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void radeon_driver_irq_postinstall( drm_device_t *dev ) {