Merge branch 'linux_next' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-edac

+2 -2

drivers/edac/Kconfig

··· 253 253 Clarksboro MCH (Intel 7300 chipset). 254 254 255 255 config EDAC_SBRIDGE 256 - tristate "Intel Sandy-Bridge Integrated MC" 256 + tristate "Intel Sandy-Bridge/Ivy-Bridge/Haswell Integrated MC" 257 257 depends on EDAC_MM_EDAC && PCI && X86_64 && X86_MCE_INTEL 258 258 depends on PCI_MMCONFIG 259 259 help 260 260 Support for error detection and correction the Intel 261 - Sandy Bridge Integrated Memory Controller. 261 + Sandy Bridge, Ivy Bridge and Haswell Integrated Memory Controllers. 262 262 263 263 config EDAC_MPC85XX 264 264 tristate "Freescale MPC83xx / MPC85xx"

+3 -1

drivers/edac/edac_mc_sysfs.c

··· 108 108 [MEM_RDDR2] = "Registered-DDR2", 109 109 [MEM_XDR] = "XDR", 110 110 [MEM_DDR3] = "Unbuffered-DDR3", 111 - [MEM_RDDR3] = "Registered-DDR3" 111 + [MEM_RDDR3] = "Registered-DDR3", 112 + [MEM_DDR4] = "Unbuffered-DDR4", 113 + [MEM_RDDR4] = "Registered-DDR4" 112 114 }; 113 115 114 116 static const char * const dev_types[] = {

+542 -270

drivers/edac/sb_edac.c

··· 99 99 #define DRAM_ATTR(reg) GET_BITFIELD(reg, 2, 3) 100 100 #define INTERLEAVE_MODE(reg) GET_BITFIELD(reg, 1, 1) 101 101 #define DRAM_RULE_ENABLE(reg) GET_BITFIELD(reg, 0, 0) 102 + #define A7MODE(reg) GET_BITFIELD(reg, 26, 26) 102 103 103 104 static char *get_dram_attr(u32 reg) 104 105 { ··· 165 164 166 165 #define TOLM 0x80 167 166 #define TOHM 0x84 167 + #define HASWELL_TOHM_0 0xd4 168 + #define HASWELL_TOHM_1 0xd8 168 169 169 170 #define GET_TOLM(reg) ((GET_BITFIELD(reg, 0, 3) << 28) | 0x3ffffff) 170 171 #define GET_TOHM(reg) ((GET_BITFIELD(reg, 0, 20) << 25) | 0x3ffffff) ··· 178 175 #define SOURCE_ID(reg) GET_BITFIELD(reg, 9, 11) 179 176 180 177 #define SAD_CONTROL 0xf4 181 - 182 - #define NODE_ID(reg) GET_BITFIELD(reg, 0, 2) 183 178 184 179 /* Device 14 function 0 */ 185 180 ··· 236 235 237 236 #define IS_RIR_VALID(reg) GET_BITFIELD(reg, 31, 31) 238 237 #define RIR_WAY(reg) GET_BITFIELD(reg, 28, 29) 239 - #define RIR_LIMIT(reg) ((GET_BITFIELD(reg, 1, 10) << 29)| 0x1fffffff) 240 238 241 239 #define MAX_RIR_WAY 8 242 240 ··· 279 279 280 280 #define IB_RANK_CFG_A 0x0320 281 281 282 - #define IS_RDIMM_ENABLED(reg) GET_BITFIELD(reg, 11, 11) 283 - 284 282 /* 285 283 * sbridge structs 286 284 */ ··· 289 291 enum type { 290 292 SANDY_BRIDGE, 291 293 IVY_BRIDGE, 294 + HASWELL, 292 295 }; 293 296 294 297 struct sbridge_pvt; ··· 299 300 u32 rankcfgr; 300 301 u64 (*get_tolm)(struct sbridge_pvt *pvt); 301 302 u64 (*get_tohm)(struct sbridge_pvt *pvt); 303 + u64 (*rir_limit)(u32 reg); 302 304 const u32 *dram_rule; 303 305 const u32 *interleave_list; 304 306 const struct interleave_pkg *interleave_pkg; 305 307 u8 max_sad; 306 308 u8 max_interleave; 309 + u8 (*get_node_id)(struct sbridge_pvt *pvt); 310 + enum mem_type (*get_memory_type)(struct sbridge_pvt *pvt); 311 + struct pci_dev *pci_vtd; 307 312 }; 308 313 309 314 struct sbridge_channel { ··· 316 313 }; 317 314 318 315 struct pci_id_descr { 319 - int dev; 320 - int func; 321 - int dev_id; 316 + int dev_id; 322 317 int optional; 323 318 }; 324 319 ··· 339 338 struct pci_dev *pci_sad0, *pci_sad1; 340 339 struct pci_dev *pci_ha0, *pci_ha1; 341 340 struct pci_dev *pci_br0, *pci_br1; 341 + struct pci_dev *pci_ha1_ta; 342 342 struct pci_dev *pci_tad[NUM_CHANNELS]; 343 343 344 344 struct sbridge_dev *sbridge_dev; ··· 364 362 u64 tolm, tohm; 365 363 }; 366 364 367 - #define PCI_DESCR(device, function, device_id, opt) \ 368 - .dev = (device), \ 369 - .func = (function), \ 370 - .dev_id = (device_id), \ 365 + #define PCI_DESCR(device_id, opt) \ 366 + .dev_id = (device_id), \ 371 367 .optional = opt 372 368 373 369 static const struct pci_id_descr pci_dev_descr_sbridge[] = { 374 370 /* Processor Home Agent */ 375 - { PCI_DESCR(14, 0, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0, 0) }, 371 + { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0, 0) }, 376 372 377 373 /* Memory controller */ 378 - { PCI_DESCR(15, 0, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA, 0) }, 379 - { PCI_DESCR(15, 1, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_RAS, 0) }, 380 - { PCI_DESCR(15, 2, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0, 0) }, 381 - { PCI_DESCR(15, 3, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD1, 0) }, 382 - { PCI_DESCR(15, 4, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD2, 0) }, 383 - { PCI_DESCR(15, 5, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD3, 0) }, 384 - { PCI_DESCR(17, 0, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_DDRIO, 1) }, 374 + { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA, 0) }, 375 + { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_RAS, 0) }, 376 + { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0, 0) }, 377 + { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD1, 0) }, 378 + { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD2, 0) }, 379 + { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD3, 0) }, 380 + { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_DDRIO, 1) }, 385 381 386 382 /* System Address Decoder */ 387 - { PCI_DESCR(12, 6, PCI_DEVICE_ID_INTEL_SBRIDGE_SAD0, 0) }, 388 - { PCI_DESCR(12, 7, PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1, 0) }, 383 + { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_SAD0, 0) }, 384 + { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1, 0) }, 389 385 390 386 /* Broadcast Registers */ 391 - { PCI_DESCR(13, 6, PCI_DEVICE_ID_INTEL_SBRIDGE_BR, 0) }, 387 + { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_BR, 0) }, 392 388 }; 393 389 394 390 #define PCI_ID_TABLE_ENTRY(A) { .descr=A, .n_devs = ARRAY_SIZE(A) } ··· 423 423 424 424 static const struct pci_id_descr pci_dev_descr_ibridge[] = { 425 425 /* Processor Home Agent */ 426 - { PCI_DESCR(14, 0, PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0, 0) }, 426 + { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0, 0) }, 427 427 428 428 /* Memory controller */ 429 - { PCI_DESCR(15, 0, PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA, 0) }, 430 - { PCI_DESCR(15, 1, PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_RAS, 0) }, 431 - { PCI_DESCR(15, 2, PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0, 0) }, 432 - { PCI_DESCR(15, 3, PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD1, 0) }, 433 - { PCI_DESCR(15, 4, PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD2, 0) }, 434 - { PCI_DESCR(15, 5, PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD3, 0) }, 429 + { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA, 0) }, 430 + { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_RAS, 0) }, 431 + { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0, 0) }, 432 + { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD1, 0) }, 433 + { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD2, 0) }, 434 + { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD3, 0) }, 435 435 436 436 /* System Address Decoder */ 437 - { PCI_DESCR(22, 0, PCI_DEVICE_ID_INTEL_IBRIDGE_SAD, 0) }, 437 + { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_SAD, 0) }, 438 438 439 439 /* Broadcast Registers */ 440 - { PCI_DESCR(22, 1, PCI_DEVICE_ID_INTEL_IBRIDGE_BR0, 1) }, 441 - { PCI_DESCR(22, 2, PCI_DEVICE_ID_INTEL_IBRIDGE_BR1, 0) }, 440 + { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_BR0, 1) }, 441 + { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_BR1, 0) }, 442 442 443 443 /* Optional, mode 2HA */ 444 - { PCI_DESCR(28, 0, PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1, 1) }, 444 + { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1, 1) }, 445 445 #if 0 446 - { PCI_DESCR(29, 0, PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TA, 1) }, 447 - { PCI_DESCR(29, 1, PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_RAS, 1) }, 446 + { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TA, 1) }, 447 + { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_RAS, 1) }, 448 448 #endif 449 - { PCI_DESCR(29, 2, PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0, 1) }, 450 - { PCI_DESCR(29, 3, PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD1, 1) }, 449 + { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0, 1) }, 450 + { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD1, 1) }, 451 451 452 - { PCI_DESCR(17, 0, PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_1HA_DDRIO0, 1) }, 453 - { PCI_DESCR(17, 4, PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_2HA_DDRIO0, 1) }, 452 + { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_1HA_DDRIO0, 1) }, 453 + { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_2HA_DDRIO0, 1) }, 454 454 }; 455 455 456 456 static const struct pci_id_table pci_dev_descr_ibridge_table[] = { 457 457 PCI_ID_TABLE_ENTRY(pci_dev_descr_ibridge), 458 + {0,} /* 0 terminated list. */ 459 + }; 460 + 461 + /* Haswell support */ 462 + /* EN processor: 463 + * - 1 IMC 464 + * - 3 DDR3 channels, 2 DPC per channel 465 + * EP processor: 466 + * - 1 or 2 IMC 467 + * - 4 DDR4 channels, 3 DPC per channel 468 + * EP 4S processor: 469 + * - 2 IMC 470 + * - 4 DDR4 channels, 3 DPC per channel 471 + * EX processor: 472 + * - 2 IMC 473 + * - each IMC interfaces with a SMI 2 channel 474 + * - each SMI channel interfaces with a scalable memory buffer 475 + * - each scalable memory buffer supports 4 DDR3/DDR4 channels, 3 DPC 476 + */ 477 + #define HASWELL_DDRCRCLKCONTROLS 0xa10 478 + #define HASWELL_HASYSDEFEATURE2 0x84 479 + #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_VTD_MISC 0x2f28 480 + #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0 0x2fa0 481 + #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1 0x2f60 482 + #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA 0x2fa8 483 + #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_THERMAL 0x2f71 484 + #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TA 0x2f68 485 + #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_THERMAL 0x2f79 486 + #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD0 0x2ffc 487 + #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD1 0x2ffd 488 + #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0 0x2faa 489 + #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD1 0x2fab 490 + #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD2 0x2fac 491 + #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD3 0x2fad 492 + #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD0 0x2f6a 493 + #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD1 0x2f6b 494 + #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD2 0x2f6c 495 + #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD3 0x2f6d 496 + #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO0 0x2fbd 497 + static const struct pci_id_descr pci_dev_descr_haswell[] = { 498 + /* first item must be the HA */ 499 + { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0, 0) }, 500 + 501 + { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD0, 0) }, 502 + { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD1, 0) }, 503 + 504 + { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1, 1) }, 505 + 506 + { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA, 0) }, 507 + { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_THERMAL, 0) }, 508 + { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0, 0) }, 509 + { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD1, 0) }, 510 + { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD2, 1) }, 511 + { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD3, 1) }, 512 + 513 + { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO0, 1) }, 514 + 515 + { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TA, 1) }, 516 + { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_THERMAL, 1) }, 517 + { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD0, 1) }, 518 + { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD1, 1) }, 519 + { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD2, 1) }, 520 + { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD3, 1) }, 521 + }; 522 + 523 + static const struct pci_id_table pci_dev_descr_haswell_table[] = { 524 + PCI_ID_TABLE_ENTRY(pci_dev_descr_haswell), 458 525 {0,} /* 0 terminated list. */ 459 526 }; 460 527 ··· 531 464 static const struct pci_device_id sbridge_pci_tbl[] = { 532 465 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA)}, 533 466 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA)}, 467 + {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0)}, 534 468 {0,} /* 0 terminated list. */ 535 469 }; 536 470 ··· 540 472 Ancillary status routines 541 473 ****************************************************************************/ 542 474 543 - static inline int numrank(u32 mtr) 475 + static inline int numrank(enum type type, u32 mtr) 544 476 { 545 477 int ranks = (1 << RANK_CNT_BITS(mtr)); 478 + int max = 4; 546 479 547 - if (ranks > 4) { 548 - edac_dbg(0, "Invalid number of ranks: %d (max = 4) raw value = %x (%04x)\n", 549 - ranks, (unsigned int)RANK_CNT_BITS(mtr), mtr); 480 + if (type == HASWELL) 481 + max = 8; 482 + 483 + if (ranks > max) { 484 + edac_dbg(0, "Invalid number of ranks: %d (max = %i) raw value = %x (%04x)\n", 485 + ranks, max, (unsigned int)RANK_CNT_BITS(mtr), mtr); 550 486 return -EINVAL; 551 487 } 552 488 ··· 660 588 return GET_TOHM(reg); 661 589 } 662 590 591 + static u64 rir_limit(u32 reg) 592 + { 593 + return ((u64)GET_BITFIELD(reg, 1, 10) << 29) | 0x1fffffff; 594 + } 595 + 596 + static enum mem_type get_memory_type(struct sbridge_pvt *pvt) 597 + { 598 + u32 reg; 599 + enum mem_type mtype; 600 + 601 + if (pvt->pci_ddrio) { 602 + pci_read_config_dword(pvt->pci_ddrio, pvt->info.rankcfgr, 603 + &reg); 604 + if (GET_BITFIELD(reg, 11, 11)) 605 + /* FIXME: Can also be LRDIMM */ 606 + mtype = MEM_RDDR3; 607 + else 608 + mtype = MEM_DDR3; 609 + } else 610 + mtype = MEM_UNKNOWN; 611 + 612 + return mtype; 613 + } 614 + 615 + static enum mem_type haswell_get_memory_type(struct sbridge_pvt *pvt) 616 + { 617 + u32 reg; 618 + bool registered = false; 619 + enum mem_type mtype = MEM_UNKNOWN; 620 + 621 + if (!pvt->pci_ddrio) 622 + goto out; 623 + 624 + pci_read_config_dword(pvt->pci_ddrio, 625 + HASWELL_DDRCRCLKCONTROLS, &reg); 626 + /* Is_Rdimm */ 627 + if (GET_BITFIELD(reg, 16, 16)) 628 + registered = true; 629 + 630 + pci_read_config_dword(pvt->pci_ta, MCMTR, &reg); 631 + if (GET_BITFIELD(reg, 14, 14)) { 632 + if (registered) 633 + mtype = MEM_RDDR4; 634 + else 635 + mtype = MEM_DDR4; 636 + } else { 637 + if (registered) 638 + mtype = MEM_RDDR3; 639 + else 640 + mtype = MEM_DDR3; 641 + } 642 + 643 + out: 644 + return mtype; 645 + } 646 + 647 + static u8 get_node_id(struct sbridge_pvt *pvt) 648 + { 649 + u32 reg; 650 + pci_read_config_dword(pvt->pci_br0, SAD_CONTROL, &reg); 651 + return GET_BITFIELD(reg, 0, 2); 652 + } 653 + 654 + static u8 haswell_get_node_id(struct sbridge_pvt *pvt) 655 + { 656 + u32 reg; 657 + 658 + pci_read_config_dword(pvt->pci_sad1, SAD_CONTROL, &reg); 659 + return GET_BITFIELD(reg, 0, 3); 660 + } 661 + 662 + static u64 haswell_get_tolm(struct sbridge_pvt *pvt) 663 + { 664 + u32 reg; 665 + 666 + pci_read_config_dword(pvt->info.pci_vtd, TOLM, &reg); 667 + return (GET_BITFIELD(reg, 26, 31) << 26) | 0x1ffffff; 668 + } 669 + 670 + static u64 haswell_get_tohm(struct sbridge_pvt *pvt) 671 + { 672 + u64 rc; 673 + u32 reg; 674 + 675 + pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOHM_0, &reg); 676 + rc = GET_BITFIELD(reg, 26, 31); 677 + pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOHM_1, &reg); 678 + rc = ((reg << 6) | rc) << 26; 679 + 680 + return rc | 0x1ffffff; 681 + } 682 + 683 + static u64 haswell_rir_limit(u32 reg) 684 + { 685 + return (((u64)GET_BITFIELD(reg, 1, 11) + 1) << 29) - 1; 686 + } 687 + 663 688 static inline u8 sad_pkg_socket(u8 pkg) 664 689 { 665 690 /* on Ivy Bridge, nodeID is SASS, where A is HA and S is node id */ 666 - return (pkg >> 3) | (pkg & 0x3); 691 + return ((pkg >> 3) << 2) | (pkg & 0x3); 667 692 } 668 693 669 694 static inline u8 sad_pkg_ha(u8 pkg) ··· 771 602 /**************************************************************************** 772 603 Memory check routines 773 604 ****************************************************************************/ 774 - static struct pci_dev *get_pdev_slot_func(u8 bus, unsigned slot, 775 - unsigned func) 605 + static struct pci_dev *get_pdev_same_bus(u8 bus, u32 id) 776 606 { 777 - struct sbridge_dev *sbridge_dev = get_sbridge_dev(bus); 778 - int i; 607 + struct pci_dev *pdev = NULL; 779 608 780 - if (!sbridge_dev) 781 - return NULL; 609 + do { 610 + pdev = pci_get_device(PCI_VENDOR_ID_INTEL, id, pdev); 611 + if (pdev && pdev->bus->number == bus) 612 + break; 613 + } while (pdev); 782 614 783 - for (i = 0; i < sbridge_dev->n_devs; i++) { 784 - if (!sbridge_dev->pdev[i]) 785 - continue; 786 - 787 - if (PCI_SLOT(sbridge_dev->pdev[i]->devfn) == slot && 788 - PCI_FUNC(sbridge_dev->pdev[i]->devfn) == func) { 789 - edac_dbg(1, "Associated %02x.%02x.%d with %p\n", 790 - bus, slot, func, sbridge_dev->pdev[i]); 791 - return sbridge_dev->pdev[i]; 792 - } 793 - } 794 - 795 - return NULL; 615 + return pdev; 796 616 } 797 617 798 618 /** 799 619 * check_if_ecc_is_active() - Checks if ECC is active 800 - * bus: Device bus 620 + * @bus: Device bus 621 + * @type: Memory controller type 622 + * returns: 0 in case ECC is active, -ENODEV if it can't be determined or 623 + * disabled 801 624 */ 802 - static int check_if_ecc_is_active(const u8 bus) 625 + static int check_if_ecc_is_active(const u8 bus, enum type type) 803 626 { 804 627 struct pci_dev *pdev = NULL; 805 - u32 mcmtr; 628 + u32 mcmtr, id; 806 629 807 - pdev = get_pdev_slot_func(bus, 15, 0); 630 + if (type == IVY_BRIDGE) 631 + id = PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA; 632 + else if (type == HASWELL) 633 + id = PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA; 634 + else 635 + id = PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA; 636 + 637 + pdev = get_pdev_same_bus(bus, id); 808 638 if (!pdev) { 809 639 sbridge_printk(KERN_ERR, "Couldn't find PCI device " 810 - "%2x.%02d.%d!!!\n", 811 - bus, 15, 0); 640 + "%04x:%04x! on bus %02d\n", 641 + PCI_VENDOR_ID_INTEL, id, bus); 812 642 return -ENODEV; 813 643 } 814 644 ··· 829 661 enum edac_type mode; 830 662 enum mem_type mtype; 831 663 832 - pci_read_config_dword(pvt->pci_br0, SAD_TARGET, &reg); 664 + if (pvt->info.type == HASWELL) 665 + pci_read_config_dword(pvt->pci_sad1, SAD_TARGET, &reg); 666 + else 667 + pci_read_config_dword(pvt->pci_br0, SAD_TARGET, &reg); 668 + 833 669 pvt->sbridge_dev->source_id = SOURCE_ID(reg); 834 670 835 - pci_read_config_dword(pvt->pci_br0, SAD_CONTROL, &reg); 836 - pvt->sbridge_dev->node_id = NODE_ID(reg); 671 + pvt->sbridge_dev->node_id = pvt->info.get_node_id(pvt); 837 672 edac_dbg(0, "mc#%d: Node ID: %d, source ID: %d\n", 838 673 pvt->sbridge_dev->mc, 839 674 pvt->sbridge_dev->node_id, ··· 869 698 pvt->is_close_pg = false; 870 699 } 871 700 872 - if (pvt->pci_ddrio) { 873 - pci_read_config_dword(pvt->pci_ddrio, pvt->info.rankcfgr, 874 - &reg); 875 - if (IS_RDIMM_ENABLED(reg)) { 876 - /* FIXME: Can also be LRDIMM */ 877 - edac_dbg(0, "Memory is registered\n"); 878 - mtype = MEM_RDDR3; 879 - } else { 880 - edac_dbg(0, "Memory is unregistered\n"); 881 - mtype = MEM_DDR3; 882 - } 883 - } else { 701 + mtype = pvt->info.get_memory_type(pvt); 702 + if (mtype == MEM_RDDR3 || mtype == MEM_RDDR4) 703 + edac_dbg(0, "Memory is registered\n"); 704 + else if (mtype == MEM_UNKNOWN) 884 705 edac_dbg(0, "Cannot determine memory type\n"); 885 - mtype = MEM_UNKNOWN; 886 - } 706 + else 707 + edac_dbg(0, "Memory is unregistered\n"); 887 708 888 - /* On all supported DDR3 DIMM types, there are 8 banks available */ 889 - banks = 8; 709 + if (mtype == MEM_DDR4 || MEM_RDDR4) 710 + banks = 16; 711 + else 712 + banks = 8; 890 713 891 714 for (i = 0; i < NUM_CHANNELS; i++) { 892 715 u32 mtr; ··· 894 729 if (IS_DIMM_PRESENT(mtr)) { 895 730 pvt->channel[i].dimms++; 896 731 897 - ranks = numrank(mtr); 732 + ranks = numrank(pvt->info.type, mtr); 898 733 rows = numrow(mtr); 899 734 cols = numcol(mtr); 900 735 901 - /* DDR3 has 8 I/O banks */ 902 736 size = ((u64)rows * cols * banks * ranks) >> (20 - 3); 903 737 npages = MiB_TO_PAGES(size); 904 738 ··· 908 744 909 745 dimm->nr_pages = npages; 910 746 dimm->grain = 32; 911 - dimm->dtype = (banks == 8) ? DEV_X8 : DEV_X4; 747 + switch (banks) { 748 + case 16: 749 + dimm->dtype = DEV_X16; 750 + break; 751 + case 8: 752 + dimm->dtype = DEV_X8; 753 + break; 754 + case 4: 755 + dimm->dtype = DEV_X4; 756 + break; 757 + } 912 758 dimm->mtype = mtype; 913 759 dimm->edac_mode = mode; 914 760 snprintf(dimm->label, sizeof(dimm->label), ··· 1061 887 if (!IS_RIR_VALID(reg)) 1062 888 continue; 1063 889 1064 - tmp_mb = RIR_LIMIT(reg) >> 20; 890 + tmp_mb = pvt->info.rir_limit(reg) >> 20; 1065 891 rir_way = 1 << RIR_WAY(reg); 1066 892 mb = div_u64_rem(tmp_mb, 1000, &kb); 1067 893 edac_dbg(0, "CH#%d RIR#%d, limit: %u.%03u GB (0x%016Lx), way: %d, reg=0x%08x\n", ··· 1110 936 struct mem_ctl_info *new_mci; 1111 937 struct sbridge_pvt *pvt = mci->pvt_info; 1112 938 struct pci_dev *pci_ha; 1113 - int n_rir, n_sads, n_tads, sad_way, sck_xch; 939 + int n_rir, n_sads, n_tads, sad_way, sck_xch; 1114 940 int sad_interl, idx, base_ch; 1115 - int interleave_mode; 941 + int interleave_mode, shiftup = 0; 1116 942 unsigned sad_interleave[pvt->info.max_interleave]; 1117 - u32 reg; 943 + u32 reg, dram_rule; 1118 944 u8 ch_way, sck_way, pkg, sad_ha = 0; 1119 945 u32 tad_offset; 1120 946 u32 rir_way; ··· 1161 987 sprintf(msg, "Can't discover the memory socket"); 1162 988 return -EINVAL; 1163 989 } 1164 - *area_type = get_dram_attr(reg); 1165 - interleave_mode = INTERLEAVE_MODE(reg); 990 + dram_rule = reg; 991 + *area_type = get_dram_attr(dram_rule); 992 + interleave_mode = INTERLEAVE_MODE(dram_rule); 1166 993 1167 994 pci_read_config_dword(pvt->pci_sad0, pvt->info.interleave_list[n_sads], 1168 995 &reg); ··· 1208 1033 *socket = sad_interleave[idx]; 1209 1034 edac_dbg(0, "SAD interleave index: %d (wayness %d) = CPU socket %d\n", 1210 1035 idx, sad_way, *socket); 1036 + } else if (pvt->info.type == HASWELL) { 1037 + int bits, a7mode = A7MODE(dram_rule); 1038 + 1039 + if (a7mode) { 1040 + /* A7 mode swaps P9 with P6 */ 1041 + bits = GET_BITFIELD(addr, 7, 8) << 1; 1042 + bits |= GET_BITFIELD(addr, 9, 9); 1043 + } else 1044 + bits = GET_BITFIELD(addr, 7, 9); 1045 + 1046 + if (interleave_mode) { 1047 + /* interleave mode will XOR {8,7,6} with {18,17,16} */ 1048 + idx = GET_BITFIELD(addr, 16, 18); 1049 + idx ^= bits; 1050 + } else 1051 + idx = bits; 1052 + 1053 + pkg = sad_pkg(pvt->info.interleave_pkg, reg, idx); 1054 + *socket = sad_pkg_socket(pkg); 1055 + sad_ha = sad_pkg_ha(pkg); 1056 + 1057 + if (a7mode) { 1058 + /* MCChanShiftUpEnable */ 1059 + pci_read_config_dword(pvt->pci_ha0, 1060 + HASWELL_HASYSDEFEATURE2, &reg); 1061 + shiftup = GET_BITFIELD(reg, 22, 22); 1062 + } 1063 + 1064 + edac_dbg(0, "SAD interleave package: %d = CPU socket %d, HA %i, shiftup: %i\n", 1065 + idx, *socket, sad_ha, shiftup); 1211 1066 } else { 1212 1067 /* Ivy Bridge's SAD mode doesn't support XOR interleave mode */ 1213 1068 idx = (addr >> 6) & 7; ··· 1295 1090 if (ch_way == 3) 1296 1091 idx = addr >> 6; 1297 1092 else 1298 - idx = addr >> (6 + sck_way); 1093 + idx = (addr >> (6 + sck_way + shiftup)) & 0x3; 1299 1094 idx = idx % ch_way; 1300 1095 1301 1096 /* ··· 1386 1181 if (!IS_RIR_VALID(reg)) 1387 1182 continue; 1388 1183 1389 - limit = RIR_LIMIT(reg); 1184 + limit = pvt->info.rir_limit(reg); 1390 1185 mb = div_u64_rem(limit >> 20, 1000, &kb); 1391 1186 edac_dbg(0, "RIR#%d, limit: %u.%03u GB (0x%016Lx), way: %d\n", 1392 1187 n_rir, ··· 1402 1197 return -EINVAL; 1403 1198 } 1404 1199 rir_way = RIR_WAY(reg); 1200 + 1405 1201 if (pvt->is_close_pg) 1406 1202 idx = (ch_addr >> 6); 1407 1203 else ··· 1465 1259 { 1466 1260 struct sbridge_dev *sbridge_dev; 1467 1261 const struct pci_id_descr *dev_descr = &table->descr[devno]; 1468 - 1469 1262 struct pci_dev *pdev = NULL; 1470 1263 u8 bus = 0; 1471 1264 1472 1265 sbridge_printk(KERN_DEBUG, 1473 - "Seeking for: dev %02x.%d PCI ID %04x:%04x\n", 1474 - dev_descr->dev, dev_descr->func, 1266 + "Seeking for: PCI ID %04x:%04x\n", 1475 1267 PCI_VENDOR_ID_INTEL, dev_descr->dev_id); 1476 1268 1477 1269 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, ··· 1484 1280 if (dev_descr->optional) 1485 1281 return 0; 1486 1282 1283 + /* if the HA wasn't found */ 1487 1284 if (devno == 0) 1488 1285 return -ENODEV; 1489 1286 1490 1287 sbridge_printk(KERN_INFO, 1491 - "Device not found: dev %02x.%d PCI ID %04x:%04x\n", 1492 - dev_descr->dev, dev_descr->func, 1288 + "Device not found: %04x:%04x\n", 1493 1289 PCI_VENDOR_ID_INTEL, dev_descr->dev_id); 1494 1290 1495 1291 /* End of list, leave */ ··· 1509 1305 1510 1306 if (sbridge_dev->pdev[devno]) { 1511 1307 sbridge_printk(KERN_ERR, 1512 - "Duplicated device for " 1513 - "dev %02x:%d.%d PCI ID %04x:%04x\n", 1514 - bus, dev_descr->dev, dev_descr->func, 1308 + "Duplicated device for %04x:%04x\n", 1515 1309 PCI_VENDOR_ID_INTEL, dev_descr->dev_id); 1516 1310 pci_dev_put(pdev); 1517 1311 return -ENODEV; ··· 1517 1315 1518 1316 sbridge_dev->pdev[devno] = pdev; 1519 1317 1520 - /* Sanity check */ 1521 - if (unlikely(PCI_SLOT(pdev->devfn) != dev_descr->dev || 1522 - PCI_FUNC(pdev->devfn) != dev_descr->func)) { 1523 - sbridge_printk(KERN_ERR, 1524 - "Device PCI ID %04x:%04x " 1525 - "has dev %02x:%d.%d instead of dev %02x:%02x.%d\n", 1526 - PCI_VENDOR_ID_INTEL, dev_descr->dev_id, 1527 - bus, PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), 1528 - bus, dev_descr->dev, dev_descr->func); 1529 - return -ENODEV; 1530 - } 1531 - 1532 1318 /* Be sure that the device is enabled */ 1533 1319 if (unlikely(pci_enable_device(pdev) < 0)) { 1534 1320 sbridge_printk(KERN_ERR, 1535 - "Couldn't enable " 1536 - "dev %02x:%d.%d PCI ID %04x:%04x\n", 1537 - bus, dev_descr->dev, dev_descr->func, 1321 + "Couldn't enable %04x:%04x\n", 1538 1322 PCI_VENDOR_ID_INTEL, dev_descr->dev_id); 1539 1323 return -ENODEV; 1540 1324 } 1541 1325 1542 - edac_dbg(0, "Detected dev %02x:%d.%d PCI ID %04x:%04x\n", 1543 - bus, dev_descr->dev, dev_descr->func, 1326 + edac_dbg(0, "Detected %04x:%04x\n", 1544 1327 PCI_VENDOR_ID_INTEL, dev_descr->dev_id); 1545 1328 1546 1329 /* ··· 1542 1355 1543 1356 /* 1544 1357 * sbridge_get_all_devices - Find and perform 'get' operation on the MCH's 1545 - * device/functions we want to reference for this driver. 1546 - * Need to 'get' device 16 func 1 and func 2. 1358 + * devices we want to reference for this driver. 1547 1359 * @num_mc: pointer to the memory controllers count, to be incremented in case 1548 - * of success. 1360 + * of success. 1549 1361 * @table: model specific table 1550 1362 * 1551 1363 * returns 0 in case of success or error code ··· 1582 1396 { 1583 1397 struct sbridge_pvt *pvt = mci->pvt_info; 1584 1398 struct pci_dev *pdev; 1585 - int i, func, slot; 1399 + int i; 1586 1400 1587 1401 for (i = 0; i < sbridge_dev->n_devs; i++) { 1588 1402 pdev = sbridge_dev->pdev[i]; 1589 1403 if (!pdev) 1590 1404 continue; 1591 - slot = PCI_SLOT(pdev->devfn); 1592 - func = PCI_FUNC(pdev->devfn); 1593 - switch (slot) { 1594 - case 12: 1595 - switch (func) { 1596 - case 6: 1597 - pvt->pci_sad0 = pdev; 1598 - break; 1599 - case 7: 1600 - pvt->pci_sad1 = pdev; 1601 - break; 1602 - default: 1603 - goto error; 1604 - } 1405 + 1406 + switch (pdev->device) { 1407 + case PCI_DEVICE_ID_INTEL_SBRIDGE_SAD0: 1408 + pvt->pci_sad0 = pdev; 1605 1409 break; 1606 - case 13: 1607 - switch (func) { 1608 - case 6: 1609 - pvt->pci_br0 = pdev; 1610 - break; 1611 - default: 1612 - goto error; 1613 - } 1410 + case PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1: 1411 + pvt->pci_sad1 = pdev; 1614 1412 break; 1615 - case 14: 1616 - switch (func) { 1617 - case 0: 1618 - pvt->pci_ha0 = pdev; 1619 - break; 1620 - default: 1621 - goto error; 1622 - } 1413 + case PCI_DEVICE_ID_INTEL_SBRIDGE_BR: 1414 + pvt->pci_br0 = pdev; 1623 1415 break; 1624 - case 15: 1625 - switch (func) { 1626 - case 0: 1627 - pvt->pci_ta = pdev; 1628 - break; 1629 - case 1: 1630 - pvt->pci_ras = pdev; 1631 - break; 1632 - case 2: 1633 - case 3: 1634 - case 4: 1635 - case 5: 1636 - pvt->pci_tad[func - 2] = pdev; 1637 - break; 1638 - default: 1639 - goto error; 1640 - } 1416 + case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0: 1417 + pvt->pci_ha0 = pdev; 1641 1418 break; 1642 - case 17: 1643 - switch (func) { 1644 - case 0: 1645 - pvt->pci_ddrio = pdev; 1646 - break; 1647 - default: 1648 - goto error; 1649 - } 1419 + case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA: 1420 + pvt->pci_ta = pdev; 1421 + break; 1422 + case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_RAS: 1423 + pvt->pci_ras = pdev; 1424 + break; 1425 + case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0: 1426 + case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD1: 1427 + case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD2: 1428 + case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD3: 1429 + { 1430 + int id = pdev->device - PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0; 1431 + pvt->pci_tad[id] = pdev; 1432 + } 1433 + break; 1434 + case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_DDRIO: 1435 + pvt->pci_ddrio = pdev; 1650 1436 break; 1651 1437 default: 1652 1438 goto error; 1653 1439 } 1654 1440 1655 - edac_dbg(0, "Associated PCI %02x.%02d.%d with dev = %p\n", 1441 + edac_dbg(0, "Associated PCI %02x:%02x, bus %d with dev = %p\n", 1442 + pdev->vendor, pdev->device, 1656 1443 sbridge_dev->bus, 1657 - PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), 1658 1444 pdev); 1659 1445 } 1660 1446 ··· 1646 1488 return -ENODEV; 1647 1489 1648 1490 error: 1649 - sbridge_printk(KERN_ERR, "Device %d, function %d " 1650 - "is out of the expected range\n", 1651 - slot, func); 1491 + sbridge_printk(KERN_ERR, "Unexpected device %02x:%02x\n", 1492 + PCI_VENDOR_ID_INTEL, pdev->device); 1652 1493 return -EINVAL; 1653 1494 } 1654 1495 ··· 1656 1499 { 1657 1500 struct sbridge_pvt *pvt = mci->pvt_info; 1658 1501 struct pci_dev *pdev, *tmp; 1659 - int i, func, slot; 1502 + int i; 1660 1503 bool mode_2ha = false; 1661 1504 1662 1505 tmp = pci_get_device(PCI_VENDOR_ID_INTEL, ··· 1670 1513 pdev = sbridge_dev->pdev[i]; 1671 1514 if (!pdev) 1672 1515 continue; 1673 - slot = PCI_SLOT(pdev->devfn); 1674 - func = PCI_FUNC(pdev->devfn); 1675 1516 1676 - switch (slot) { 1677 - case 14: 1678 - if (func == 0) { 1679 - pvt->pci_ha0 = pdev; 1680 - break; 1681 - } 1682 - goto error; 1683 - case 15: 1684 - switch (func) { 1685 - case 0: 1686 - pvt->pci_ta = pdev; 1687 - break; 1688 - case 1: 1689 - pvt->pci_ras = pdev; 1690 - break; 1691 - case 4: 1692 - case 5: 1693 - /* if we have 2 HAs active, channels 2 and 3 1694 - * are in other device */ 1695 - if (mode_2ha) 1696 - break; 1697 - /* fall through */ 1698 - case 2: 1699 - case 3: 1700 - pvt->pci_tad[func - 2] = pdev; 1701 - break; 1702 - default: 1703 - goto error; 1704 - } 1517 + switch (pdev->device) { 1518 + case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0: 1519 + pvt->pci_ha0 = pdev; 1705 1520 break; 1706 - case 17: 1707 - if (func == 4) { 1521 + case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA: 1522 + pvt->pci_ta = pdev; 1523 + case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_RAS: 1524 + pvt->pci_ras = pdev; 1525 + break; 1526 + case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD2: 1527 + case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD3: 1528 + /* if we have 2 HAs active, channels 2 and 3 1529 + * are in other device */ 1530 + if (mode_2ha) 1531 + break; 1532 + /* fall through */ 1533 + case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0: 1534 + case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD1: 1535 + { 1536 + int id = pdev->device - PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0; 1537 + pvt->pci_tad[id] = pdev; 1538 + } 1539 + break; 1540 + case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_2HA_DDRIO0: 1541 + pvt->pci_ddrio = pdev; 1542 + break; 1543 + case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_1HA_DDRIO0: 1544 + if (!mode_2ha) 1708 1545 pvt->pci_ddrio = pdev; 1709 - break; 1710 - } else if (func == 0) { 1711 - if (!mode_2ha) 1712 - pvt->pci_ddrio = pdev; 1713 - break; 1714 - } 1715 - goto error; 1716 - case 22: 1717 - switch (func) { 1718 - case 0: 1719 - pvt->pci_sad0 = pdev; 1720 - break; 1721 - case 1: 1722 - pvt->pci_br0 = pdev; 1723 - break; 1724 - case 2: 1725 - pvt->pci_br1 = pdev; 1726 - break; 1727 - default: 1728 - goto error; 1729 - } 1730 1546 break; 1731 - case 28: 1732 - if (func == 0) { 1733 - pvt->pci_ha1 = pdev; 1734 - break; 1735 - } 1736 - goto error; 1737 - case 29: 1547 + case PCI_DEVICE_ID_INTEL_IBRIDGE_SAD: 1548 + pvt->pci_sad0 = pdev; 1549 + break; 1550 + case PCI_DEVICE_ID_INTEL_IBRIDGE_BR0: 1551 + pvt->pci_br0 = pdev; 1552 + break; 1553 + case PCI_DEVICE_ID_INTEL_IBRIDGE_BR1: 1554 + pvt->pci_br1 = pdev; 1555 + break; 1556 + case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1: 1557 + pvt->pci_ha1 = pdev; 1558 + break; 1559 + case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0: 1560 + case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD1: 1561 + { 1562 + int id = pdev->device - PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0 + 2; 1563 + 1738 1564 /* we shouldn't have this device if we have just one 1739 1565 * HA present */ 1740 1566 WARN_ON(!mode_2ha); 1741 - if (func == 2 || func == 3) { 1742 - pvt->pci_tad[func] = pdev; 1743 - break; 1744 - } 1745 - goto error; 1567 + pvt->pci_tad[id] = pdev; 1568 + } 1569 + break; 1746 1570 default: 1747 1571 goto error; 1748 1572 } ··· 1752 1614 1753 1615 error: 1754 1616 sbridge_printk(KERN_ERR, 1755 - "Device %d, function %d is out of the expected range\n", 1756 - slot, func); 1617 + "Unexpected device %02x:%02x\n", PCI_VENDOR_ID_INTEL, 1618 + pdev->device); 1757 1619 return -EINVAL; 1620 + } 1621 + 1622 + static int haswell_mci_bind_devs(struct mem_ctl_info *mci, 1623 + struct sbridge_dev *sbridge_dev) 1624 + { 1625 + struct sbridge_pvt *pvt = mci->pvt_info; 1626 + struct pci_dev *pdev, *tmp; 1627 + int i; 1628 + bool mode_2ha = false; 1629 + 1630 + tmp = pci_get_device(PCI_VENDOR_ID_INTEL, 1631 + PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1, NULL); 1632 + if (tmp) { 1633 + mode_2ha = true; 1634 + pci_dev_put(tmp); 1635 + } 1636 + 1637 + /* there's only one device per system; not tied to any bus */ 1638 + if (pvt->info.pci_vtd == NULL) 1639 + /* result will be checked later */ 1640 + pvt->info.pci_vtd = pci_get_device(PCI_VENDOR_ID_INTEL, 1641 + PCI_DEVICE_ID_INTEL_HASWELL_IMC_VTD_MISC, 1642 + NULL); 1643 + 1644 + for (i = 0; i < sbridge_dev->n_devs; i++) { 1645 + pdev = sbridge_dev->pdev[i]; 1646 + if (!pdev) 1647 + continue; 1648 + 1649 + switch (pdev->device) { 1650 + case PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD0: 1651 + pvt->pci_sad0 = pdev; 1652 + break; 1653 + case PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD1: 1654 + pvt->pci_sad1 = pdev; 1655 + break; 1656 + case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0: 1657 + pvt->pci_ha0 = pdev; 1658 + break; 1659 + case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA: 1660 + pvt->pci_ta = pdev; 1661 + break; 1662 + case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_THERMAL: 1663 + pvt->pci_ras = pdev; 1664 + break; 1665 + case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0: 1666 + pvt->pci_tad[0] = pdev; 1667 + break; 1668 + case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD1: 1669 + pvt->pci_tad[1] = pdev; 1670 + break; 1671 + case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD2: 1672 + if (!mode_2ha) 1673 + pvt->pci_tad[2] = pdev; 1674 + break; 1675 + case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD3: 1676 + if (!mode_2ha) 1677 + pvt->pci_tad[3] = pdev; 1678 + break; 1679 + case PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO0: 1680 + pvt->pci_ddrio = pdev; 1681 + break; 1682 + case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1: 1683 + pvt->pci_ha1 = pdev; 1684 + break; 1685 + case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TA: 1686 + pvt->pci_ha1_ta = pdev; 1687 + break; 1688 + case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD0: 1689 + if (mode_2ha) 1690 + pvt->pci_tad[2] = pdev; 1691 + break; 1692 + case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD1: 1693 + if (mode_2ha) 1694 + pvt->pci_tad[3] = pdev; 1695 + break; 1696 + default: 1697 + break; 1698 + } 1699 + 1700 + edac_dbg(0, "Associated PCI %02x.%02d.%d with dev = %p\n", 1701 + sbridge_dev->bus, 1702 + PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), 1703 + pdev); 1704 + } 1705 + 1706 + /* Check if everything were registered */ 1707 + if (!pvt->pci_sad0 || !pvt->pci_ha0 || !pvt->pci_sad1 || 1708 + !pvt->pci_ras || !pvt->pci_ta || !pvt->info.pci_vtd) 1709 + goto enodev; 1710 + 1711 + for (i = 0; i < NUM_CHANNELS; i++) { 1712 + if (!pvt->pci_tad[i]) 1713 + goto enodev; 1714 + } 1715 + return 0; 1716 + 1717 + enodev: 1718 + sbridge_printk(KERN_ERR, "Some needed devices are missing\n"); 1719 + return -ENODEV; 1758 1720 } 1759 1721 1760 1722 /**************************************************************************** ··· 1974 1736 * EDAC core should be handling the channel mask, in order to point 1975 1737 * to the group of dimm's where the error may be happening. 1976 1738 */ 1739 + if (!pvt->is_lockstep && !pvt->is_mirrored && !pvt->is_close_pg) 1740 + channel = first_channel; 1741 + 1977 1742 snprintf(msg, sizeof(msg), 1978 1743 "%s%s area:%s err_code:%04x:%04x socket:%d channel_mask:%ld rank:%d", 1979 1744 overflow ? " OVERFLOW" : "", ··· 2106 1865 "%u APIC %x\n", mce->cpuvendor, mce->cpuid, 2107 1866 mce->time, mce->socketid, mce->apicid); 2108 1867 2109 - /* Only handle if it is the right mc controller */ 2110 - if (cpu_data(mce->cpu).phys_proc_id != pvt->sbridge_dev->mc) 2111 - return NOTIFY_DONE; 2112 - 2113 1868 smp_rmb(); 2114 1869 if ((pvt->mce_out + 1) % MCE_LOG_LEN == pvt->mce_in) { 2115 1870 smp_wmb(); ··· 2169 1932 int rc; 2170 1933 2171 1934 /* Check the number of active and not disabled channels */ 2172 - rc = check_if_ecc_is_active(sbridge_dev->bus); 1935 + rc = check_if_ecc_is_active(sbridge_dev->bus, type); 2173 1936 if (unlikely(rc < 0)) 2174 1937 return rc; 2175 1938 ··· 2208 1971 mci->edac_check = sbridge_check_error; 2209 1972 2210 1973 pvt->info.type = type; 2211 - if (type == IVY_BRIDGE) { 1974 + switch (type) { 1975 + case IVY_BRIDGE: 2212 1976 pvt->info.rankcfgr = IB_RANK_CFG_A; 2213 1977 pvt->info.get_tolm = ibridge_get_tolm; 2214 1978 pvt->info.get_tohm = ibridge_get_tohm; 2215 1979 pvt->info.dram_rule = ibridge_dram_rule; 1980 + pvt->info.get_memory_type = get_memory_type; 1981 + pvt->info.get_node_id = get_node_id; 1982 + pvt->info.rir_limit = rir_limit; 2216 1983 pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule); 2217 1984 pvt->info.interleave_list = ibridge_interleave_list; 2218 1985 pvt->info.max_interleave = ARRAY_SIZE(ibridge_interleave_list); ··· 2227 1986 rc = ibridge_mci_bind_devs(mci, sbridge_dev); 2228 1987 if (unlikely(rc < 0)) 2229 1988 goto fail0; 2230 - } else { 1989 + break; 1990 + case SANDY_BRIDGE: 2231 1991 pvt->info.rankcfgr = SB_RANK_CFG_A; 2232 1992 pvt->info.get_tolm = sbridge_get_tolm; 2233 1993 pvt->info.get_tohm = sbridge_get_tohm; 2234 1994 pvt->info.dram_rule = sbridge_dram_rule; 1995 + pvt->info.get_memory_type = get_memory_type; 1996 + pvt->info.get_node_id = get_node_id; 1997 + pvt->info.rir_limit = rir_limit; 2235 1998 pvt->info.max_sad = ARRAY_SIZE(sbridge_dram_rule); 2236 1999 pvt->info.interleave_list = sbridge_interleave_list; 2237 2000 pvt->info.max_interleave = ARRAY_SIZE(sbridge_interleave_list); ··· 2246 2001 rc = sbridge_mci_bind_devs(mci, sbridge_dev); 2247 2002 if (unlikely(rc < 0)) 2248 2003 goto fail0; 2249 - } 2004 + break; 2005 + case HASWELL: 2006 + /* rankcfgr isn't used */ 2007 + pvt->info.get_tolm = haswell_get_tolm; 2008 + pvt->info.get_tohm = haswell_get_tohm; 2009 + pvt->info.dram_rule = ibridge_dram_rule; 2010 + pvt->info.get_memory_type = haswell_get_memory_type; 2011 + pvt->info.get_node_id = haswell_get_node_id; 2012 + pvt->info.rir_limit = haswell_rir_limit; 2013 + pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule); 2014 + pvt->info.interleave_list = ibridge_interleave_list; 2015 + pvt->info.max_interleave = ARRAY_SIZE(ibridge_interleave_list); 2016 + pvt->info.interleave_pkg = ibridge_interleave_pkg; 2017 + mci->ctl_name = kasprintf(GFP_KERNEL, "Haswell Socket#%d", mci->mc_idx); 2250 2018 2019 + /* Store pci devices at mci for faster access */ 2020 + rc = haswell_mci_bind_devs(mci, sbridge_dev); 2021 + if (unlikely(rc < 0)) 2022 + goto fail0; 2023 + break; 2024 + } 2251 2025 2252 2026 /* Get dimm basic config and the memory layout */ 2253 2027 get_dimm_config(mci); ··· 2301 2037 2302 2038 static int sbridge_probe(struct pci_dev *pdev, const struct pci_device_id *id) 2303 2039 { 2304 - int rc; 2040 + int rc = -ENODEV; 2305 2041 u8 mc, num_mc = 0; 2306 2042 struct sbridge_dev *sbridge_dev; 2307 - enum type type; 2043 + enum type type = SANDY_BRIDGE; 2308 2044 2309 2045 /* get the pci devices we want to reserve for our use */ 2310 2046 mutex_lock(&sbridge_edac_lock); ··· 2318 2054 } 2319 2055 probed++; 2320 2056 2321 - if (pdev->device == PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA) { 2057 + switch (pdev->device) { 2058 + case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA: 2322 2059 rc = sbridge_get_all_devices(&num_mc, pci_dev_descr_ibridge_table); 2323 2060 type = IVY_BRIDGE; 2324 - } else { 2061 + break; 2062 + case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA: 2325 2063 rc = sbridge_get_all_devices(&num_mc, pci_dev_descr_sbridge_table); 2326 2064 type = SANDY_BRIDGE; 2065 + break; 2066 + case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0: 2067 + rc = sbridge_get_all_devices(&num_mc, pci_dev_descr_haswell_table); 2068 + type = HASWELL; 2069 + break; 2327 2070 } 2328 2071 if (unlikely(rc < 0)) 2329 2072 goto fail0; ··· 2339 2068 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) { 2340 2069 edac_dbg(0, "Registering MC#%d (%d of %d)\n", 2341 2070 mc, mc + 1, num_mc); 2071 + 2342 2072 sbridge_dev->mc = mc++; 2343 2073 rc = sbridge_register_mci(sbridge_dev, type); 2344 2074 if (unlikely(rc < 0))

+5

include/linux/edac.h

··· 194 194 * @MEM_DDR3: DDR3 RAM 195 195 * @MEM_RDDR3: Registered DDR3 RAM 196 196 * This is a variant of the DDR3 memories. 197 + * @MEM_DDR4: DDR4 RAM 198 + * @MEM_RDDR4: Registered DDR4 RAM 199 + * This is a variant of the DDR4 memories. 197 200 */ 198 201 enum mem_type { 199 202 MEM_EMPTY = 0, ··· 216 213 MEM_XDR, 217 214 MEM_DDR3, 218 215 MEM_RDDR3, 216 + MEM_DDR4, 217 + MEM_RDDR4, 219 218 }; 220 219 221 220 #define MEM_FLAG_EMPTY BIT(MEM_EMPTY)