tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

ASoC: rt5645: fix issue of random interrupt from push-button

Modify register setting sequence of enabling inline command
to fix issue of random interrupt from push-button.

Signed-off-by: Jack Yu <jack.yu@realtek.com>
Link: https://patch.msgid.link/9a7a3a66cbcb426487ca6f558f45e922@realtek.com
Signed-off-by: Mark Brown <broonie@kernel.org>

authored by

Jack Yu and committed by
Mark Brown 68f97fe3 63b47f02

+24 -6
+18 -6
sound/soc/codecs/rt5645.c
··· 81 81 static const struct reg_sequence rt5650_init_list[] = { 82 82 {0xf6, 0x0100}, 83 83 {RT5645_PWR_ANLG1, 0x02}, 84 - {RT5645_IL_CMD3, 0x0018}, 84 + {RT5645_IL_CMD3, 0x6728}, 85 85 }; 86 86 87 87 static const struct reg_default rt5645_reg[] = { ··· 3130 3130 bool enable) 3131 3131 { 3132 3132 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 3133 + int ret; 3133 3134 3134 3135 if (enable) { 3135 3136 snd_soc_dapm_force_enable_pin(dapm, "ADC L power"); 3136 3137 snd_soc_dapm_force_enable_pin(dapm, "ADC R power"); 3137 3138 snd_soc_dapm_sync(dapm); 3138 3139 3140 + snd_soc_component_update_bits(component, RT5650_4BTN_IL_CMD2, 3141 + RT5645_EN_4BTN_IL_MASK | RT5645_RST_4BTN_IL_MASK, 3142 + RT5645_EN_4BTN_IL_EN | RT5645_RST_4BTN_IL_RST); 3143 + usleep_range(10000, 15000); 3144 + snd_soc_component_update_bits(component, RT5650_4BTN_IL_CMD2, 3145 + RT5645_EN_4BTN_IL_MASK | RT5645_RST_4BTN_IL_MASK, 3146 + RT5645_EN_4BTN_IL_EN | RT5645_RST_4BTN_IL_NORM); 3147 + msleep(50); 3148 + ret = snd_soc_component_read(component, RT5645_INT_IRQ_ST); 3149 + pr_debug("%s read %x = %x\n", __func__, RT5645_INT_IRQ_ST, 3150 + snd_soc_component_read(component, RT5645_INT_IRQ_ST)); 3151 + snd_soc_component_write(component, RT5645_INT_IRQ_ST, ret); 3152 + ret = snd_soc_component_read(component, RT5650_4BTN_IL_CMD1); 3153 + pr_debug("%s read %x = %x\n", __func__, RT5650_4BTN_IL_CMD1, 3154 + snd_soc_component_read(component, RT5650_4BTN_IL_CMD1)); 3155 + snd_soc_component_write(component, RT5650_4BTN_IL_CMD1, ret); 3139 3156 snd_soc_component_update_bits(component, RT5650_4BTN_IL_CMD1, 0x3, 0x3); 3140 3157 snd_soc_component_update_bits(component, 3141 3158 RT5645_INT_IRQ_ST, 0x8, 0x8); 3142 - snd_soc_component_update_bits(component, 3143 - RT5650_4BTN_IL_CMD2, 0x8000, 0x8000); 3144 - snd_soc_component_read(component, RT5650_4BTN_IL_CMD1); 3145 - pr_debug("%s read %x = %x\n", __func__, RT5650_4BTN_IL_CMD1, 3146 - snd_soc_component_read(component, RT5650_4BTN_IL_CMD1)); 3147 3159 } else { 3148 3160 snd_soc_component_update_bits(component, RT5650_4BTN_IL_CMD2, 0x8000, 0x0); 3149 3161 snd_soc_component_update_bits(component, RT5645_INT_IRQ_ST, 0x8, 0x0);
+6
sound/soc/codecs/rt5645.h
··· 2011 2011 #define RT5645_ZCD_HP_DIS (0x0 << 15) 2012 2012 #define RT5645_ZCD_HP_EN (0x1 << 15) 2013 2013 2014 + /* Buttons Inline Command Function 2 (0xe0) */ 2015 + #define RT5645_EN_4BTN_IL_MASK (0x1 << 15) 2016 + #define RT5645_EN_4BTN_IL_EN (0x1 << 15) 2017 + #define RT5645_RST_4BTN_IL_MASK (0x1 << 14) 2018 + #define RT5645_RST_4BTN_IL_RST (0x0 << 14) 2019 + #define RT5645_RST_4BTN_IL_NORM (0x1 << 14) 2014 2020 2015 2021 /* Codec Private Register definition */ 2016 2022 /* DAC ADC Digital Volume (0x00) */