tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
sh: rework ipr code
This patch reworks the ipr code by grouping the offset array together
with the ipr_data structure in a new data structure called ipr_desc.
This new structure also contains the name of the controller in struct
irq_chip. The idea behind putting struct irq_chip in there is that we
can use offsetof() to locate the base addresses in the irq_chip
callbacks. This strategy has much in common with the recently merged
intc2 code.
One logic change has been made - the original ipr code enabled the
interrupts by default but with this patch they are all disabled by
default.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
authored by
Magnus Damm
and committed by
Paul Mundt
68abdbbb
50f63f25
+429
-326
+53
-71
arch/sh/boards/se/770x/irq.c
+53
-71
arch/sh/boards/se/770x/irq.c
···
15
15
#include <asm/io.h>
16
16
#include <asm/se.h>
17
17
18
-
/*
19
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* If the problem of make_ipr_irq is solved,
20
-
* this code will become unnecessary. :-)
21
-
*/
22
-
static void se770x_disable_ipr_irq(unsigned int irq)
23
-
{
24
-
struct ipr_data *p = get_irq_chip_data(irq);
25
-
26
-
ctrl_outw(ctrl_inw(p->addr) & (0xffff ^ (0xf << p->shift)), p->addr);
27
-
}
28
-
29
-
static void se770x_enable_ipr_irq(unsigned int irq)
30
-
{
31
-
struct ipr_data *p = get_irq_chip_data(irq);
32
-
33
-
ctrl_outw(ctrl_inw(p->addr) | (p->priority << p->shift), p->addr);
34
-
}
35
-
36
-
static struct irq_chip se770x_irq_chip = {
37
-
.name = "MS770xSE-FPGA",
38
-
.mask = se770x_disable_ipr_irq,
39
-
.unmask = se770x_enable_ipr_irq,
40
-
.mask_ack = se770x_disable_ipr_irq,
41
-
};
42
-
43
-
void make_se770x_irq(struct ipr_data *table, unsigned int nr_irqs)
44
-
{
45
-
int i;
46
-
47
-
for (i = 0; i < nr_irqs; i++) {
48
-
unsigned int irq = table[i].irq;
49
-
disable_irq_nosync(irq);
50
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set_irq_chip_and_handler_name(irq, &se770x_irq_chip,
51
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handle_level_irq, "level");
52
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set_irq_chip_data(irq, &table[i]);
53
-
se770x_enable_ipr_irq(irq);
54
-
}
55
-
}
56
-
57
-
static struct ipr_data se770x_ipr_map[] = {
18
+
static struct ipr_data ipr_irq_table[] = {
58
19
/*
59
20
* Super I/O (Just mimic PC):
60
21
* 1: keyboard
···
29
68
*/
30
69
#if defined(CONFIG_CPU_SUBTYPE_SH7705)
31
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/* This is default value */
32
-
{ 13, 0, 8, 0x0f-13 ,BCR_ILCRA},
33
-
{ 5 , 0, 4, 0x0f- 5 ,BCR_ILCRA},
34
-
{ 10, 0, 0, 0x0f-10, BCR_ILCRB},
35
-
{ 7 , 0, 4, 0x0f- 7, BCR_ILCRC},
36
-
{ 3 , 0, 0, 0x0f- 3, BCR_ILCRC},
37
-
{ 1 , 0, 12, 0x0f- 1, BCR_ILCRD},
38
-
{ 12, 0, 4, 0x0f-12, BCR_ILCRD}, /* LAN */
39
-
{ 2 , 0, 8, 0x0f- 2, BCR_ILCRE}, /* PCIRQ2 */
40
-
{ 6 , 0, 4, 0x0f- 6, BCR_ILCRE}, /* PCIRQ1 */
41
-
{ 14, 0, 0, 0x0f-14, BCR_ILCRE}, /* PCIRQ0 */
42
-
{ 0 , 0, 12, 0x0f , BCR_ILCRF},
43
-
{ 4 , 0, 4, 0x0f- 4, BCR_ILCRF},
44
-
{ 8 , 0, 12, 0x0f- 8, BCR_ILCRG},
45
-
{ 9 , 0, 8, 0x0f- 9, BCR_ILCRG},
46
-
{ 11, 0, 4, 0x0f-11, BCR_ILCRG},
71
+
{ 13, 0, 8, 0x0f-13, },
72
+
{ 5 , 0, 4, 0x0f- 5, },
73
+
{ 10, 1, 0, 0x0f-10, },
74
+
{ 7 , 2, 4, 0x0f- 7, },
75
+
{ 3 , 2, 0, 0x0f- 3, },
76
+
{ 1 , 3, 12, 0x0f- 1, },
77
+
{ 12, 3, 4, 0x0f-12, }, /* LAN */
78
+
{ 2 , 4, 8, 0x0f- 2, }, /* PCIRQ2 */
79
+
{ 6 , 4, 4, 0x0f- 6, }, /* PCIRQ1 */
80
+
{ 14, 4, 0, 0x0f-14, }, /* PCIRQ0 */
81
+
{ 0 , 5, 12, 0x0f , },
82
+
{ 4 , 5, 4, 0x0f- 4, },
83
+
{ 8 , 6, 12, 0x0f- 8, },
84
+
{ 9 , 6, 8, 0x0f- 9, },
85
+
{ 11, 6, 4, 0x0f-11, },
47
86
#else
48
-
{ 14, 0, 8, 0x0f-14 ,BCR_ILCRA},
49
-
{ 12, 0, 4, 0x0f-12 ,BCR_ILCRA},
50
-
{ 8, 0, 4, 0x0f- 8 ,BCR_ILCRB},
51
-
{ 6, 0, 12, 0x0f- 6 ,BCR_ILCRC},
52
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{ 5, 0, 8, 0x0f- 5 ,BCR_ILCRC},
53
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{ 4, 0, 4, 0x0f- 4 ,BCR_ILCRC},
54
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{ 3, 0, 0, 0x0f- 3 ,BCR_ILCRC},
55
-
{ 1, 0, 12, 0x0f- 1 ,BCR_ILCRD},
87
+
{ 14, 0, 8, 0x0f-14, },
88
+
{ 12, 0, 4, 0x0f-12, },
89
+
{ 8, 1, 4, 0x0f- 8, },
90
+
{ 6, 2, 12, 0x0f- 6, },
91
+
{ 5, 2, 8, 0x0f- 5, },
92
+
{ 4, 2, 4, 0x0f- 4, },
93
+
{ 3, 2, 0, 0x0f- 3, },
94
+
{ 1, 3, 12, 0x0f- 1, },
56
95
#if defined(CONFIG_STNIC)
57
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/* ST NIC */
58
-
{ 10, 0, 4, 0x0f-10 ,BCR_ILCRD}, /* LAN */
97
+
{ 10, 3, 4, 0x0f-10, }, /* LAN */
59
98
#endif
60
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/* MRSHPC IRQs setting */
61
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{ 0, 0, 12, 0x0f- 0 ,BCR_ILCRE}, /* PCIRQ3 */
62
-
{ 11, 0, 8, 0x0f-11 ,BCR_ILCRE}, /* PCIRQ2 */
63
-
{ 9, 0, 4, 0x0f- 9 ,BCR_ILCRE}, /* PCIRQ1 */
64
-
{ 7, 0, 0, 0x0f- 7 ,BCR_ILCRE}, /* PCIRQ0 */
100
+
{ 0, 4, 12, 0x0f- 0, }, /* PCIRQ3 */
101
+
{ 11, 4, 8, 0x0f-11, }, /* PCIRQ2 */
102
+
{ 9, 4, 4, 0x0f- 9, }, /* PCIRQ1 */
103
+
{ 7, 4, 0, 0x0f- 7, }, /* PCIRQ0 */
65
104
/* #2, #13 are allocated for SLOT IRQ #1 and #2 (for now) */
66
105
/* NOTE: #2 and #13 are not used on PC */
67
-
{ 13, 0, 4, 0x0f-13 ,BCR_ILCRG}, /* SLOTIRQ2 */
68
-
{ 2, 0, 0, 0x0f- 2 ,BCR_ILCRG}, /* SLOTIRQ1 */
106
+
{ 13, 6, 4, 0x0f-13, }, /* SLOTIRQ2 */
107
+
{ 2, 6, 0, 0x0f- 2, }, /* SLOTIRQ1 */
69
108
#endif
109
+
};
110
+
111
+
static unsigned long ipr_offsets[] = {
112
+
BCR_ILCRA,
113
+
BCR_ILCRB,
114
+
BCR_ILCRC,
115
+
BCR_ILCRD,
116
+
BCR_ILCRE,
117
+
BCR_ILCRF,
118
+
BCR_ILCRG,
119
+
};
120
+
121
+
static struct ipr_desc ipr_irq_desc = {
122
+
.ipr_offsets = ipr_offsets,
123
+
.nr_offsets = ARRAY_SIZE(ipr_offsets),
124
+
125
+
.ipr_data = ipr_irq_table,
126
+
.nr_irqs = ARRAY_SIZE(ipr_irq_table),
127
+
.chip = {
128
+
.name = "IPR-se770x",
129
+
},
70
130
};
71
131
72
132
/*
···
104
122
ctrl_outw(0, BCR_ILCRF);
105
123
ctrl_outw(0, BCR_ILCRG);
106
124
107
-
make_se770x_irq(se770x_ipr_map, ARRAY_SIZE(se770x_ipr_map));
125
+
register_ipr_controller(&ipr_irq_desc);
108
126
}
+12
-3
arch/sh/boards/se/7722/irq.c
+12
-3
arch/sh/boards/se/7722/irq.c
···
19
19
#define INTC_INTMSK0 0xFFD00044
20
20
#define INTC_INTMSKCLR0 0xFFD00064
21
21
22
+
struct se7722_data {
23
+
unsigned char irq;
24
+
unsigned char ipr_idx;
25
+
unsigned char shift;
26
+
unsigned short priority;
27
+
unsigned long addr;
28
+
};
29
+
30
+
22
31
static void disable_se7722_irq(unsigned int irq)
23
32
{
24
-
struct ipr_data *p = get_irq_chip_data(irq);
33
+
struct se7722_data *p = get_irq_chip_data(irq);
25
34
ctrl_outw( ctrl_inw( p->addr ) | p->priority , p->addr );
26
35
}
27
36
28
37
static void enable_se7722_irq(unsigned int irq)
29
38
{
30
-
struct ipr_data *p = get_irq_chip_data(irq);
39
+
struct se7722_data *p = get_irq_chip_data(irq);
31
40
ctrl_outw( ctrl_inw( p->addr ) & ~p->priority , p->addr );
32
41
}
33
42
···
47
38
.mask_ack = disable_se7722_irq,
48
39
};
49
40
50
-
static struct ipr_data ipr_irq_table[] = {
41
+
static struct se7722_data ipr_irq_table[] = {
51
42
/* irq ,idx,sft, priority , addr */
52
43
{ MRSHPC_IRQ0 , 0 , 0 , MRSHPC_BIT0 , IRQ01_MASK } ,
53
44
{ MRSHPC_IRQ1 , 0 , 0 , MRSHPC_BIT1 , IRQ01_MASK } ,
+25
-38
arch/sh/boards/se/7751/irq.c
+25
-38
arch/sh/boards/se/7751/irq.c
···
14
14
#include <asm/irq.h>
15
15
#include <asm/se7751.h>
16
16
17
-
static struct ipr_data se7751_ipr_map[] = {
18
-
/* Leave old Solution Engine code in for reference. */
19
-
#if defined(CONFIG_SH_SOLUTION_ENGINE)
20
-
/*
21
-
* Super I/O (Just mimic PC):
22
-
* 1: keyboard
23
-
* 3: serial 0
24
-
* 4: serial 1
25
-
* 5: printer
26
-
* 6: floppy
27
-
* 8: rtc
28
-
* 12: mouse
29
-
* 14: ide0
30
-
*/
31
-
{ 14, BCR_ILCRA, 2, 0x0f-14 },
32
-
{ 12, BCR_ILCRA, 1, 0x0f-12 },
33
-
{ 8, BCR_ILCRB, 1, 0x0f- 8 },
34
-
{ 6, BCR_ILCRC, 3, 0x0f- 6 },
35
-
{ 5, BCR_ILCRC, 2, 0x0f- 5 },
36
-
{ 4, BCR_ILCRC, 1, 0x0f- 4 },
37
-
{ 3, BCR_ILCRC, 0, 0x0f- 3 },
38
-
{ 1, BCR_ILCRD, 3, 0x0f- 1 },
39
-
40
-
{ 10, BCR_ILCRD, 1, 0x0f-10 }, /* LAN */
41
-
42
-
{ 0, BCR_ILCRE, 3, 0x0f- 0 }, /* PCIRQ3 */
43
-
{ 11, BCR_ILCRE, 2, 0x0f-11 }, /* PCIRQ2 */
44
-
{ 9, BCR_ILCRE, 1, 0x0f- 9 }, /* PCIRQ1 */
45
-
{ 7, BCR_ILCRE, 0, 0x0f- 7 }, /* PCIRQ0 */
46
-
47
-
/* #2, #13 are allocated for SLOT IRQ #1 and #2 (for now) */
48
-
/* NOTE: #2 and #13 are not used on PC */
49
-
{ 13, BCR_ILCRG, 1, 0x0f-13 }, /* SLOTIRQ2 */
50
-
{ 2, BCR_ILCRG, 0, 0x0f- 2 }, /* SLOTIRQ1 */
51
-
#elif defined(CONFIG_SH_7751_SOLUTION_ENGINE)
52
-
{ 13, BCR_ILCRD, 3, 2 },
17
+
static struct ipr_data ipr_irq_table[] = {
18
+
{ 13, 3, 3, 2 },
53
19
/* Add additional entries here as drivers are added and tested. */
54
-
#endif
20
+
};
21
+
22
+
static unsigned long ipr_offsets[] = {
23
+
BCR_ILCRA,
24
+
BCR_ILCRB,
25
+
BCR_ILCRC,
26
+
BCR_ILCRD,
27
+
BCR_ILCRE,
28
+
BCR_ILCRF,
29
+
BCR_ILCRG,
30
+
};
31
+
32
+
static struct ipr_desc ipr_irq_desc = {
33
+
.ipr_offsets = ipr_offsets,
34
+
.nr_offsets = ARRAY_SIZE(ipr_offsets),
35
+
36
+
.ipr_data = ipr_irq_table,
37
+
.nr_irqs = ARRAY_SIZE(ipr_irq_table),
38
+
39
+
.chip = {
40
+
.name = "IPR-se7751",
41
+
},
55
42
};
56
43
57
44
/*
···
46
59
*/
47
60
void __init init_7751se_IRQ(void)
48
61
{
49
-
make_ipr_irq(se7751_ipr_map, ARRAY_SIZE(se7751_ipr_map));
62
+
register_ipr_controller(&ipr_irq_desc);
50
63
}
+22
-6
arch/sh/boards/sh03/setup.c
+22
-6
arch/sh/boards/sh03/setup.c
···
15
15
#include <asm/sh03/sh03.h>
16
16
#include <asm/addrspace.h>
17
17
18
-
static struct ipr_data sh03_ipr_map[] = {
19
-
{ IRL0_IRQ, IRL0_IPR_ADDR, IRL0_IPR_POS, IRL0_PRIORITY },
20
-
{ IRL1_IRQ, IRL1_IPR_ADDR, IRL1_IPR_POS, IRL1_PRIORITY },
21
-
{ IRL2_IRQ, IRL2_IPR_ADDR, IRL2_IPR_POS, IRL2_PRIORITY },
22
-
{ IRL3_IRQ, IRL3_IPR_ADDR, IRL3_IPR_POS, IRL3_PRIORITY },
18
+
static struct ipr_data ipr_irq_table[] = {
19
+
{ IRL0_IRQ, 0, IRL0_IPR_POS, IRL0_PRIORITY },
20
+
{ IRL1_IRQ, 0, IRL1_IPR_POS, IRL1_PRIORITY },
21
+
{ IRL2_IRQ, 0, IRL2_IPR_POS, IRL2_PRIORITY },
22
+
{ IRL3_IRQ, 0, IRL3_IPR_POS, IRL3_PRIORITY },
23
+
};
24
+
25
+
static unsigned long ipr_offsets[] = {
26
+
INTC_IPRD,
27
+
};
28
+
29
+
static struct ipr_desc ipr_irq_desc = {
30
+
.ipr_offsets = ipr_offsets,
31
+
.nr_offsets = ARRAY_SIZE(ipr_offsets),
32
+
33
+
.ipr_data = ipr_irq_table,
34
+
.nr_irqs = ARRAY_SIZE(ipr_irq_table),
35
+
36
+
.chip = {
37
+
.name = "IPR-sh03",
38
+
},
23
39
};
24
40
25
41
static void __init init_sh03_IRQ(void)
26
42
{
27
43
ctrl_outw(ctrl_inw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR);
28
-
make_ipr_irq(sh03_ipr_map, ARRAY_SIZE(sh03_ipr_map));
44
+
register_ipr_controller(&ipr_irq_desc);
29
45
}
30
46
31
47
extern void *cf_io_base;
+23
-7
arch/sh/boards/shmin/setup.c
+23
-7
arch/sh/boards/shmin/setup.c
···
6
6
* SHMIN Support.
7
7
*/
8
8
#include <linux/init.h>
9
+
#include <linux/irq.h>
9
10
#include <asm/machvec.h>
10
11
#include <asm/shmin.h>
11
12
#include <asm/clock.h>
12
-
#include <asm/irq.h>
13
13
#include <asm/io.h>
14
14
15
15
#define PFC_PHCR 0xa400010eUL
16
16
#define INTC_ICR1 0xa4000010UL
17
17
#define INTC_IPRC 0xa4000016UL
18
18
19
-
static struct ipr_data shmin_ipr_map[] = {
20
-
{ .irq=32, .addr=INTC_IPRC, .shift= 0, .priority=0 },
21
-
{ .irq=33, .addr=INTC_IPRC, .shift= 4, .priority=0 },
22
-
{ .irq=34, .addr=INTC_IPRC, .shift= 8, .priority=8 },
23
-
{ .irq=35, .addr=INTC_IPRC, .shift=12, .priority=0 },
19
+
static struct ipr_data ipr_irq_table[] = {
20
+
{ 32, 0, 0, 0 },
21
+
{ 33, 0, 4, 0 },
22
+
{ 34, 0, 8, 8 },
23
+
{ 35, 0, 12, 0 },
24
+
};
25
+
26
+
static unsigned long ipr_offsets[] = {
27
+
INTC_IPRC,
28
+
};
29
+
30
+
static struct ipr_desc ipr_irq_desc = {
31
+
.ipr_offsets = ipr_offsets,
32
+
.nr_offsets = ARRAY_SIZE(ipr_offsets),
33
+
34
+
.ipr_data = ipr_irq_table,
35
+
.nr_irqs = ARRAY_SIZE(ipr_irq_table),
36
+
37
+
.chip = {
38
+
.name = "IPR-shmin",
39
+
},
24
40
};
25
41
26
42
static void __init init_shmin_irq(void)
27
43
{
28
44
ctrl_outw(0x2a00, PFC_PHCR); // IRQ0-3=IRQ
29
45
ctrl_outw(0x0aaa, INTC_ICR1); // IRQ0-3=IRQ-mode,Low-active.
30
-
make_ipr_irq(shmin_ipr_map, ARRAY_SIZE(shmin_ipr_map));
46
+
register_ipr_controller(&ipr_irq_desc);
31
47
}
32
48
33
49
static void __iomem *shmin_ioport_map(unsigned long port, unsigned int size)
+22
-6
arch/sh/boards/snapgear/setup.c
+22
-6
arch/sh/boards/snapgear/setup.c
···
68
68
* IRL3 = crypto
69
69
*/
70
70
71
-
static struct ipr_data snapgear_ipr_map[] = {
72
-
make_ipr_irq(IRL0_IRQ, IRL0_IPR_ADDR, IRL0_IPR_POS, IRL0_PRIORITY);
73
-
make_ipr_irq(IRL1_IRQ, IRL1_IPR_ADDR, IRL1_IPR_POS, IRL1_PRIORITY);
74
-
make_ipr_irq(IRL2_IRQ, IRL2_IPR_ADDR, IRL2_IPR_POS, IRL2_PRIORITY);
75
-
make_ipr_irq(IRL3_IRQ, IRL3_IPR_ADDR, IRL3_IPR_POS, IRL3_PRIORITY);
71
+
static struct ipr_data ipr_irq_table[] = {
72
+
{ IRL0_IRQ, 0, IRL0_IPR_POS, IRL0_PRIORITY },
73
+
{ IRL1_IRQ, 0, IRL1_IPR_POS, IRL1_PRIORITY },
74
+
{ IRL2_IRQ, 0, IRL2_IPR_POS, IRL2_PRIORITY },
75
+
{ IRL3_IRQ, 0, IRL3_IPR_POS, IRL3_PRIORITY },
76
+
};
77
+
78
+
static unsigned long ipr_offsets[] = {
79
+
INTC_IPRD,
80
+
};
81
+
82
+
static struct ipr_desc ipr_irq_desc = {
83
+
.ipr_offsets = ipr_offsets,
84
+
.nr_offsets = ARRAY_SIZE(ipr_offsets),
85
+
86
+
.ipr_data = ipr_irq_table,
87
+
.nr_irqs = ARRAY_SIZE(ipr_irq_table),
88
+
89
+
.chip = {
90
+
.name = "IPR-snapgear",
91
+
},
76
92
};
77
93
78
94
static void __init init_snapgear_IRQ(void)
···
98
82
99
83
printk("Setup SnapGear IRQ/IPR ...\n");
100
84
101
-
make_ipr_irq(snapgear_ipr_map, ARRAY_SIZE(snapgear_ipr_map));
85
+
register_ipr_controller(&ipr_irq_desc);
102
86
}
103
87
104
88
/*
+20
-2
arch/sh/boards/titan/setup.c
+20
-2
arch/sh/boards/titan/setup.c
···
12
12
#include <asm/titan.h>
13
13
#include <asm/io.h>
14
14
15
-
static struct ipr_data titan_ipr_map[] = {
15
+
static struct ipr_data ipr_irq_table[] = {
16
16
/* IRQ, IPR idx, shift, prio */
17
17
{ TITAN_IRQ_WAN, 3, 12, 8 }, /* eth0 (WAN) */
18
18
{ TITAN_IRQ_LAN, 3, 8, 8 }, /* eth1 (LAN) */
···
20
20
{ TITAN_IRQ_USB, 3, 0, 8 }, /* mPCI B (bottom), USB */
21
21
};
22
22
23
+
static unsigned long ipr_offsets[] = { /* stolen from setup-sh7750.c */
24
+
0xffd00004UL, /* 0: IPRA */
25
+
0xffd00008UL, /* 1: IPRB */
26
+
0xffd0000cUL, /* 2: IPRC */
27
+
0xffd00010UL, /* 3: IPRD */
28
+
};
29
+
30
+
static struct ipr_desc ipr_irq_desc = {
31
+
.ipr_offsets = ipr_offsets,
32
+
.nr_offsets = ARRAY_SIZE(ipr_offsets),
33
+
34
+
.ipr_data = ipr_irq_table,
35
+
.nr_irqs = ARRAY_SIZE(ipr_irq_table),
36
+
37
+
.chip = {
38
+
.name = "IPR-titan",
39
+
},
40
+
};
23
41
static void __init init_titan_irq(void)
24
42
{
25
43
/* enable individual interrupt mode for externals */
26
44
ipr_irq_enable_irlm();
27
45
/* register ipr irqs */
28
-
make_ipr_irq(titan_ipr_map, ARRAY_SIZE(titan_ipr_map));
46
+
register_ipr_controller(&ipr_irq_desc);
29
47
}
30
48
31
49
static struct sh_machine_vector mv_titan __initmv = {
+29
-30
arch/sh/kernel/cpu/irq/ipr.c
+29
-30
arch/sh/kernel/cpu/irq/ipr.c
···
22
22
#include <linux/io.h>
23
23
#include <linux/interrupt.h>
24
24
25
+
static inline struct ipr_desc *get_ipr_desc(unsigned int irq)
26
+
{
27
+
struct irq_chip *chip = get_irq_chip(irq);
28
+
return (void *)((char *)chip - offsetof(struct ipr_desc, chip));
29
+
}
30
+
25
31
static void disable_ipr_irq(unsigned int irq)
26
32
{
27
33
struct ipr_data *p = get_irq_chip_data(irq);
34
+
unsigned long addr = get_ipr_desc(irq)->ipr_offsets[p->ipr_idx];
28
35
/* Set the priority in IPR to 0 */
29
-
ctrl_outw(ctrl_inw(p->addr) & (0xffff ^ (0xf << p->shift)), p->addr);
36
+
ctrl_outw(ctrl_inw(addr) & (0xffff ^ (0xf << p->shift)), addr);
30
37
}
31
38
32
39
static void enable_ipr_irq(unsigned int irq)
33
40
{
34
41
struct ipr_data *p = get_irq_chip_data(irq);
42
+
unsigned long addr = get_ipr_desc(irq)->ipr_offsets[p->ipr_idx];
35
43
/* Set priority in IPR back to original value */
36
-
ctrl_outw(ctrl_inw(p->addr) | (p->priority << p->shift), p->addr);
44
+
ctrl_outw(ctrl_inw(addr) | (p->priority << p->shift), addr);
37
45
}
38
46
39
-
static struct irq_chip ipr_irq_chip = {
40
-
.name = "IPR",
41
-
.mask = disable_ipr_irq,
42
-
.unmask = enable_ipr_irq,
43
-
.mask_ack = disable_ipr_irq,
44
-
};
47
+
/*
48
+
* The shift value is now the number of bits to shift, not the number of
49
+
* bits/4. This is to make it easier to read the value directly from the
50
+
* datasheets. The IPR address is calculated using the ipr_offset table.
51
+
*/
45
52
46
-
unsigned int map_ipridx_to_addr(int idx) __attribute__ ((weak));
47
-
unsigned int map_ipridx_to_addr(int idx)
48
-
{
49
-
return 0;
50
-
}
51
-
52
-
void make_ipr_irq(struct ipr_data *table, unsigned int nr_irqs)
53
+
void register_ipr_controller(struct ipr_desc *desc)
53
54
{
54
55
int i;
55
56
56
-
for (i = 0; i < nr_irqs; i++) {
57
-
unsigned int irq = table[i].irq;
57
+
desc->chip.mask = disable_ipr_irq;
58
+
desc->chip.unmask = enable_ipr_irq;
59
+
desc->chip.mask_ack = disable_ipr_irq;
58
60
59
-
if (!irq)
60
-
irq = table[i].irq = i;
61
+
for (i = 0; i < desc->nr_irqs; i++) {
62
+
struct ipr_data *p = desc->ipr_data + i;
61
63
62
-
/* could the IPR index be mapped, if not we ignore this */
63
-
if (!table[i].addr) {
64
-
table[i].addr = map_ipridx_to_addr(table[i].ipr_idx);
65
-
if (!table[i].addr)
66
-
continue;
67
-
}
64
+
BUG_ON(p->ipr_idx >= desc->nr_offsets);
65
+
BUG_ON(!desc->ipr_offsets[p->ipr_idx]);
68
66
69
-
disable_irq_nosync(irq);
70
-
set_irq_chip_and_handler_name(irq, &ipr_irq_chip,
67
+
disable_irq_nosync(p->irq);
68
+
set_irq_chip_and_handler_name(p->irq, &desc->chip,
71
69
handle_level_irq, "level");
72
-
set_irq_chip_data(irq, &table[i]);
73
-
enable_ipr_irq(irq);
70
+
set_irq_chip_data(p->irq, p);
71
+
disable_ipr_irq(p->irq);
74
72
}
75
73
}
76
-
EXPORT_SYMBOL(make_ipr_irq);
74
+
75
+
EXPORT_SYMBOL(register_ipr_controller);
77
76
78
77
#if !defined(CONFIG_CPU_HAS_PINT_IRQ)
79
78
int ipr_irq_demux(int irq)
+14
-10
arch/sh/kernel/cpu/sh2/setup-sh7619.c
+14
-10
arch/sh/kernel/cpu/sh2/setup-sh7619.c
···
52
52
}
53
53
__initcall(sh7619_devices_setup);
54
54
55
-
static struct ipr_data sh7619_ipr_map[] = {
55
+
static struct ipr_data ipr_irq_table[] = {
56
56
{ 86, 0, 4, 2 }, /* CMI0 */
57
57
{ 88, 1, 12, 3 }, /* SCIF0_ERI */
58
58
{ 89, 1, 12, 3 }, /* SCIF0_RXI */
···
68
68
{ 99, 1, 4, 3 }, /* SCIF2_TXI */
69
69
};
70
70
71
-
static unsigned int ipr_offsets[] = {
71
+
static unsigned long ipr_offsets[] = {
72
72
0xf8080000, /* IPRC */
73
73
0xf8080002, /* IPRD */
74
74
0xf8080004, /* IPRE */
···
76
76
0xf8080008, /* IPRG */
77
77
};
78
78
79
-
/* given the IPR index return the address of the IPR register */
80
-
unsigned int map_ipridx_to_addr(int idx)
81
-
{
82
-
if (unlikely(idx >= ARRAY_SIZE(ipr_offsets)))
83
-
return 0;
84
-
return ipr_offsets[idx];
85
-
}
79
+
static struct ipr_desc ipr_irq_desc = {
80
+
.ipr_offsets = ipr_offsets,
81
+
.nr_offsets = ARRAY_SIZE(ipr_offsets),
82
+
83
+
.ipr_data = ipr_irq_table,
84
+
.nr_irqs = ARRAY_SIZE(ipr_irq_table),
85
+
86
+
.chip = {
87
+
.name = "IPR-sh7619",
88
+
},
89
+
};
86
90
87
91
void __init init_IRQ_ipr(void)
88
92
{
89
-
make_ipr_irq(sh7619_ipr_map, ARRAY_SIZE(sh7619_ipr_map));
93
+
register_ipr_controller(&ipr_irq_desc);
90
94
}
+14
-10
arch/sh/kernel/cpu/sh2a/setup-sh7206.c
+14
-10
arch/sh/kernel/cpu/sh2a/setup-sh7206.c
···
57
57
}
58
58
__initcall(sh7206_devices_setup);
59
59
60
-
static struct ipr_data sh7206_ipr_map[] = {
60
+
static struct ipr_data ipr_irq_table[] = {
61
61
{ 140, 7, 12, 2 }, /* CMI0 */
62
62
{ 164, 8, 4, 2 }, /* MTU2_TGI1A */
63
63
{ 240, 13, 12, 3 }, /* SCIF0_BRI */
···
78
78
{ 255, 13, 0, 3 }, /* SCIF3_TXI */
79
79
};
80
80
81
-
static unsigned int ipr_offsets[] = {
81
+
static unsigned long ipr_offsets[] = {
82
82
0xfffe0818, /* IPR01 */
83
83
0xfffe081a, /* IPR02 */
84
84
0, /* unused */
···
95
95
0xfffe0c10, /* IPR14 */
96
96
};
97
97
98
-
/* given the IPR index return the address of the IPR register */
99
-
unsigned int map_ipridx_to_addr(int idx)
100
-
{
101
-
if (unlikely(idx >= ARRAY_SIZE(ipr_offsets)))
102
-
return 0;
103
-
return ipr_offsets[idx];
104
-
}
98
+
static struct ipr_desc ipr_irq_desc = {
99
+
.ipr_offsets = ipr_offsets,
100
+
.nr_offsets = ARRAY_SIZE(ipr_offsets),
101
+
102
+
.ipr_data = ipr_irq_table,
103
+
.nr_irqs = ARRAY_SIZE(ipr_irq_table),
104
+
105
+
.chip = {
106
+
.name = "IPR-sh7206",
107
+
},
108
+
};
105
109
106
110
void __init init_IRQ_ipr(void)
107
111
{
108
-
make_ipr_irq(sh7206_ipr_map, ARRAY_SIZE(sh7206_ipr_map));
112
+
register_ipr_controller(&ipr_irq_desc);
109
113
}
+22
-18
arch/sh/kernel/cpu/sh3/setup-sh7705.c
+22
-18
arch/sh/kernel/cpu/sh3/setup-sh7705.c
···
48
48
}
49
49
__initcall(sh7705_devices_setup);
50
50
51
-
static struct ipr_data sh7705_ipr_map[] = {
51
+
static struct ipr_data ipr_irq_table[] = {
52
52
/* IRQ, IPR-idx, shift, priority */
53
53
{ 16, 0, 12, 2 }, /* TMU0 TUNI*/
54
54
{ 17, 0, 8, 2 }, /* TMU1 TUNI */
···
70
70
};
71
71
72
72
static unsigned long ipr_offsets[] = {
73
-
0xFFFFFEE2 /* 0: IPRA */
74
-
, 0xFFFFFEE4 /* 1: IPRB */
75
-
, 0xA4000016 /* 2: IPRC */
76
-
, 0xA4000018 /* 3: IPRD */
77
-
, 0xA400001A /* 4: IPRE */
78
-
, 0xA4080000 /* 5: IPRF */
79
-
, 0xA4080002 /* 6: IPRG */
80
-
, 0xA4080004 /* 7: IPRH */
73
+
0xFFFFFEE2, /* 0: IPRA */
74
+
0xFFFFFEE4, /* 1: IPRB */
75
+
0xA4000016, /* 2: IPRC */
76
+
0xA4000018, /* 3: IPRD */
77
+
0xA400001A, /* 4: IPRE */
78
+
0xA4080000, /* 5: IPRF */
79
+
0xA4080002, /* 6: IPRG */
80
+
0xA4080004, /* 7: IPRH */
81
81
};
82
82
83
-
/* given the IPR index return the address of the IPR register */
84
-
unsigned int map_ipridx_to_addr(int idx)
85
-
{
86
-
if (idx >= ARRAY_SIZE(ipr_offsets))
87
-
return 0;
88
-
return ipr_offsets[idx];
89
-
}
83
+
static struct ipr_desc ipr_irq_desc = {
84
+
.ipr_offsets = ipr_offsets,
85
+
.nr_offsets = ARRAY_SIZE(ipr_offsets),
90
86
91
-
void __init init_IRQ_ipr()
87
+
.ipr_data = ipr_irq_table,
88
+
.nr_irqs = ARRAY_SIZE(ipr_irq_table),
89
+
90
+
.chip = {
91
+
.name = "IPR-sh7705",
92
+
},
93
+
};
94
+
95
+
void __init init_IRQ_ipr(void)
92
96
{
93
-
make_ipr_irq(sh7705_ipr_map, ARRAY_SIZE(sh7705_ipr_map));
97
+
register_ipr_controller(&ipr_irq_desc);
94
98
}
+58
-24
arch/sh/kernel/cpu/sh3/setup-sh7709.c
+58
-24
arch/sh/kernel/cpu/sh3/setup-sh7709.c
···
52
52
}
53
53
__initcall(sh7709_devices_setup);
54
54
55
-
#define IPRx(A,N) .addr=A, .shift=N
56
-
#define IPRA(N) IPRx(0xfffffee2UL,N)
57
-
#define IPRB(N) IPRx(0xfffffee4UL,N)
58
-
#define IPRC(N) IPRx(0xa4000016UL,N)
59
-
#define IPRD(N) IPRx(0xa4000018UL,N)
60
-
#define IPRE(N) IPRx(0xa400001aUL,N)
55
+
static struct ipr_data ipr_irq_table[] = {
56
+
{ 16, 0, 12, 2 }, /* TMU TUNI0 */
57
+
{ 17, 0, 8, 4 }, /* TMU TUNI1 */
58
+
{ 18, 0, 4, 1 }, /* TMU TUNI1 */
59
+
{ 19, 0, 4, 1 }, /* TMU TUNI1 */
60
+
{ 20, 0, 0, 2 }, /* RTC CUI */
61
+
{ 21, 0, 0, 2 }, /* RTC CUI */
62
+
{ 22, 0, 0, 2 }, /* RTC CUI */
61
63
62
-
static struct ipr_data sh7709_ipr_map[] = {
63
-
[16] = { IPRA(12), 2 }, /* TMU TUNI0 */
64
-
[17] = { IPRA(8), 4 }, /* TMU TUNI1 */
65
-
[18 ... 19] = { IPRA(4), 1 }, /* TMU TUNI1 */
66
-
[20 ... 22] = { IPRA(0), 2 }, /* RTC CUI */
67
-
[23 ... 26] = { IPRB(4), 3 }, /* SCI */
68
-
[27] = { IPRB(12), 2 }, /* WDT ITI */
69
-
[32] = { IPRC(0), 1 }, /* IRQ 0 */
70
-
[33] = { IPRC(4), 1 }, /* IRQ 1 */
71
-
[34] = { IPRC(8), 1 }, /* IRQ 2 APM */
72
-
[35] = { IPRC(12), 1 }, /* IRQ 3 TOUCHSCREEN */
73
-
[36] = { IPRD(0), 1 }, /* IRQ 4 */
74
-
[37] = { IPRD(4), 1 }, /* IRQ 5 */
75
-
[48 ... 51] = { IPRE(12), 7 }, /* DMA */
76
-
[52 ... 55] = { IPRE(8), 3 }, /* IRDA */
77
-
[56 ... 59] = { IPRE(4), 3 }, /* SCIF */
64
+
{ 23, 1, 4, 3 }, /* SCI */
65
+
{ 24, 1, 4, 3 }, /* SCI */
66
+
{ 25, 1, 4, 3 }, /* SCI */
67
+
{ 26, 1, 4, 3 }, /* SCI */
68
+
{ 27, 1, 12, 3 }, /* WDT ITI */
69
+
70
+
{ 32, 2, 0, 1 }, /* IRQ 0 */
71
+
{ 33, 2, 4, 1 }, /* IRQ 1 */
72
+
{ 34, 2, 8, 1 }, /* IRQ 2 APM */
73
+
{ 35, 2, 12, 1 }, /* IRQ 3 TOUCHSCREEN */
74
+
75
+
{ 36, 3, 0, 1 }, /* IRQ 4 */
76
+
{ 37, 3, 4, 1 }, /* IRQ 5 */
77
+
78
+
{ 48, 4, 12, 7 }, /* DMA */
79
+
{ 49, 4, 12, 7 }, /* DMA */
80
+
{ 50, 4, 12, 7 }, /* DMA */
81
+
{ 51, 4, 12, 7 }, /* DMA */
82
+
83
+
{ 52, 4, 8, 3 }, /* IRDA */
84
+
{ 53, 4, 8, 3 }, /* IRDA */
85
+
{ 54, 4, 8, 3 }, /* IRDA */
86
+
{ 55, 4, 8, 3 }, /* IRDA */
87
+
88
+
{ 56, 4, 4, 3 }, /* SCIF */
89
+
{ 57, 4, 4, 3 }, /* SCIF */
90
+
{ 58, 4, 4, 3 }, /* SCIF */
91
+
{ 59, 4, 4, 3 }, /* SCIF */
78
92
};
79
93
80
-
void __init init_IRQ_ipr()
94
+
static unsigned long ipr_offsets[] = {
95
+
0xfffffee2, /* 0: IPRA */
96
+
0xfffffee4, /* 1: IPRB */
97
+
0xa4000016, /* 2: IPRC */
98
+
0xa4000018, /* 3: IPRD */
99
+
0xa400001a, /* 4: IPRE */
100
+
};
101
+
102
+
static struct ipr_desc ipr_irq_desc = {
103
+
.ipr_offsets = ipr_offsets,
104
+
.nr_offsets = ARRAY_SIZE(ipr_offsets),
105
+
106
+
.ipr_data = ipr_irq_table,
107
+
.nr_irqs = ARRAY_SIZE(ipr_irq_table),
108
+
109
+
.chip = {
110
+
.name = "IPR-sh7709",
111
+
},
112
+
};
113
+
114
+
void __init init_IRQ_ipr(void)
81
115
{
82
-
make_ipr_irq(sh7709_ipr_map, ARRAY_SIZE(sh7709_ipr_map));
116
+
register_ipr_controller(&ipr_irq_desc);
83
117
}
+23
-19
arch/sh/kernel/cpu/sh3/setup-sh7710.c
+23
-19
arch/sh/kernel/cpu/sh3/setup-sh7710.c
···
49
49
}
50
50
__initcall(sh7710_devices_setup);
51
51
52
-
static struct ipr_data sh7710_ipr_map[] = {
52
+
static struct ipr_data ipr_irq_table[] = {
53
53
/* IRQ, IPR-idx, shift, priority */
54
54
{ 16, 0, 12, 2 }, /* TMU0 TUNI*/
55
55
{ 17, 0, 8, 2 }, /* TMU1 TUNI */
···
78
78
};
79
79
80
80
static unsigned long ipr_offsets[] = {
81
-
0xA414FEE2 /* 0: IPRA */
82
-
, 0xA414FEE4 /* 1: IPRB */
83
-
, 0xA4140016 /* 2: IPRC */
84
-
, 0xA4140018 /* 3: IPRD */
85
-
, 0xA414001A /* 4: IPRE */
86
-
, 0xA4080000 /* 5: IPRF */
87
-
, 0xA4080002 /* 6: IPRG */
88
-
, 0xA4080004 /* 7: IPRH */
89
-
, 0xA4080006 /* 8: IPRI */
81
+
0xA414FEE2, /* 0: IPRA */
82
+
0xA414FEE4, /* 1: IPRB */
83
+
0xA4140016, /* 2: IPRC */
84
+
0xA4140018, /* 3: IPRD */
85
+
0xA414001A, /* 4: IPRE */
86
+
0xA4080000, /* 5: IPRF */
87
+
0xA4080002, /* 6: IPRG */
88
+
0xA4080004, /* 7: IPRH */
89
+
0xA4080006, /* 8: IPRI */
90
90
};
91
91
92
-
/* given the IPR index return the address of the IPR register */
93
-
unsigned int map_ipridx_to_addr(int idx)
94
-
{
95
-
if (idx >= ARRAY_SIZE(ipr_offsets))
96
-
return 0;
97
-
return ipr_offsets[idx];
98
-
}
92
+
static struct ipr_desc ipr_irq_desc = {
93
+
.ipr_offsets = ipr_offsets,
94
+
.nr_offsets = ARRAY_SIZE(ipr_offsets),
99
95
100
-
void __init init_IRQ_ipr()
96
+
.ipr_data = ipr_irq_table,
97
+
.nr_irqs = ARRAY_SIZE(ipr_irq_table),
98
+
99
+
.chip = {
100
+
.name = "IPR-sh7710",
101
+
},
102
+
};
103
+
104
+
void __init init_IRQ_ipr(void)
101
105
{
102
-
make_ipr_irq(sh7710_ipr_map, ARRAY_SIZE(sh7710_ipr_map));
106
+
register_ipr_controller(&ipr_irq_desc);
103
107
}
+38
-22
arch/sh/kernel/cpu/sh4/setup-sh7750.c
+38
-22
arch/sh/kernel/cpu/sh4/setup-sh7750.c
···
82
82
}
83
83
__initcall(sh7750_devices_setup);
84
84
85
-
static struct ipr_data sh7750_ipr_map[] = {
85
+
static struct ipr_data ipr_irq_table[] = {
86
86
/* IRQ, IPR-idx, shift, priority */
87
87
{ 16, 0, 12, 2 }, /* TMU0 TUNI*/
88
88
{ 17, 0, 12, 2 }, /* TMU1 TUNI */
···
106
106
{ 38, 2, 8, 7 }, /* DMAC DMAE */
107
107
};
108
108
109
+
static unsigned long ipr_offsets[] = {
110
+
0xffd00004UL, /* 0: IPRA */
111
+
0xffd00008UL, /* 1: IPRB */
112
+
0xffd0000cUL, /* 2: IPRC */
113
+
0xffd00010UL, /* 3: IPRD */
114
+
};
115
+
116
+
static struct ipr_desc ipr_irq_desc = {
117
+
.ipr_offsets = ipr_offsets,
118
+
.nr_offsets = ARRAY_SIZE(ipr_offsets),
119
+
120
+
.ipr_data = ipr_irq_table,
121
+
.nr_irqs = ARRAY_SIZE(ipr_irq_table),
122
+
123
+
.chip = {
124
+
.name = "IPR-sh7750",
125
+
},
126
+
};
127
+
109
128
#ifdef CONFIG_CPU_SUBTYPE_SH7751
110
-
static struct ipr_data sh7751_ipr_map[] = {
129
+
static struct ipr_data ipr_irq_table_sh7751[] = {
111
130
{ 44, 2, 8, 7 }, /* DMAC DMTE4 */
112
131
{ 45, 2, 8, 7 }, /* DMAC DMTE5 */
113
132
{ 46, 2, 8, 7 }, /* DMAC DMTE6 */
···
137
118
/*{ 72, INTPRI00, 8, ? },*/ /* TMU3 TUNI */
138
119
/*{ 76, INTPRI00, 12, ? },*/ /* TMU4 TUNI */
139
120
};
121
+
122
+
static struct ipr_desc ipr_irq_desc_sh7751 = {
123
+
.ipr_offsets = ipr_offsets,
124
+
.nr_offsets = ARRAY_SIZE(ipr_offsets),
125
+
126
+
.ipr_data = ipr_irq_table_sh7751,
127
+
.nr_irqs = ARRAY_SIZE(ipr_irq_table_sh7751),
128
+
129
+
.chip = {
130
+
.name = "IPR-sh7751",
131
+
},
132
+
};
140
133
#endif
141
134
142
-
static unsigned long ipr_offsets[] = {
143
-
0xffd00004UL, /* 0: IPRA */
144
-
0xffd00008UL, /* 1: IPRB */
145
-
0xffd0000cUL, /* 2: IPRC */
146
-
0xffd00010UL, /* 3: IPRD */
147
-
};
148
-
149
-
/* given the IPR index return the address of the IPR register */
150
-
unsigned int map_ipridx_to_addr(int idx)
135
+
void __init init_IRQ_ipr(void)
151
136
{
152
-
if (idx >= ARRAY_SIZE(ipr_offsets))
153
-
return 0;
154
-
return ipr_offsets[idx];
137
+
register_ipr_controller(&ipr_irq_desc);
138
+
#ifdef CONFIG_CPU_SUBTYPE_SH7751
139
+
register_ipr_controller(&ipr_irq_desc_sh7751);
140
+
#endif
155
141
}
156
142
157
143
#define INTC_ICR 0xffd00000UL
···
166
142
void ipr_irq_enable_irlm(void)
167
143
{
168
144
ctrl_outw(ctrl_inw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR);
169
-
}
170
-
171
-
void __init init_IRQ_ipr()
172
-
{
173
-
make_ipr_irq(sh7750_ipr_map, ARRAY_SIZE(sh7750_ipr_map));
174
-
#ifdef CONFIG_CPU_SUBTYPE_SH7751
175
-
make_ipr_irq(sh7751_ipr_map, ARRAY_SIZE(sh7751_ipr_map));
176
-
#endif
177
145
}
+18
-14
arch/sh/kernel/cpu/sh4/setup-sh7760.c
+18
-14
arch/sh/kernel/cpu/sh4/setup-sh7760.c
···
109
109
},
110
110
};
111
111
112
-
static struct ipr_data sh7760_ipr_map[] = {
112
+
void __init init_IRQ_intc2(void)
113
+
{
114
+
register_intc2_controller(&intc2_irq_desc);
115
+
}
116
+
117
+
static struct ipr_data ipr_irq_table[] = {
113
118
/* IRQ, IPR-idx, shift, priority */
114
119
{ 16, 0, 12, 2 }, /* TMU0 TUNI*/
115
120
{ 17, 0, 8, 2 }, /* TMU1 TUNI */
···
151
146
0xffd00010UL, /* 3: IPRD */
152
147
};
153
148
154
-
/* given the IPR index return the address of the IPR register */
155
-
unsigned int map_ipridx_to_addr(int idx)
156
-
{
157
-
if (idx >= ARRAY_SIZE(ipr_offsets))
158
-
return 0;
159
-
return ipr_offsets[idx];
160
-
}
149
+
static struct ipr_desc ipr_irq_desc = {
150
+
.ipr_offsets = ipr_offsets,
151
+
.nr_offsets = ARRAY_SIZE(ipr_offsets),
161
152
162
-
void __init init_IRQ_intc2(void)
163
-
{
164
-
register_intc2_controller(&intc2_irq_desc);
165
-
}
153
+
.ipr_data = ipr_irq_table,
154
+
.nr_irqs = ARRAY_SIZE(ipr_irq_table),
166
155
167
-
void __init init_IRQ_ipr(void)
156
+
.chip = {
157
+
.name = "IPR-sh7760",
158
+
},
159
+
};
160
+
161
+
void __init init_IRQ_ipr(void)
168
162
{
169
-
make_ipr_irq(sh7760_ipr_map, ARRAY_SIZE(sh7760_ipr_map));
163
+
register_ipr_controller(&ipr_irq_desc);
170
164
}
+13
-8
arch/sh/kernel/cpu/sh4a/setup-sh7722.c
+13
-8
arch/sh/kernel/cpu/sh4a/setup-sh7722.c
···
44
44
}
45
45
__initcall(sh7722_devices_setup);
46
46
47
-
static struct ipr_data sh7722_ipr_map[] = {
47
+
static struct ipr_data ipr_irq_table[] = {
48
48
/* IRQ, IPR-idx, shift, prio */
49
49
{ 16, 0, 12, 2 }, /* TMU0 */
50
50
{ 17, 0, 8, 2 }, /* TMU1 */
···
69
69
0xa408002c, /* 11: IPRL */
70
70
};
71
71
72
-
unsigned int map_ipridx_to_addr(int idx)
73
-
{
74
-
if (unlikely(idx >= ARRAY_SIZE(ipr_offsets)))
75
-
return 0;
76
-
return ipr_offsets[idx];
77
-
}
72
+
static struct ipr_desc ipr_irq_desc = {
73
+
.ipr_offsets = ipr_offsets,
74
+
.nr_offsets = ARRAY_SIZE(ipr_offsets),
75
+
76
+
.ipr_data = ipr_irq_table,
77
+
.nr_irqs = ARRAY_SIZE(ipr_irq_table),
78
+
79
+
.chip = {
80
+
.name = "IPR-sh7722",
81
+
},
82
+
};
78
83
79
84
void __init init_IRQ_ipr(void)
80
85
{
81
-
make_ipr_irq(sh7722_ipr_map, ARRAY_SIZE(sh7722_ipr_map));
86
+
register_ipr_controller(&ipr_irq_desc);
82
87
}
83
88
84
89
void __init plat_mem_setup(void)
+23
include/asm-sh/hw_irq.h
+23
include/asm-sh/hw_irq.h
···
24
24
void register_intc2_controller(struct intc2_desc *);
25
25
void init_IRQ_intc2(void);
26
26
27
+
struct ipr_data {
28
+
unsigned char irq;
29
+
unsigned char ipr_idx; /* Index for the IPR registered */
30
+
unsigned char shift; /* Number of bits to shift the data */
31
+
unsigned char priority; /* The priority */
32
+
};
33
+
34
+
struct ipr_desc {
35
+
unsigned long *ipr_offsets;
36
+
unsigned int nr_offsets;
37
+
struct ipr_data *ipr_data;
38
+
unsigned int nr_irqs;
39
+
struct irq_chip chip;
40
+
};
41
+
42
+
void register_ipr_controller(struct ipr_desc *);
43
+
void init_IRQ_ipr(void);
44
+
45
+
/*
46
+
* Enable individual interrupt mode for external IPR IRQs.
47
+
*/
48
+
void ipr_irq_enable_irlm(void);
49
+
27
50
#endif /* __ASM_SH_HW_IRQ_H */
-30
include/asm-sh/irq.h
-30
include/asm-sh/irq.h
···
31
31
* PINT IRQs
32
32
*/
33
33
void init_IRQ_pint(void);
34
-
35
-
/*
36
-
* The shift value is now the number of bits to shift, not the number of
37
-
* bits/4. This is to make it easier to read the value directly from the
38
-
* datasheets. The IPR address, addr, will be set from ipr_idx via the
39
-
* map_ipridx_to_addr function.
40
-
*/
41
-
struct ipr_data {
42
-
unsigned int irq;
43
-
int ipr_idx; /* Index for the IPR registered */
44
-
int shift; /* Number of bits to shift the data */
45
-
int priority; /* The priority */
46
-
unsigned int addr; /* Address of Interrupt Priority Register */
47
-
};
48
-
49
-
/*
50
-
* Given an IPR IDX, map the value to an IPR register address.
51
-
*/
52
-
unsigned int map_ipridx_to_addr(int idx);
53
-
54
-
/*
55
-
* Enable individual interrupt mode for external IPR IRQs.
56
-
*/
57
-
void ipr_irq_enable_irlm(void);
58
-
59
-
/*
60
-
* Function for "on chip support modules".
61
-
*/
62
-
void make_ipr_irq(struct ipr_data *table, unsigned int nr_irqs);
63
34
void make_imask_irq(unsigned int irq);
64
-
void init_IRQ_ipr(void);
65
35
66
36
static inline int generic_irq_demux(int irq)
67
37
{
-4
include/asm-sh/sh03/io.h
-4
include/asm-sh/sh03/io.h
···
14
14
#define INTC_IPRD 0xffd00010UL
15
15
16
16
#define IRL0_IRQ 2
17
-
#define IRL0_IPR_ADDR INTC_IPRD
18
17
#define IRL0_IPR_POS 3
19
18
#define IRL0_PRIORITY 13
20
19
21
20
#define IRL1_IRQ 5
22
-
#define IRL1_IPR_ADDR INTC_IPRD
23
21
#define IRL1_IPR_POS 2
24
22
#define IRL1_PRIORITY 10
25
23
26
24
#define IRL2_IRQ 8
27
-
#define IRL2_IPR_ADDR INTC_IPRD
28
25
#define IRL2_IPR_POS 1
29
26
#define IRL2_PRIORITY 7
30
27
31
28
#define IRL3_IRQ 11
32
-
#define IRL3_IPR_ADDR INTC_IPRD
33
29
#define IRL3_IPR_POS 0
34
30
#define IRL3_PRIORITY 4
35
31
-4
include/asm-sh/snapgear.h
-4
include/asm-sh/snapgear.h
···
20
20
*/
21
21
22
22
#define IRL0_IRQ 2
23
-
#define IRL0_IPR_ADDR INTC_IPRD
24
23
#define IRL0_IPR_POS 3
25
24
#define IRL0_PRIORITY 13
26
25
27
26
#define IRL1_IRQ 5
28
-
#define IRL1_IPR_ADDR INTC_IPRD
29
27
#define IRL1_IPR_POS 2
30
28
#define IRL1_PRIORITY 10
31
29
32
30
#define IRL2_IRQ 8
33
-
#define IRL2_IPR_ADDR INTC_IPRD
34
31
#define IRL2_IPR_POS 1
35
32
#define IRL2_PRIORITY 7
36
33
37
34
#define IRL3_IRQ 11
38
-
#define IRL3_IPR_ADDR INTC_IPRD
39
35
#define IRL3_IPR_POS 0
40
36
#define IRL3_PRIORITY 4
41
37
#endif