drm/amdgpu: add some required DCE6 registers (v7)

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

To help with the DC port.

v2: add missing masks, add additional registers
v3: more updates
v4: fix accidently dropped changes
v5: add missing nb pstate mask
v6: add vblank, vline masks
v7: add SCL_HORZ_FILTER_INIT regs

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

Alex Deucher 5 years ago 6863660d 9b66d660

+180

2 changed files

expand all

drivers

gpu

drm

amd

include

asic_reg

dce

dce_6_0_d.h

dce_6_0_sh_mask.h

+76

drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_d.h

··· 4444 4444 4445 4445 /* Registers that spilled out of sid.h */ 4446 4446 #define mmDATA_FORMAT 0x1AC0 4447 + #define mmLB0_DATA_FORMAT 0x1AC0 4448 + #define mmLB1_DATA_FORMAT 0x1DC0 4449 + #define mmLB2_DATA_FORMAT 0x40C0 4450 + #define mmLB3_DATA_FORMAT 0x43C0 4451 + #define mmLB4_DATA_FORMAT 0x46C0 4452 + #define mmLB5_DATA_FORMAT 0x49C0 4447 4453 #define mmDESKTOP_HEIGHT 0x1AC1 4454 + #define mmLB0_DESKTOP_HEIGHT 0x1AC1 4455 + #define mmLB1_DESKTOP_HEIGHT 0x1DC1 4456 + #define mmLB2_DESKTOP_HEIGHT 0x40C1 4457 + #define mmLB3_DESKTOP_HEIGHT 0x43C1 4458 + #define mmLB4_DESKTOP_HEIGHT 0x46C1 4459 + #define mmLB5_DESKTOP_HEIGHT 0x49C1 4448 4460 #define mmDC_LB_MEMORY_SPLIT 0x1AC3 4461 + #define mmLB0_DC_LB_MEMORY_SPLIT 0x1AC3 4462 + #define mmLB1_DC_LB_MEMORY_SPLIT 0x1DC3 4463 + #define mmLB2_DC_LB_MEMORY_SPLIT 0x40C3 4464 + #define mmLB3_DC_LB_MEMORY_SPLIT 0x43C3 4465 + #define mmLB4_DC_LB_MEMORY_SPLIT 0x46C3 4466 + #define mmLB5_DC_LB_MEMORY_SPLIT 0x49C3 4467 + #define mmDC_LB_MEM_SIZE 0x1AC4 4468 + #define mmLB0_DC_LB_MEM_SIZE 0x1AC4 4469 + #define mmLB1_DC_LB_MEM_SIZE 0x1DC4 4470 + #define mmLB2_DC_LB_MEM_SIZE 0x40C4 4471 + #define mmLB3_DC_LB_MEM_SIZE 0x43C4 4472 + #define mmLB4_DC_LB_MEM_SIZE 0x46C4 4473 + #define mmLB5_DC_LB_MEM_SIZE 0x49C4 4449 4474 #define mmPRIORITY_A_CNT 0x1AC6 4475 + #define mmLB0_PRIORITY_A_CNT 0x1AC6 4476 + #define mmLB1_PRIORITY_A_CNT 0x1DC6 4477 + #define mmLB2_PRIORITY_A_CNT 0x40C6 4478 + #define mmLB3_PRIORITY_A_CNT 0x43C6 4479 + #define mmLB4_PRIORITY_A_CNT 0x46C6 4480 + #define mmLB5_PRIORITY_A_CNT 0x49C6 4450 4481 #define mmPRIORITY_B_CNT 0x1AC7 4482 + #define mmLB0_PRIORITY_B_CNT 0x1AC7 4483 + #define mmLB1_PRIORITY_B_CNT 0x1DC7 4484 + #define mmLB2_PRIORITY_B_CNT 0x40C7 4485 + #define mmLB3_PRIORITY_B_CNT 0x43C7 4486 + #define mmLB4_PRIORITY_B_CNT 0x46C7 4487 + #define mmLB5_PRIORITY_B_CNT 0x49C7 4451 4488 #define mmDPG_PIPE_ARBITRATION_CONTROL3 0x1B32 4489 + #define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL3 0x1B32 4490 + #define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL3 0x1E32 4491 + #define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL3 0x4132 4492 + #define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL3 0x4432 4493 + #define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL3 0x4732 4494 + #define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL3 0x4A32 4452 4495 #define mmINT_MASK 0x1AD0 4496 + #define mmLB0_INT_MASK 0x1AD0 4497 + #define mmLB1_INT_MASK 0x1DD0 4498 + #define mmLB2_INT_MASK 0x40D0 4499 + #define mmLB3_INT_MASK 0x43D0 4500 + #define mmLB4_INT_MASK 0x46D0 4501 + #define mmLB5_INT_MASK 0x49D0 4453 4502 #define mmVLINE_STATUS 0x1AEE 4503 + #define mmLB0_VLINE_STATUS 0x1AEE 4504 + #define mmLB1_VLINE_STATUS 0x1DEE 4505 + #define mmLB2_VLINE_STATUS 0x40EE 4506 + #define mmLB3_VLINE_STATUS 0x43EE 4507 + #define mmLB4_VLINE_STATUS 0x46EE 4508 + #define mmLB5_VLINE_STATUS 0x49EE 4454 4509 #define mmVBLANK_STATUS 0x1AEF 4510 + #define mmLB0_VBLANK_STATUS 0x1AEF 4511 + #define mmLB1_VBLANK_STATUS 0x1DEF 4512 + #define mmLB2_VBLANK_STATUS 0x40EF 4513 + #define mmLB3_VBLANK_STATUS 0x43EF 4514 + #define mmLB4_VBLANK_STATUS 0x46EF 4515 + #define mmLB5_VBLANK_STATUS 0x49EF 4455 4516 4517 + #define mmSCL_HORZ_FILTER_INIT_RGB_LUMA 0x1B4C 4518 + #define mmSCL0_SCL_HORZ_FILTER_INIT_RGB_LUMA 0x1B4C 4519 + #define mmSCL1_SCL_HORZ_FILTER_INIT_RGB_LUMA 0x1E4C 4520 + #define mmSCL2_SCL_HORZ_FILTER_INIT_RGB_LUMA 0x414C 4521 + #define mmSCL3_SCL_HORZ_FILTER_INIT_RGB_LUMA 0x444C 4522 + #define mmSCL4_SCL_HORZ_FILTER_INIT_RGB_LUMA 0x474C 4523 + #define mmSCL5_SCL_HORZ_FILTER_INIT_RGB_LUMA 0x4A4C 4524 + 4525 + #define mmSCL_HORZ_FILTER_INIT_CHROMA 0x1B4D 4526 + #define mmSCL0_SCL_HORZ_FILTER_INIT_CHROMA 0x1B4D 4527 + #define mmSCL1_SCL_HORZ_FILTER_INIT_CHROMA 0x1E4D 4528 + #define mmSCL2_SCL_HORZ_FILTER_INIT_CHROMA 0x414D 4529 + #define mmSCL3_SCL_HORZ_FILTER_INIT_CHROMA 0x444D 4530 + #define mmSCL4_SCL_HORZ_FILTER_INIT_CHROMA 0x474D 4531 + #define mmSCL5_SCL_HORZ_FILTER_INIT_CHROMA 0x4A4D 4456 4532 4457 4533 #endif

+104

drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h

··· 2076 2076 #define CRTC_CONTROL__CRTC_START_POINT_CNTL__SHIFT 0x0000000c 2077 2077 #define CRTC_CONTROL__CRTC_SYNC_RESET_SEL_MASK 0x00000010L 2078 2078 #define CRTC_CONTROL__CRTC_SYNC_RESET_SEL__SHIFT 0x00000004 2079 + #define CRTC_CONTROL__CRTC_PREFETCH_EN_MASK 0x10000000L 2080 + #define CRTC_CONTROL__CRTC_PREFETCH_EN__SHIFT 0x0000001c 2079 2081 #define CRTC_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN_MASK 0x00000001L 2080 2082 #define CRTC_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN__SHIFT 0x00000000 2081 2083 #define CRTC_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT_MASK 0x0000001eL ··· 6366 6364 #define DPG_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT__SHIFT 0x00000000 6367 6365 #define DPG_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT_MASK 0xffff0000L 6368 6366 #define DPG_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT__SHIFT 0x00000010 6367 + #define DPG_PIPE_ARBITRATION_CONTROL3__URGENCY_WATERMARK_MASK_MASK 0x00030000L 6368 + #define DPG_PIPE_ARBITRATION_CONTROL3__URGENCY_WATERMARK_MASK__SHIFT 0x00000010 6369 6369 #define DPG_PIPE_DPM_CONTROL__DPM_ENABLE_MASK 0x00000001L 6370 6370 #define DPG_PIPE_DPM_CONTROL__DPM_ENABLE__SHIFT 0x00000000 6371 6371 #define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_ENABLE_MASK 0x00000010L ··· 6388 6384 #define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST__SHIFT 0x00000008 6389 6385 #define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK 0x00000010L 6390 6386 #define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT 0x00000004 6387 + #define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK_MASK 0x00003000L 6388 + #define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK__SHIFT 0x0000000c 6391 6389 #define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK 0xffff0000L 6392 6390 #define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK__SHIFT 0x00000010 6393 6391 #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH_MASK 0x00000001L ··· 6412 6406 #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH__SHIFT 0x00000008 6413 6407 #define DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK 0x00000001L 6414 6408 #define DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE__SHIFT 0x00000000 6409 + #define DPG_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK_MASK 0x00003000L 6410 + #define DPG_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK__SHIFT 0x0000000c 6415 6411 #define DPG_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK 0xffff0000L 6416 6412 #define DPG_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK__SHIFT 0x00000010 6417 6413 #define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_MASK 0x00000010L ··· 7264 7256 #define GRPH_CONTROL__GRPH_FORMAT__SHIFT 0x00000008 7265 7257 #define GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT_MASK 0x000c0000L 7266 7258 #define GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT__SHIFT 0x00000012 7259 + #define GRPH_CONTROL__GRPH_ARRAY_MODE_MASK 0x00f00000L 7260 + #define GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT 0x00000014 7267 7261 #define GRPH_CONTROL__GRPH_NUM_BANKS_MASK 0x0000000cL 7268 7262 #define GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT 0x00000002 7269 7263 #define GRPH_CONTROL__GRPH_PIPE_CONFIG_MASK 0x1f000000L ··· 9844 9834 #define XDMA_TEST_DEBUG_INDEX__XDMA_TEST_DEBUG_INDEX__SHIFT 0x00000000 9845 9835 #define XDMA_TEST_DEBUG_INDEX__XDMA_TEST_DEBUG_WRITE_EN_MASK 0x00000100L 9846 9836 #define XDMA_TEST_DEBUG_INDEX__XDMA_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 9837 + 9838 + // DATA_FORMAT 9839 + #define DATA_FORMAT__INTERLEAVE_EN_MASK 0x00000001L 9840 + #define DATA_FORMAT__INTERLEAVE_EN__SHIFT 0x00000000 9841 + #define DATA_FORMAT__RESET_REQ_AT_EOL_MASK 0x00000010L 9842 + #define DATA_FORMAT__RESET_REQ_AT_EOL__SHIFT 0x00000004 9843 + #define DATA_FORMAT__PREFETCH_MASK 0x00001000L 9844 + #define DATA_FORMAT__PREFETCH__SHIFT 0x0000000c 9845 + #define DATA_FORMAT__SOF_READ_PT_MASK 0x001f0000L 9846 + #define DATA_FORMAT__SOF_READ_PT__SHIFT 0x00000010 9847 + #define DATA_FORMAT__REQUEST_MODE_MASK 0x03000000L 9848 + #define DATA_FORMAT__REQUEST_MODE__SHIFT 0x00000018 9849 + #define DATA_FORMAT__ALLOW_REQ_MODE_1_2_MASK 0x10000000L 9850 + #define DATA_FORMAT__ALLOW_REQ_MODE_1_2__SHIFT 0x0000001c 9851 + 9852 + 9853 + // DC_LB_MEMORY_SPLIT 9854 + #define DC_LB_MEMORY_SPLIT__LB_NUM_PARTITIONS_MASK 0x000f0000L 9855 + #define DC_LB_MEMORY_SPLIT__LB_NUM_PARTITIONS__SHIFT 0x00000010 9856 + #define DC_LB_MEMORY_SPLIT__DC_LB_MEMORY_CONFIG_MASK 0x00300000L 9857 + #define DC_LB_MEMORY_SPLIT__DC_LB_MEMORY_CONFIG__SHIFT 0x00000014 9858 + 9859 + // DC_LB_MEM_SIZE 9860 + #define DC_LB_MEM_SIZE__DC_LB_MEM_SIZE_MASK 0x000007ffL 9861 + #define DC_LB_MEM_SIZE__DC_LB_MEM_SIZE__SHIFT 0x00000000 9862 + 9863 + // SCL_TAP_CONTROL 9864 + #define SCL_TAP_CONTROL__SCL_V_NUM_OF_TAPS_MASK 0x00000007L 9865 + #define SCL_TAP_CONTROL__SCL_V_NUM_OF_TAPS__SHIFT 0x00000000 9866 + #define SCL_TAP_CONTROL__SCL_H_NUM_OF_TAPS_MASK 0x00000f00L 9867 + #define SCL_TAP_CONTROL__SCL_H_NUM_OF_TAPS__SHIFT 0x00000008 9868 + 9869 + // INT_MASK 9870 + #define INT_MASK__VBLANK_INT_MASK 0x00000001L 9871 + #define INT_MASK__VBLANK_INT__SHIFT 0x00000000 9872 + #define INT_MASK__VLINE_INT_MASK 0x00000010L 9873 + #define INT_MASK__VLINE_INT__SHIFT 0x00000004 9874 + 9875 + // PRIORITY_A_CNT 9876 + #define PRIORITY_A_CNT__PRIORITY_MARK_A_MASK 0x00007fffL 9877 + #define PRIORITY_A_CNT__PRIORITY_MARK_A__SHIFT 0x00000000 9878 + #define PRIORITY_A_CNT__PRIORITY_A_OFF_MASK 0x00010000L 9879 + #define PRIORITY_A_CNT__PRIORITY_A_OFF__SHIFT 0x00000010 9880 + #define PRIORITY_A_CNT__PRIORITY_A_ALWAYS_ON_MASK 0x00100000L 9881 + #define PRIORITY_A_CNT__PRIORITY_A_ALWAYS_ON__SHIFT 0x00000014 9882 + #define PRIORITY_A_CNT__PRIORITY_A_FORCE_MASK_MASK 0x01000000L 9883 + #define PRIORITY_A_CNT__PRIORITY_A_FORCE_MASK__SHIFT 0x00000018 9884 + 9885 + // PRIORITY_B_CNT 9886 + #define PRIORITY_B_CNT__PRIORITY_MARK_B_MASK 0x00007fffL 9887 + #define PRIORITY_B_CNT__PRIORITY_MARK_B__SHIFT 0x00000000 9888 + #define PRIORITY_B_CNT__PRIORITY_B_OFF_MASK 0x00010000L 9889 + #define PRIORITY_B_CNT__PRIORITY_B_OFF__SHIFT 0x00000010 9890 + #define PRIORITY_B_CNT__PRIORITY_B_ALWAYS_ON_MASK 0x00100000L 9891 + #define PRIORITY_B_CNT__PRIORITY_B_ALWAYS_ON__SHIFT 0x00000014 9892 + #define PRIORITY_B_CNT__PRIORITY_B_FORCE_MASK_MASK 0x01000000L 9893 + #define PRIORITY_B_CNT__PRIORITY_B_FORCE_MASK__SHIFT 0x00000018 9894 + 9895 + // VLINE_STATUS 9896 + #define VLINE_STATUS__VLINE_OCCURRED_MASK 0x00000001L 9897 + #define VLINE_STATUS__VLINE_OCCURRED__SHIFT 0x00000000 9898 + #define VLINE_STATUS__VLINE_ACK_MASK 0x00000010L 9899 + #define VLINE_STATUS__VLINE_ACK__SHIFT 0x00000004 9900 + #define VLINE_STATUS__VLINE_STAT_MASK 0x00001000L 9901 + #define VLINE_STATUS__VLINE_STAT__SHIFT 0x0000000c 9902 + #define VLINE_STATUS__VLINE_INTERRUPT_MASK 0x00010000L 9903 + #define VLINE_STATUS__VLINE_INTERRUPT__SHIFT 0x00000010 9904 + #define VLINE_STATUS__VLINE_INTERRUPT_TYPE_MASK 0x00020000L 9905 + #define VLINE_STATUS__VLINE_INTERRUPT_TYPE__SHIFT 0x00000011 9906 + 9907 + // VBLANK_STATUS 9908 + #define VBLANK_STATUS__VBLANK_OCCURRED_MASK 0x00000001L 9909 + #define VBLANK_STATUS__VBLANK_OCCURRED__SHIFT 0x00000000 9910 + #define VBLANK_STATUS__VBLANK_ACK_MASK 0x00000010L 9911 + #define VBLANK_STATUS__VBLANK_ACK__SHIFT 0x00000004 9912 + #define VBLANK_STATUS__VBLANK_STAT_MASK 0x00001000L 9913 + #define VBLANK_STATUS__VBLANK_STAT__SHIFT 0x0000000c 9914 + #define VBLANK_STATUS__VBLANK_INTERRUPT_MASK 0x00010000L 9915 + #define VBLANK_STATUS__VBLANK_INTERRUPT__SHIFT 0x00000010 9916 + #define VBLANK_STATUS__VBLANK_INTERRUPT_TYPE_MASK 0x00020000L 9917 + #define VBLANK_STATUS__VBLANK_INTERRUPT_TYPE__SHIFT 0x00000011 9918 + 9919 + // SCL_HORZ_FILTER_INIT_RGB_LUMA 9920 + #define SCL_HORZ_FILTER_INIT_RGB_LUMA__SCL_H_INIT_FRAC_RGB_Y_MASK 0x0000ffffL 9921 + #define SCL_HORZ_FILTER_INIT_RGB_LUMA__SCL_H_INIT_FRAC_RGB_Y__SHIFT 0x00000000 9922 + #define SCL_HORZ_FILTER_INIT_RGB_LUMA__SCL_H_INIT_INT_RGB_Y_MASK 0x000f0000L 9923 + #define SCL_HORZ_FILTER_INIT_RGB_LUMA__SCL_H_INIT_INT_RGB_Y__SHIFT 0x00000010 9924 + 9925 + // SCL_HORZ_FILTER_INIT_CHROMA 9926 + #define SCL_HORZ_FILTER_INIT_CHROMA__SCL_H_INIT_FRAC_CBCR_MASK 0x0000ffffL 9927 + #define SCL_HORZ_FILTER_INIT_CHROMA__SCL_H_INIT_FRAC_CBCR__SHIFT 0x00000000 9928 + #define SCL_HORZ_FILTER_INIT_CHROMA__SCL_H_INIT_INT_CBCR_MASK 0x00070000L 9929 + #define SCL_HORZ_FILTER_INIT_CHROMA__SCL_H_INIT_INT_CBCR__SHIFT 0x00000010 9930 + 9847 9931 9848 9932 #endif