drm/amdgpu/si/dpm: fix symbol conflicts with radeon

+147 -140

drivers/gpu/drm/amd/amdgpu/si_dpm.c

··· 2274 2274 smc_table->dpm2Params.SafePowerLimit = 2275 2275 cpu_to_be32(si_scale_power_for_smc((near_tdp_limit * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000); 2276 2276 2277 - ret = si_copy_bytes_to_smc(adev, 2278 - (si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) + 2279 - offsetof(PP_SIslands_DPM2Parameters, TDPLimit)), 2280 - (u8 *)(&(smc_table->dpm2Params.TDPLimit)), 2281 - sizeof(u32) * 3, 2282 - si_pi->sram_end); 2277 + ret = amdgpu_si_copy_bytes_to_smc(adev, 2278 + (si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) + 2279 + offsetof(PP_SIslands_DPM2Parameters, TDPLimit)), 2280 + (u8 *)(&(smc_table->dpm2Params.TDPLimit)), 2281 + sizeof(u32) * 3, 2282 + si_pi->sram_end); 2283 2283 if (ret) 2284 2284 return ret; 2285 2285 ··· 2293 2293 papm_parm->PlatformPowerLimit = 0xffffffff; 2294 2294 papm_parm->NearTDPLimitPAPM = 0xffffffff; 2295 2295 2296 - ret = si_copy_bytes_to_smc(adev, si_pi->papm_cfg_table_start, 2297 - (u8 *)papm_parm, 2298 - sizeof(PP_SIslands_PAPMParameters), 2299 - si_pi->sram_end); 2296 + ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->papm_cfg_table_start, 2297 + (u8 *)papm_parm, 2298 + sizeof(PP_SIslands_PAPMParameters), 2299 + si_pi->sram_end); 2300 2300 if (ret) 2301 2301 return ret; 2302 2302 } ··· 2322 2322 smc_table->dpm2Params.SafePowerLimit = 2323 2323 cpu_to_be32(si_scale_power_for_smc((adev->pm.dpm.near_tdp_limit_adjusted * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000); 2324 2324 2325 - ret = si_copy_bytes_to_smc(adev, 2326 - (si_pi->state_table_start + 2327 - offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) + 2328 - offsetof(PP_SIslands_DPM2Parameters, NearTDPLimit)), 2329 - (u8 *)(&(smc_table->dpm2Params.NearTDPLimit)), 2330 - sizeof(u32) * 2, 2331 - si_pi->sram_end); 2325 + ret = amdgpu_si_copy_bytes_to_smc(adev, 2326 + (si_pi->state_table_start + 2327 + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) + 2328 + offsetof(PP_SIslands_DPM2Parameters, NearTDPLimit)), 2329 + (u8 *)(&(smc_table->dpm2Params.NearTDPLimit)), 2330 + sizeof(u32) * 2, 2331 + si_pi->sram_end); 2332 2332 if (ret) 2333 2333 return ret; 2334 2334 } ··· 2538 2538 if (ni_pi->enable_power_containment) { 2539 2539 if (enable) { 2540 2540 if (!si_should_disable_uvd_powertune(adev, amdgpu_new_state)) { 2541 - smc_result = si_send_msg_to_smc(adev, PPSMC_TDPClampingActive); 2541 + smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_TDPClampingActive); 2542 2542 if (smc_result != PPSMC_Result_OK) { 2543 2543 ret = -EINVAL; 2544 2544 ni_pi->pc_enabled = false; ··· 2547 2547 } 2548 2548 } 2549 2549 } else { 2550 - smc_result = si_send_msg_to_smc(adev, PPSMC_TDPClampingInactive); 2550 + smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_TDPClampingInactive); 2551 2551 if (smc_result != PPSMC_Result_OK) 2552 2552 ret = -EINVAL; 2553 2553 ni_pi->pc_enabled = false; ··· 2615 2615 dte_tables->Tdep_R[i] = cpu_to_be32(dte_data->tdep_r[i]); 2616 2616 } 2617 2617 2618 - ret = si_copy_bytes_to_smc(adev, si_pi->dte_table_start, (u8 *)dte_tables, 2619 - sizeof(Smc_SIslands_DTE_Configuration), si_pi->sram_end); 2618 + ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->dte_table_start, 2619 + (u8 *)dte_tables, 2620 + sizeof(Smc_SIslands_DTE_Configuration), 2621 + si_pi->sram_end); 2620 2622 kfree(dte_tables); 2621 2623 2622 2624 return ret; ··· 2808 2806 cac_tables->lkge_lut_T0 = cpu_to_be32((u32)t0); 2809 2807 cac_tables->lkge_lut_Tstep = cpu_to_be32((u32)t_step); 2810 2808 2811 - ret = si_copy_bytes_to_smc(adev, si_pi->cac_table_start, (u8 *)cac_tables, 2812 - sizeof(PP_SIslands_CacConfig), si_pi->sram_end); 2809 + ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->cac_table_start, 2810 + (u8 *)cac_tables, 2811 + sizeof(PP_SIslands_CacConfig), 2812 + si_pi->sram_end); 2813 2813 2814 2814 if (ret) 2815 2815 goto done_free; ··· 2904 2900 if (enable) { 2905 2901 if (!si_should_disable_uvd_powertune(adev, amdgpu_new_state)) { 2906 2902 if (ni_pi->support_cac_long_term_average) { 2907 - smc_result = si_send_msg_to_smc(adev, PPSMC_CACLongTermAvgEnable); 2903 + smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_CACLongTermAvgEnable); 2908 2904 if (smc_result != PPSMC_Result_OK) 2909 2905 ni_pi->support_cac_long_term_average = false; 2910 2906 } 2911 2907 2912 - smc_result = si_send_msg_to_smc(adev, PPSMC_MSG_EnableCac); 2908 + smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableCac); 2913 2909 if (smc_result != PPSMC_Result_OK) { 2914 2910 ret = -EINVAL; 2915 2911 ni_pi->cac_enabled = false; ··· 2918 2914 } 2919 2915 2920 2916 if (si_pi->enable_dte) { 2921 - smc_result = si_send_msg_to_smc(adev, PPSMC_MSG_EnableDTE); 2917 + smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableDTE); 2922 2918 if (smc_result != PPSMC_Result_OK) 2923 2919 ret = -EINVAL; 2924 2920 } 2925 2921 } 2926 2922 } else if (ni_pi->cac_enabled) { 2927 2923 if (si_pi->enable_dte) 2928 - smc_result = si_send_msg_to_smc(adev, PPSMC_MSG_DisableDTE); 2924 + smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_DisableDTE); 2929 2925 2930 - smc_result = si_send_msg_to_smc(adev, PPSMC_MSG_DisableCac); 2926 + smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_DisableCac); 2931 2927 2932 2928 ni_pi->cac_enabled = false; 2933 2929 2934 2930 if (ni_pi->support_cac_long_term_average) 2935 - smc_result = si_send_msg_to_smc(adev, PPSMC_CACLongTermAvgDisable); 2931 + smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_CACLongTermAvgDisable); 2936 2932 } 2937 2933 } 2938 2934 return ret; ··· 2996 2992 2997 2993 2998 2994 if (!ret) 2999 - ret = si_copy_bytes_to_smc(adev, si_pi->spll_table_start, 3000 - (u8 *)spll_table, sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), 3001 - si_pi->sram_end); 2995 + ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->spll_table_start, 2996 + (u8 *)spll_table, 2997 + sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), 2998 + si_pi->sram_end); 3002 2999 3003 3000 if (ret) 3004 3001 ni_pi->enable_power_containment = false; ··· 3669 3664 { 3670 3665 struct si_power_info *si_pi = si_get_pi(adev); 3671 3666 3672 - return si_read_smc_sram_dword(adev, 3673 - si_pi->soft_regs_start + reg_offset, value, 3674 - si_pi->sram_end); 3667 + return amdgpu_si_read_smc_sram_dword(adev, 3668 + si_pi->soft_regs_start + reg_offset, value, 3669 + si_pi->sram_end); 3675 3670 } 3676 3671 #endif 3677 3672 ··· 3680 3675 { 3681 3676 struct si_power_info *si_pi = si_get_pi(adev); 3682 3677 3683 - return si_write_smc_sram_dword(adev, 3684 - si_pi->soft_regs_start + reg_offset, 3685 - value, si_pi->sram_end); 3678 + return amdgpu_si_write_smc_sram_dword(adev, 3679 + si_pi->soft_regs_start + reg_offset, 3680 + value, si_pi->sram_end); 3686 3681 } 3687 3682 3688 3683 static bool si_is_special_1gb_platform(struct amdgpu_device *adev) ··· 3839 3834 PPSMC_Result ret; 3840 3835 3841 3836 if (thermal_level == 0) { 3842 - ret = si_send_msg_to_smc(adev, PPSMC_MSG_EnableThermalInterrupt); 3837 + ret = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableThermalInterrupt); 3843 3838 if (ret == PPSMC_Result_OK) 3844 3839 return 0; 3845 3840 else ··· 3858 3853 static int si_notify_hw_of_powersource(struct amdgpu_device *adev, bool ac_power) 3859 3854 { 3860 3855 if (ac_power) 3861 - return (si_send_msg_to_smc(adev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ? 3856 + return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ? 3862 3857 0 : -EINVAL; 3863 3858 3864 3859 return 0; ··· 3869 3864 PPSMC_Msg msg, u32 parameter) 3870 3865 { 3871 3866 WREG32(SMC_SCRATCH0, parameter); 3872 - return si_send_msg_to_smc(adev, msg); 3867 + return amdgpu_si_send_msg_to_smc(adev, msg); 3873 3868 } 3874 3869 3875 3870 static int si_restrict_performance_levels_before_switch(struct amdgpu_device *adev) 3876 3871 { 3877 - if (si_send_msg_to_smc(adev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK) 3872 + if (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK) 3878 3873 return -EINVAL; 3879 3874 3880 3875 return (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK) ? ··· 3916 3911 #if 0 3917 3912 static int si_set_boot_state(struct amdgpu_device *adev) 3918 3913 { 3919 - return (si_send_msg_to_smc(adev, PPSMC_MSG_SwitchToInitialState) == PPSMC_Result_OK) ? 3914 + return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_SwitchToInitialState) == PPSMC_Result_OK) ? 3920 3915 0 : -EINVAL; 3921 3916 } 3922 3917 #endif 3923 3918 3924 3919 static int si_set_sw_state(struct amdgpu_device *adev) 3925 3920 { 3926 - return (si_send_msg_to_smc(adev, PPSMC_MSG_SwitchToSwState) == PPSMC_Result_OK) ? 3921 + return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_SwitchToSwState) == PPSMC_Result_OK) ? 3927 3922 0 : -EINVAL; 3928 3923 } 3929 3924 3930 3925 static int si_halt_smc(struct amdgpu_device *adev) 3931 3926 { 3932 - if (si_send_msg_to_smc(adev, PPSMC_MSG_Halt) != PPSMC_Result_OK) 3927 + if (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_Halt) != PPSMC_Result_OK) 3933 3928 return -EINVAL; 3934 3929 3935 - return (si_wait_for_smc_inactive(adev) == PPSMC_Result_OK) ? 3930 + return (amdgpu_si_wait_for_smc_inactive(adev) == PPSMC_Result_OK) ? 3936 3931 0 : -EINVAL; 3937 3932 } 3938 3933 3939 3934 static int si_resume_smc(struct amdgpu_device *adev) 3940 3935 { 3941 - if (si_send_msg_to_smc(adev, PPSMC_FlushDataCache) != PPSMC_Result_OK) 3936 + if (amdgpu_si_send_msg_to_smc(adev, PPSMC_FlushDataCache) != PPSMC_Result_OK) 3942 3937 return -EINVAL; 3943 3938 3944 - return (si_send_msg_to_smc(adev, PPSMC_MSG_Resume) == PPSMC_Result_OK) ? 3939 + return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_Resume) == PPSMC_Result_OK) ? 3945 3940 0 : -EINVAL; 3946 3941 } 3947 3942 3948 3943 static void si_dpm_start_smc(struct amdgpu_device *adev) 3949 3944 { 3950 - si_program_jump_on_start(adev); 3951 - si_start_smc(adev); 3952 - si_smc_clock(adev, true); 3945 + amdgpu_si_program_jump_on_start(adev); 3946 + amdgpu_si_start_smc(adev); 3947 + amdgpu_si_smc_clock(adev, true); 3953 3948 } 3954 3949 3955 3950 static void si_dpm_stop_smc(struct amdgpu_device *adev) 3956 3951 { 3957 - si_reset_smc(adev); 3958 - si_smc_clock(adev, false); 3952 + amdgpu_si_reset_smc(adev); 3953 + amdgpu_si_smc_clock(adev, false); 3959 3954 } 3960 3955 3961 3956 static int si_process_firmware_header(struct amdgpu_device *adev) ··· 3964 3959 u32 tmp; 3965 3960 int ret; 3966 3961 3967 - ret = si_read_smc_sram_dword(adev, 3968 - SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3969 - SISLANDS_SMC_FIRMWARE_HEADER_stateTable, 3970 - &tmp, si_pi->sram_end); 3962 + ret = amdgpu_si_read_smc_sram_dword(adev, 3963 + SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3964 + SISLANDS_SMC_FIRMWARE_HEADER_stateTable, 3965 + &tmp, si_pi->sram_end); 3971 3966 if (ret) 3972 3967 return ret; 3973 3968 3974 3969 si_pi->state_table_start = tmp; 3975 3970 3976 - ret = si_read_smc_sram_dword(adev, 3977 - SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3978 - SISLANDS_SMC_FIRMWARE_HEADER_softRegisters, 3979 - &tmp, si_pi->sram_end); 3971 + ret = amdgpu_si_read_smc_sram_dword(adev, 3972 + SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3973 + SISLANDS_SMC_FIRMWARE_HEADER_softRegisters, 3974 + &tmp, si_pi->sram_end); 3980 3975 if (ret) 3981 3976 return ret; 3982 3977 3983 3978 si_pi->soft_regs_start = tmp; 3984 3979 3985 - ret = si_read_smc_sram_dword(adev, 3986 - SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3987 - SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable, 3988 - &tmp, si_pi->sram_end); 3980 + ret = amdgpu_si_read_smc_sram_dword(adev, 3981 + SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3982 + SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable, 3983 + &tmp, si_pi->sram_end); 3989 3984 if (ret) 3990 3985 return ret; 3991 3986 3992 3987 si_pi->mc_reg_table_start = tmp; 3993 3988 3994 - ret = si_read_smc_sram_dword(adev, 3995 - SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3996 - SISLANDS_SMC_FIRMWARE_HEADER_fanTable, 3997 - &tmp, si_pi->sram_end); 3989 + ret = amdgpu_si_read_smc_sram_dword(adev, 3990 + SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3991 + SISLANDS_SMC_FIRMWARE_HEADER_fanTable, 3992 + &tmp, si_pi->sram_end); 3998 3993 if (ret) 3999 3994 return ret; 4000 3995 4001 3996 si_pi->fan_table_start = tmp; 4002 3997 4003 - ret = si_read_smc_sram_dword(adev, 4004 - SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 4005 - SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable, 4006 - &tmp, si_pi->sram_end); 3998 + ret = amdgpu_si_read_smc_sram_dword(adev, 3999 + SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 4000 + SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable, 4001 + &tmp, si_pi->sram_end); 4007 4002 if (ret) 4008 4003 return ret; 4009 4004 4010 4005 si_pi->arb_table_start = tmp; 4011 4006 4012 - ret = si_read_smc_sram_dword(adev, 4013 - SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 4014 - SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable, 4015 - &tmp, si_pi->sram_end); 4007 + ret = amdgpu_si_read_smc_sram_dword(adev, 4008 + SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 4009 + SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable, 4010 + &tmp, si_pi->sram_end); 4016 4011 if (ret) 4017 4012 return ret; 4018 4013 4019 4014 si_pi->cac_table_start = tmp; 4020 4015 4021 - ret = si_read_smc_sram_dword(adev, 4022 - SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 4023 - SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration, 4024 - &tmp, si_pi->sram_end); 4016 + ret = amdgpu_si_read_smc_sram_dword(adev, 4017 + SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 4018 + SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration, 4019 + &tmp, si_pi->sram_end); 4025 4020 if (ret) 4026 4021 return ret; 4027 4022 4028 4023 si_pi->dte_table_start = tmp; 4029 4024 4030 - ret = si_read_smc_sram_dword(adev, 4031 - SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 4032 - SISLANDS_SMC_FIRMWARE_HEADER_spllTable, 4033 - &tmp, si_pi->sram_end); 4025 + ret = amdgpu_si_read_smc_sram_dword(adev, 4026 + SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 4027 + SISLANDS_SMC_FIRMWARE_HEADER_spllTable, 4028 + &tmp, si_pi->sram_end); 4034 4029 if (ret) 4035 4030 return ret; 4036 4031 4037 4032 si_pi->spll_table_start = tmp; 4038 4033 4039 - ret = si_read_smc_sram_dword(adev, 4040 - SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 4041 - SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters, 4042 - &tmp, si_pi->sram_end); 4034 + ret = amdgpu_si_read_smc_sram_dword(adev, 4035 + SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 4036 + SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters, 4037 + &tmp, si_pi->sram_end); 4043 4038 if (ret) 4044 4039 return ret; 4045 4040 ··· 4117 4112 PPSMC_Msg msg = has_display ? 4118 4113 PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay; 4119 4114 4120 - return (si_send_msg_to_smc(adev, msg) == PPSMC_Result_OK) ? 4115 + return (amdgpu_si_send_msg_to_smc(adev, msg) == PPSMC_Result_OK) ? 4121 4116 0 : -EINVAL; 4122 4117 } 4123 4118 ··· 4370 4365 { 4371 4366 struct si_power_info *si_pi = si_get_pi(adev); 4372 4367 4373 - si_reset_smc(adev); 4374 - si_smc_clock(adev, false); 4368 + amdgpu_si_reset_smc(adev); 4369 + amdgpu_si_smc_clock(adev, false); 4375 4370 4376 - return si_load_smc_ucode(adev, si_pi->sram_end); 4371 + return amdgpu_si_load_smc_ucode(adev, si_pi->sram_end); 4377 4372 } 4378 4373 4379 4374 static bool si_validate_phase_shedding_tables(struct amdgpu_device *adev, ··· 4717 4712 u32 tmp; 4718 4713 int ret; 4719 4714 4720 - ret = si_read_smc_sram_dword(adev, si_pi->arb_table_start, &tmp, si_pi->sram_end); 4715 + ret = amdgpu_si_read_smc_sram_dword(adev, si_pi->arb_table_start, 4716 + &tmp, si_pi->sram_end); 4721 4717 if (ret) 4722 4718 return ret; 4723 4719 4724 4720 tmp &= 0x00FFFFFF; 4725 4721 tmp |= MC_CG_ARB_FREQ_F1 << 24; 4726 4722 4727 - return si_write_smc_sram_dword(adev, si_pi->arb_table_start, tmp, si_pi->sram_end); 4723 + return amdgpu_si_write_smc_sram_dword(adev, si_pi->arb_table_start, 4724 + tmp, si_pi->sram_end); 4728 4725 } 4729 4726 4730 4727 static int si_initial_switch_from_arb_f0_to_f1(struct amdgpu_device *adev) ··· 4736 4729 4737 4730 static int si_reset_to_default(struct amdgpu_device *adev) 4738 4731 { 4739 - return (si_send_msg_to_smc(adev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ? 4732 + return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ? 4740 4733 0 : -EINVAL; 4741 4734 } 4742 4735 ··· 4746 4739 u32 tmp; 4747 4740 int ret; 4748 4741 4749 - ret = si_read_smc_sram_dword(adev, si_pi->arb_table_start, 4750 - &tmp, si_pi->sram_end); 4742 + ret = amdgpu_si_read_smc_sram_dword(adev, si_pi->arb_table_start, 4743 + &tmp, si_pi->sram_end); 4751 4744 if (ret) 4752 4745 return ret; 4753 4746 ··· 4817 4810 ret = si_populate_memory_timing_parameters(adev, &state->performance_levels[i], &arb_regs); 4818 4811 if (ret) 4819 4812 break; 4820 - ret = si_copy_bytes_to_smc(adev, 4821 - si_pi->arb_table_start + 4822 - offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) + 4823 - sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * (first_arb_set + i), 4824 - (u8 *)&arb_regs, 4825 - sizeof(SMC_SIslands_MCArbDramTimingRegisterSet), 4826 - si_pi->sram_end); 4813 + ret = amdgpu_si_copy_bytes_to_smc(adev, 4814 + si_pi->arb_table_start + 4815 + offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) + 4816 + sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * (first_arb_set + i), 4817 + (u8 *)&arb_regs, 4818 + sizeof(SMC_SIslands_MCArbDramTimingRegisterSet), 4819 + si_pi->sram_end); 4827 4820 if (ret) 4828 4821 break; 4829 4822 } ··· 5159 5152 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_ulv_volt_change_delay, 5160 5153 ulv->volt_change_delay); 5161 5154 5162 - ret = si_copy_bytes_to_smc(adev, 5163 - si_pi->arb_table_start + 5164 - offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) + 5165 - sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * SISLANDS_ULV_STATE_ARB_INDEX, 5166 - (u8 *)&arb_regs, 5167 - sizeof(SMC_SIslands_MCArbDramTimingRegisterSet), 5168 - si_pi->sram_end); 5155 + ret = amdgpu_si_copy_bytes_to_smc(adev, 5156 + si_pi->arb_table_start + 5157 + offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) + 5158 + sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * SISLANDS_ULV_STATE_ARB_INDEX, 5159 + (u8 *)&arb_regs, 5160 + sizeof(SMC_SIslands_MCArbDramTimingRegisterSet), 5161 + si_pi->sram_end); 5169 5162 5170 5163 return ret; 5171 5164 } ··· 5259 5252 table->ULVState = table->initialState; 5260 5253 } 5261 5254 5262 - return si_copy_bytes_to_smc(adev, si_pi->state_table_start, 5263 - (u8 *)table, sizeof(SISLANDS_SMC_STATETABLE), 5264 - si_pi->sram_end); 5255 + return amdgpu_si_copy_bytes_to_smc(adev, si_pi->state_table_start, 5256 + (u8 *)table, sizeof(SISLANDS_SMC_STATETABLE), 5257 + si_pi->sram_end); 5265 5258 } 5266 5259 5267 5260 static int si_calculate_sclk_params(struct amdgpu_device *adev, ··· 5623 5616 struct si_ulv_param *ulv = &si_pi->ulv; 5624 5617 5625 5618 if (ulv->supported) 5626 - return (si_send_msg_to_smc(adev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ? 5619 + return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ? 5627 5620 0 : -EINVAL; 5628 5621 5629 5622 return 0; ··· 5665 5658 5666 5659 if (ulv->supported) { 5667 5660 if (si_is_state_ulv_compatible(adev, amdgpu_new_state)) 5668 - return (si_send_msg_to_smc(adev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ? 5661 + return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ? 5669 5662 0 : -EINVAL; 5670 5663 } 5671 5664 return 0; ··· 5770 5763 if (ret) 5771 5764 return ret; 5772 5765 5773 - return si_copy_bytes_to_smc(adev, address, (u8 *)smc_state, 5774 - state_size, si_pi->sram_end); 5766 + return amdgpu_si_copy_bytes_to_smc(adev, address, (u8 *)smc_state, 5767 + state_size, si_pi->sram_end); 5775 5768 } 5776 5769 5777 5770 static int si_upload_ulv_state(struct amdgpu_device *adev) ··· 5790 5783 5791 5784 ret = si_populate_ulv_state(adev, smc_state); 5792 5785 if (!ret) 5793 - ret = si_copy_bytes_to_smc(adev, address, (u8 *)smc_state, 5794 - state_size, si_pi->sram_end); 5786 + ret = amdgpu_si_copy_bytes_to_smc(adev, address, (u8 *)smc_state, 5787 + state_size, si_pi->sram_end); 5795 5788 } 5796 5789 5797 5790 return ret; ··· 6162 6155 6163 6156 si_convert_mc_reg_table_to_smc(adev, amdgpu_boot_state, smc_mc_reg_table); 6164 6157 6165 - return si_copy_bytes_to_smc(adev, si_pi->mc_reg_table_start, 6166 - (u8 *)smc_mc_reg_table, 6167 - sizeof(SMC_SIslands_MCRegisters), si_pi->sram_end); 6158 + return amdgpu_si_copy_bytes_to_smc(adev, si_pi->mc_reg_table_start, 6159 + (u8 *)smc_mc_reg_table, 6160 + sizeof(SMC_SIslands_MCRegisters), si_pi->sram_end); 6168 6161 } 6169 6162 6170 6163 static int si_upload_mc_reg_table(struct amdgpu_device *adev, ··· 6181 6174 6182 6175 si_convert_mc_reg_table_to_smc(adev, amdgpu_new_state, smc_mc_reg_table); 6183 6176 6184 - return si_copy_bytes_to_smc(adev, address, 6185 - (u8 *)&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT], 6186 - sizeof(SMC_SIslands_MCRegisterSet) * new_state->performance_level_count, 6187 - si_pi->sram_end); 6177 + return amdgpu_si_copy_bytes_to_smc(adev, address, 6178 + (u8 *)&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT], 6179 + sizeof(SMC_SIslands_MCRegisterSet) * new_state->performance_level_count, 6180 + si_pi->sram_end); 6188 6181 } 6189 6182 6190 6183 static void si_enable_voltage_control(struct amdgpu_device *adev, bool enable) ··· 6292 6285 6293 6286 if (eg_pi->sclk_deep_sleep) { 6294 6287 if (ds_status_on) 6295 - return (si_send_msg_to_smc(adev, PPSMC_MSG_CancelThrottleOVRDSCLKDS) == 6288 + return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_CancelThrottleOVRDSCLKDS) == 6296 6289 PPSMC_Result_OK) ? 6297 6290 0 : -EINVAL; 6298 6291 else 6299 - return (si_send_msg_to_smc(adev, PPSMC_MSG_ThrottleOVRDSCLKDS) == 6292 + return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_ThrottleOVRDSCLKDS) == 6300 6293 PPSMC_Result_OK) ? 0 : -EINVAL; 6301 6294 } 6302 6295 return 0; ··· 6427 6420 6428 6421 thermal_int &= ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW); 6429 6422 WREG32(CG_THERMAL_INT, thermal_int); 6430 - result = si_send_msg_to_smc(adev, PPSMC_MSG_EnableThermalInterrupt); 6423 + result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableThermalInterrupt); 6431 6424 if (result != PPSMC_Result_OK) { 6432 6425 DRM_DEBUG_KMS("Could not enable thermal interrupts.\n"); 6433 6426 return -EINVAL; ··· 6542 6535 tmp = (RREG32(CG_MULT_THERMAL_CTRL) & TEMP_SEL_MASK) >> TEMP_SEL_SHIFT; 6543 6536 fan_table.temp_src = (uint8_t)tmp; 6544 6537 6545 - ret = si_copy_bytes_to_smc(adev, 6546 - si_pi->fan_table_start, 6547 - (u8 *)(&fan_table), 6548 - sizeof(fan_table), 6549 - si_pi->sram_end); 6538 + ret = amdgpu_si_copy_bytes_to_smc(adev, 6539 + si_pi->fan_table_start, 6540 + (u8 *)(&fan_table), 6541 + sizeof(fan_table), 6542 + si_pi->sram_end); 6550 6543 6551 6544 if (ret) { 6552 6545 DRM_ERROR("Failed to load fan table to the SMC."); ··· 6561 6554 struct si_power_info *si_pi = si_get_pi(adev); 6562 6555 PPSMC_Result ret; 6563 6556 6564 - ret = si_send_msg_to_smc(adev, PPSMC_StartFanControl); 6557 + ret = amdgpu_si_send_msg_to_smc(adev, PPSMC_StartFanControl); 6565 6558 if (ret == PPSMC_Result_OK) { 6566 6559 si_pi->fan_is_controlled_by_smc = true; 6567 6560 return 0; ··· 6575 6568 struct si_power_info *si_pi = si_get_pi(adev); 6576 6569 PPSMC_Result ret; 6577 6570 6578 - ret = si_send_msg_to_smc(adev, PPSMC_StopFanControl); 6571 + ret = amdgpu_si_send_msg_to_smc(adev, PPSMC_StopFanControl); 6579 6572 6580 6573 if (ret == PPSMC_Result_OK) { 6581 6574 si_pi->fan_is_controlled_by_smc = false; ··· 6806 6799 struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps; 6807 6800 int ret; 6808 6801 6809 - if (si_is_smc_running(adev)) 6802 + if (amdgpu_si_is_smc_running(adev)) 6810 6803 return -EINVAL; 6811 6804 if (pi->voltage_control || si_pi->voltage_control_svi2) 6812 6805 si_enable_voltage_control(adev, true); ··· 6937 6930 struct rv7xx_power_info *pi = rv770_get_pi(adev); 6938 6931 struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps; 6939 6932 6940 - if (!si_is_smc_running(adev)) 6933 + if (!amdgpu_si_is_smc_running(adev)) 6941 6934 return; 6942 6935 si_thermal_stop_thermal_controller(adev); 6943 6936 si_disable_ulv(adev);

+19 -18

drivers/gpu/drm/amd/amdgpu/si_smc.c

··· 44 44 return 0; 45 45 } 46 46 47 - int si_copy_bytes_to_smc(struct amdgpu_device *adev, 48 - u32 smc_start_address, 49 - const u8 *src, u32 byte_count, u32 limit) 47 + int amdgpu_si_copy_bytes_to_smc(struct amdgpu_device *adev, 48 + u32 smc_start_address, 49 + const u8 *src, u32 byte_count, u32 limit) 50 50 { 51 51 unsigned long flags; 52 52 int ret = 0; ··· 108 108 return ret; 109 109 } 110 110 111 - void si_start_smc(struct amdgpu_device *adev) 111 + void amdgpu_si_start_smc(struct amdgpu_device *adev) 112 112 { 113 113 u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL); 114 114 ··· 117 117 WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp); 118 118 } 119 119 120 - void si_reset_smc(struct amdgpu_device *adev) 120 + void amdgpu_si_reset_smc(struct amdgpu_device *adev) 121 121 { 122 122 u32 tmp; 123 123 ··· 131 131 WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp); 132 132 } 133 133 134 - int si_program_jump_on_start(struct amdgpu_device *adev) 134 + int amdgpu_si_program_jump_on_start(struct amdgpu_device *adev) 135 135 { 136 136 static const u8 data[] = { 0x0E, 0x00, 0x40, 0x40 }; 137 137 138 - return si_copy_bytes_to_smc(adev, 0x0, data, 4, sizeof(data)+1); 138 + return amdgpu_si_copy_bytes_to_smc(adev, 0x0, data, 4, sizeof(data)+1); 139 139 } 140 140 141 - void si_smc_clock(struct amdgpu_device *adev, bool enable) 141 + void amdgpu_si_smc_clock(struct amdgpu_device *adev, bool enable) 142 142 { 143 143 u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0); 144 144 ··· 150 150 WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp); 151 151 } 152 152 153 - bool si_is_smc_running(struct amdgpu_device *adev) 153 + bool amdgpu_si_is_smc_running(struct amdgpu_device *adev) 154 154 { 155 155 u32 rst = RREG32_SMC(SMC_SYSCON_RESET_CNTL); 156 156 u32 clk = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0); ··· 161 161 return false; 162 162 } 163 163 164 - PPSMC_Result si_send_msg_to_smc(struct amdgpu_device *adev, PPSMC_Msg msg) 164 + PPSMC_Result amdgpu_si_send_msg_to_smc(struct amdgpu_device *adev, 165 + PPSMC_Msg msg) 165 166 { 166 167 u32 tmp; 167 168 int i; 168 169 169 - if (!si_is_smc_running(adev)) 170 + if (!amdgpu_si_is_smc_running(adev)) 170 171 return PPSMC_Result_Failed; 171 172 172 173 WREG32(SMC_MESSAGE_0, msg); ··· 182 181 return (PPSMC_Result)RREG32(SMC_RESP_0); 183 182 } 184 183 185 - PPSMC_Result si_wait_for_smc_inactive(struct amdgpu_device *adev) 184 + PPSMC_Result amdgpu_si_wait_for_smc_inactive(struct amdgpu_device *adev) 186 185 { 187 186 u32 tmp; 188 187 int i; 189 188 190 - if (!si_is_smc_running(adev)) 189 + if (!amdgpu_si_is_smc_running(adev)) 191 190 return PPSMC_Result_OK; 192 191 193 192 for (i = 0; i < adev->usec_timeout; i++) { ··· 200 199 return PPSMC_Result_OK; 201 200 } 202 201 203 - int si_load_smc_ucode(struct amdgpu_device *adev, u32 limit) 202 + int amdgpu_si_load_smc_ucode(struct amdgpu_device *adev, u32 limit) 204 203 { 205 204 const struct smc_firmware_header_v1_0 *hdr; 206 205 unsigned long flags; ··· 242 241 return 0; 243 242 } 244 243 245 - int si_read_smc_sram_dword(struct amdgpu_device *adev, u32 smc_address, 246 - u32 *value, u32 limit) 244 + int amdgpu_si_read_smc_sram_dword(struct amdgpu_device *adev, u32 smc_address, 245 + u32 *value, u32 limit) 247 246 { 248 247 unsigned long flags; 249 248 int ret; ··· 257 256 return ret; 258 257 } 259 258 260 - int si_write_smc_sram_dword(struct amdgpu_device *adev, u32 smc_address, 261 - u32 value, u32 limit) 259 + int amdgpu_si_write_smc_sram_dword(struct amdgpu_device *adev, u32 smc_address, 260 + u32 value, u32 limit) 262 261 { 263 262 unsigned long flags; 264 263 int ret;

+15 -15

drivers/gpu/drm/amd/amdgpu/sislands_smc.h

··· 402 402 403 403 #pragma pack(pop) 404 404 405 - int si_copy_bytes_to_smc(struct amdgpu_device *adev, 406 - u32 smc_start_address, 407 - const u8 *src, u32 byte_count, u32 limit); 408 - void si_start_smc(struct amdgpu_device *adev); 409 - void si_reset_smc(struct amdgpu_device *adev); 410 - int si_program_jump_on_start(struct amdgpu_device *adev); 411 - void si_smc_clock(struct amdgpu_device *adev, bool enable); 412 - bool si_is_smc_running(struct amdgpu_device *adev); 413 - PPSMC_Result si_send_msg_to_smc(struct amdgpu_device *adev, PPSMC_Msg msg); 414 - PPSMC_Result si_wait_for_smc_inactive(struct amdgpu_device *adev); 415 - int si_load_smc_ucode(struct amdgpu_device *adev, u32 limit); 416 - int si_read_smc_sram_dword(struct amdgpu_device *adev, u32 smc_address, 417 - u32 *value, u32 limit); 418 - int si_write_smc_sram_dword(struct amdgpu_device *adev, u32 smc_address, 419 - u32 value, u32 limit); 405 + int amdgpu_si_copy_bytes_to_smc(struct amdgpu_device *adev, 406 + u32 smc_start_address, 407 + const u8 *src, u32 byte_count, u32 limit); 408 + void amdgpu_si_start_smc(struct amdgpu_device *adev); 409 + void amdgpu_si_reset_smc(struct amdgpu_device *adev); 410 + int amdgpu_si_program_jump_on_start(struct amdgpu_device *adev); 411 + void amdgpu_si_smc_clock(struct amdgpu_device *adev, bool enable); 412 + bool amdgpu_si_is_smc_running(struct amdgpu_device *adev); 413 + PPSMC_Result amdgpu_si_send_msg_to_smc(struct amdgpu_device *adev, PPSMC_Msg msg); 414 + PPSMC_Result amdgpu_si_wait_for_smc_inactive(struct amdgpu_device *adev); 415 + int amdgpu_si_load_smc_ucode(struct amdgpu_device *adev, u32 limit); 416 + int amdgpu_si_read_smc_sram_dword(struct amdgpu_device *adev, u32 smc_address, 417 + u32 *value, u32 limit); 418 + int amdgpu_si_write_smc_sram_dword(struct amdgpu_device *adev, u32 smc_address, 419 + u32 value, u32 limit); 420 420 421 421 #endif 422 422