Merge branch 'release' of git://git.kernel.org/pub/scm/linux/kernel/git/lenb/linux

+37

arch/x86/include/uapi/asm/msr-index.h

··· 35 35 #define MSR_IA32_PERFCTR0 0x000000c1 36 36 #define MSR_IA32_PERFCTR1 0x000000c2 37 37 #define MSR_FSB_FREQ 0x000000cd 38 + #define MSR_NHM_PLATFORM_INFO 0x000000ce 38 39 39 40 #define MSR_NHM_SNB_PKG_CST_CFG_CTL 0x000000e2 40 41 #define NHM_C3_AUTO_DEMOTE (1UL << 25) 41 42 #define NHM_C1_AUTO_DEMOTE (1UL << 26) 42 43 #define ATM_LNC_C6_AUTO_DEMOTE (1UL << 25) 44 + #define SNB_C1_AUTO_UNDEMOTE (1UL << 27) 45 + #define SNB_C3_AUTO_UNDEMOTE (1UL << 28) 43 46 44 47 #define MSR_MTRRcap 0x000000fe 45 48 #define MSR_IA32_BBL_CR_CTL 0x00000119 ··· 58 55 59 56 #define MSR_OFFCORE_RSP_0 0x000001a6 60 57 #define MSR_OFFCORE_RSP_1 0x000001a7 58 + #define MSR_NHM_TURBO_RATIO_LIMIT 0x000001ad 59 + #define MSR_IVT_TURBO_RATIO_LIMIT 0x000001ae 61 60 62 61 #define MSR_LBR_SELECT 0x000001c8 63 62 #define MSR_LBR_TOS 0x000001c9 ··· 107 102 #define MSR_IA32_MC0_STATUS 0x00000401 108 103 #define MSR_IA32_MC0_ADDR 0x00000402 109 104 #define MSR_IA32_MC0_MISC 0x00000403 105 + 106 + /* C-state Residency Counters */ 107 + #define MSR_PKG_C3_RESIDENCY 0x000003f8 108 + #define MSR_PKG_C6_RESIDENCY 0x000003f9 109 + #define MSR_PKG_C7_RESIDENCY 0x000003fa 110 + #define MSR_CORE_C3_RESIDENCY 0x000003fc 111 + #define MSR_CORE_C6_RESIDENCY 0x000003fd 112 + #define MSR_CORE_C7_RESIDENCY 0x000003fe 113 + #define MSR_PKG_C2_RESIDENCY 0x0000060d 114 + 115 + /* Run Time Average Power Limiting (RAPL) Interface */ 116 + 117 + #define MSR_RAPL_POWER_UNIT 0x00000606 118 + 119 + #define MSR_PKG_POWER_LIMIT 0x00000610 120 + #define MSR_PKG_ENERGY_STATUS 0x00000611 121 + #define MSR_PKG_PERF_STATUS 0x00000613 122 + #define MSR_PKG_POWER_INFO 0x00000614 123 + 124 + #define MSR_DRAM_POWER_LIMIT 0x00000618 125 + #define MSR_DRAM_ENERGY_STATUS 0x00000619 126 + #define MSR_DRAM_PERF_STATUS 0x0000061b 127 + #define MSR_DRAM_POWER_INFO 0x0000061c 128 + 129 + #define MSR_PP0_POWER_LIMIT 0x00000638 130 + #define MSR_PP0_ENERGY_STATUS 0x00000639 131 + #define MSR_PP0_POLICY 0x0000063a 132 + #define MSR_PP0_PERF_STATUS 0x0000063b 133 + 134 + #define MSR_PP1_POWER_LIMIT 0x00000640 135 + #define MSR_PP1_ENERGY_STATUS 0x00000641 136 + #define MSR_PP1_POLICY 0x00000642 110 137 111 138 #define MSR_AMD64_MC0_MASK 0xc0010044 112 139

+17 -4

tools/power/x86/turbostat/Makefile

··· 1 + CC = $(CROSS_COMPILE)gcc 2 + BUILD_OUTPUT := $(PWD) 3 + PREFIX := /usr 4 + DESTDIR := 5 + 1 6 turbostat : turbostat.c 2 7 CFLAGS += -Wall 8 + CFLAGS += -I../../../../arch/x86/include/uapi/ 3 9 10 + %: %.c 11 + @mkdir -p $(BUILD_OUTPUT) 12 + $(CC) $(CFLAGS) $< -o $(BUILD_OUTPUT)/$@ 13 + 14 + .PHONY : clean 4 15 clean : 5 - rm -f turbostat 16 + @rm -f $(BUILD_OUTPUT)/turbostat 6 17 7 - install : 8 - install turbostat /usr/bin/turbostat 9 - install turbostat.8 /usr/share/man/man8 18 + install : turbostat 19 + install -d $(DESTDIR)$(PREFIX)/bin 20 + install $(BUILD_OUTPUT)/turbostat $(DESTDIR)$(PREFIX)/bin/turbostat 21 + install -d $(DESTDIR)$(PREFIX)/share/man/man8 22 + install turbostat.8 $(DESTDIR)$(PREFIX)/share/man/man8

+67 -36

tools/power/x86/turbostat/turbostat.8

··· 11 11 .RB [ Options ] 12 12 .RB [ "\-i interval_sec" ] 13 13 .SH DESCRIPTION 14 - \fBturbostat \fP reports processor topology, frequency 15 - and idle power state statistics on modern X86 processors. 14 + \fBturbostat \fP reports processor topology, frequency, 15 + idle power-state statistics, temperature and power on modern X86 processors. 16 16 Either \fBcommand\fP is forked and statistics are printed 17 17 upon its completion, or statistics are printed periodically. 18 18 19 19 \fBturbostat \fP 20 - requires that the processor 20 + must be run on root, and 21 + minimally requires that the processor 21 22 supports an "invariant" TSC, plus the APERF and MPERF MSRs. 22 - \fBturbostat \fP will report idle cpu power state residency 23 - on processors that additionally support C-state residency counters. 23 + Additional information is reported depending on hardware counter support. 24 24 25 25 .SS Options 26 26 The \fB-p\fP option limits output to the 1st thread in 1st core of each package. ··· 57 57 \fBGHz\fP average clock rate while the CPU was in c0 state. 58 58 \fBTSC\fP average GHz that the TSC ran during the entire interval. 59 59 \fB%c1, %c3, %c6, %c7\fP show the percentage residency in hardware core idle states. 60 + \fBCTMP\fP Degrees Celsius reported by the per-core Digital Thermal Sensor. 61 + \fBPTMP\fP Degrees Celsius reported by the per-package Package Thermal Monitor. 60 62 \fB%pc2, %pc3, %pc6, %pc7\fP percentage residency in hardware package idle states. 63 + \fBPkg_W\fP Watts consumed by the whole package. 64 + \fBCor_W\fP Watts consumed by the core part of the package. 65 + \fBGFX_W\fP Watts consumed by the Graphics part of the package -- available only on client processors. 66 + \fBRAM_W\fP Watts consumed by the DRAM DIMMS -- available only on server processors. 67 + \fBPKG_%\fP percent of the interval that RAPL throttling was active on the Package. 68 + \fBRAM_%\fP percent of the interval that RAPL throttling was active on DRAM. 61 69 .fi 62 70 .PP 63 71 .SH EXAMPLE ··· 74 66 for turbostat to fork). 75 67 76 68 The first row of statistics is a summary for the entire system. 77 - Note that the summary is a weighted average. 69 + For residency % columns, the summary is a weighted average. 70 + For Temperature columns, the summary is the column maximum. 71 + For Watts columns, the summary is a system total. 78 72 Subsequent rows show per-CPU statistics. 79 73 80 74 .nf 81 - [root@x980]# ./turbostat 82 - cor CPU %c0 GHz TSC %c1 %c3 %c6 %pc3 %pc6 83 - 0.09 1.62 3.38 1.83 0.32 97.76 1.26 83.61 84 - 0 0 0.15 1.62 3.38 10.23 0.05 89.56 1.26 83.61 85 - 0 6 0.05 1.62 3.38 10.34 86 - 1 2 0.03 1.62 3.38 0.07 0.05 99.86 87 - 1 8 0.03 1.62 3.38 0.06 88 - 2 4 0.21 1.62 3.38 0.10 1.49 98.21 89 - 2 10 0.02 1.62 3.38 0.29 90 - 8 1 0.04 1.62 3.38 0.04 0.08 99.84 91 - 8 7 0.01 1.62 3.38 0.06 92 - 9 3 0.53 1.62 3.38 0.10 0.20 99.17 93 - 9 9 0.02 1.62 3.38 0.60 94 - 10 5 0.01 1.62 3.38 0.02 0.04 99.92 95 - 10 11 0.02 1.62 3.38 0.02 75 + [root@sandy]# ./turbostat 76 + cor CPU %c0 GHz TSC %c1 %c3 %c6 %c7 CTMP PTMP %pc2 %pc3 %pc6 %pc7 Pkg_W Cor_W GFX_W 77 + 0.06 0.80 2.29 0.11 0.00 0.00 99.83 47 40 0.26 0.01 0.44 98.78 3.49 0.12 0.14 78 + 0 0 0.07 0.80 2.29 0.07 0.00 0.00 99.86 40 40 0.26 0.01 0.44 98.78 3.49 0.12 0.14 79 + 0 4 0.03 0.80 2.29 0.12 80 + 1 1 0.04 0.80 2.29 0.25 0.01 0.00 99.71 40 81 + 1 5 0.16 0.80 2.29 0.13 82 + 2 2 0.05 0.80 2.29 0.06 0.01 0.00 99.88 40 83 + 2 6 0.03 0.80 2.29 0.08 84 + 3 3 0.05 0.80 2.29 0.08 0.00 0.00 99.87 47 85 + 3 7 0.04 0.84 2.29 0.09 96 86 .fi 97 87 .SH SUMMARY EXAMPLE 98 88 The "-s" option prints the column headers just once, 99 89 and then the one line system summary for each sample interval. 100 90 101 91 .nf 102 - [root@x980]# ./turbostat -s 103 - %c0 GHz TSC %c1 %c3 %c6 %pc3 %pc6 104 - 0.23 1.67 3.38 2.00 0.30 97.47 1.07 82.12 105 - 0.10 1.62 3.38 1.87 2.25 95.77 12.02 72.60 106 - 0.20 1.64 3.38 1.98 0.11 97.72 0.30 83.36 107 - 0.11 1.70 3.38 1.86 1.81 96.22 9.71 74.90 92 + [root@wsm]# turbostat -S 93 + %c0 GHz TSC %c1 %c3 %c6 CTMP %pc3 %pc6 94 + 1.40 2.81 3.38 10.78 43.47 44.35 42 13.67 2.09 95 + 1.34 2.90 3.38 11.48 58.96 28.23 41 19.89 0.15 96 + 1.55 2.72 3.38 26.73 37.66 34.07 42 2.53 2.80 97 + 1.37 2.83 3.38 16.95 60.05 21.63 42 5.76 0.20 108 98 .fi 109 99 .SH VERBOSE EXAMPLE 110 100 The "-v" option adds verbosity to the output: 111 101 112 102 .nf 113 - GenuineIntel 11 CPUID levels; family:model:stepping 0x6:2c:2 (6:44:2) 114 - 12 * 133 = 1600 MHz max efficiency 115 - 25 * 133 = 3333 MHz TSC frequency 116 - 26 * 133 = 3467 MHz max turbo 4 active cores 117 - 26 * 133 = 3467 MHz max turbo 3 active cores 118 - 27 * 133 = 3600 MHz max turbo 2 active cores 119 - 27 * 133 = 3600 MHz max turbo 1 active cores 120 - 103 + [root@ivy]# turbostat -v 104 + turbostat v3.0 November 23, 2012 - Len Brown <lenb@kernel.org> 105 + CPUID(0): GenuineIntel 13 CPUID levels; family:model:stepping 0x6:3a:9 (6:58:9) 106 + CPUID(6): APERF, DTS, PTM, EPB 107 + RAPL: 851 sec. Joule Counter Range 108 + cpu0: MSR_NHM_PLATFORM_INFO: 0x81010f0012300 109 + 16 * 100 = 1600 MHz max efficiency 110 + 35 * 100 = 3500 MHz TSC frequency 111 + cpu0: MSR_NHM_SNB_PKG_CST_CFG_CTL: 0x1e008402 (UNdemote-C3, UNdemote-C1, demote-C3, demote-C1, locked: pkg-cstate-limit=2: pc6-noret) 112 + cpu0: MSR_NHM_TURBO_RATIO_LIMIT: 0x25262727 113 + 37 * 100 = 3700 MHz max turbo 4 active cores 114 + 38 * 100 = 3800 MHz max turbo 3 active cores 115 + 39 * 100 = 3900 MHz max turbo 2 active cores 116 + 39 * 100 = 3900 MHz max turbo 1 active cores 117 + cpu0: MSR_IA32_ENERGY_PERF_BIAS: 0x00000006 (balanced) 118 + cpu0: MSR_RAPL_POWER_UNIT: 0x000a1003 (0.125000 Watts, 0.000015 Joules, 0.000977 sec.) 119 + cpu0: MSR_PKG_POWER_INFO: 0x01e00268 (77 W TDP, RAPL 60 - 0 W, 0.000000 sec.) 120 + cpu0: MSR_PKG_POWER_LIMIT: 0x830000148268 (UNlocked) 121 + cpu0: PKG Limit #1: ENabled (77.000000 Watts, 1.000000 sec, clamp DISabled) 122 + cpu0: PKG Limit #2: ENabled (96.000000 Watts, 0.000977* sec, clamp DISabled) 123 + cpu0: MSR_PP0_POLICY: 0 124 + cpu0: MSR_PP0_POWER_LIMIT: 0x00000000 (UNlocked) 125 + cpu0: Cores Limit: DISabled (0.000000 Watts, 0.000977 sec, clamp DISabled) 126 + cpu0: MSR_PP1_POLICY: 0 127 + cpu0: MSR_PP1_POWER_LIMIT: 0x00000000 (UNlocked) 128 + cpu0: GFX Limit: DISabled (0.000000 Watts, 0.000977 sec, clamp DISabled) 129 + cpu0: MSR_IA32_TEMPERATURE_TARGET: 0x00691400 (105 C) 130 + cpu0: MSR_IA32_PACKAGE_THERM_STATUS: 0x884e0000 (27 C) 131 + cpu0: MSR_IA32_THERM_STATUS: 0x88560000 (19 C +/- 1) 132 + cpu1: MSR_IA32_THERM_STATUS: 0x88560000 (19 C +/- 1) 133 + cpu2: MSR_IA32_THERM_STATUS: 0x88540000 (21 C +/- 1) 134 + cpu3: MSR_IA32_THERM_STATUS: 0x884e0000 (27 C +/- 1) 135 + ... 121 136 .fi 122 137 The \fBmax efficiency\fP frequency, a.k.a. Low Frequency Mode, is the frequency 123 138 available at the minimum package voltage. The \fBTSC frequency\fP is the nominal ··· 173 142 10 5 1.42 3.43 3.38 2.14 30.99 65.44 174 143 10 11 0.16 2.88 3.38 3.40 175 144 .fi 176 - Above the cycle soaker drives cpu7 up its 3.6 Ghz turbo limit 145 + Above the cycle soaker drives cpu7 up its 3.6 GHz turbo limit 177 146 while the other processors are generally in various states of idle. 178 147 179 148 Note that cpu1 and cpu7 are HT siblings within core8.

+639 -38

tools/power/x86/turbostat/turbostat.c

··· 20 20 */ 21 21 22 22 #define _GNU_SOURCE 23 + #include <asm/msr.h> 23 24 #include <stdio.h> 24 25 #include <unistd.h> 25 26 #include <sys/types.h> ··· 36 35 #include <ctype.h> 37 36 #include <sched.h> 38 37 39 - #define MSR_NEHALEM_PLATFORM_INFO 0xCE 40 - #define MSR_NEHALEM_TURBO_RATIO_LIMIT 0x1AD 41 - #define MSR_IVT_TURBO_RATIO_LIMIT 0x1AE 42 - #define MSR_APERF 0xE8 43 - #define MSR_MPERF 0xE7 44 - #define MSR_PKG_C2_RESIDENCY 0x60D /* SNB only */ 45 - #define MSR_PKG_C3_RESIDENCY 0x3F8 46 - #define MSR_PKG_C6_RESIDENCY 0x3F9 47 - #define MSR_PKG_C7_RESIDENCY 0x3FA /* SNB only */ 48 - #define MSR_CORE_C3_RESIDENCY 0x3FC 49 - #define MSR_CORE_C6_RESIDENCY 0x3FD 50 - #define MSR_CORE_C7_RESIDENCY 0x3FE /* SNB only */ 51 - 52 38 char *proc_stat = "/proc/stat"; 53 39 unsigned int interval_sec = 5; /* set with -i interval_sec */ 54 40 unsigned int verbose; /* set with -v */ 41 + unsigned int rapl_verbose; /* set with -R */ 42 + unsigned int thermal_verbose; /* set with -T */ 55 43 unsigned int summary_only; /* set with -s */ 56 44 unsigned int skip_c0; 57 45 unsigned int skip_c1; 58 46 unsigned int do_nhm_cstates; 59 47 unsigned int do_snb_cstates; 60 48 unsigned int has_aperf; 49 + unsigned int has_epb; 61 50 unsigned int units = 1000000000; /* Ghz etc */ 62 51 unsigned int genuine_intel; 63 52 unsigned int has_invariant_tsc; ··· 65 74 unsigned int show_pkg_only; 66 75 unsigned int show_core_only; 67 76 char *output_buffer, *outp; 77 + unsigned int do_rapl; 78 + unsigned int do_dts; 79 + unsigned int do_ptm; 80 + unsigned int tcc_activation_temp; 81 + unsigned int tcc_activation_temp_override; 82 + double rapl_power_units, rapl_energy_units, rapl_time_units; 83 + double rapl_joule_counter_range; 84 + 85 + #define RAPL_PKG (1 << 0) 86 + #define RAPL_CORES (1 << 1) 87 + #define RAPL_GFX (1 << 2) 88 + #define RAPL_DRAM (1 << 3) 89 + #define RAPL_PKG_PERF_STATUS (1 << 4) 90 + #define RAPL_DRAM_PERF_STATUS (1 << 5) 91 + #define TJMAX_DEFAULT 100 92 + 93 + #define MAX(a, b) ((a) > (b) ? (a) : (b)) 68 94 69 95 int aperf_mperf_unstable; 70 96 int backwards_count; ··· 109 101 unsigned long long c3; 110 102 unsigned long long c6; 111 103 unsigned long long c7; 104 + unsigned int core_temp_c; 112 105 unsigned int core_id; 113 106 } *core_even, *core_odd; 114 107 ··· 119 110 unsigned long long pc6; 120 111 unsigned long long pc7; 121 112 unsigned int package_id; 113 + unsigned int energy_pkg; /* MSR_PKG_ENERGY_STATUS */ 114 + unsigned int energy_dram; /* MSR_DRAM_ENERGY_STATUS */ 115 + unsigned int energy_cores; /* MSR_PP0_ENERGY_STATUS */ 116 + unsigned int energy_gfx; /* MSR_PP1_ENERGY_STATUS */ 117 + unsigned int rapl_pkg_perf_status; /* MSR_PKG_PERF_STATUS */ 118 + unsigned int rapl_dram_perf_status; /* MSR_DRAM_PERF_STATUS */ 119 + unsigned int pkg_temp_c; 120 + 122 121 } *package_even, *package_odd; 123 122 124 123 #define ODD_COUNTERS thread_odd, core_odd, package_odd ··· 264 247 outp += sprintf(outp, " %%c6"); 265 248 if (do_snb_cstates) 266 249 outp += sprintf(outp, " %%c7"); 250 + 251 + if (do_dts) 252 + outp += sprintf(outp, " CTMP"); 253 + if (do_ptm) 254 + outp += sprintf(outp, " PTMP"); 255 + 267 256 if (do_snb_cstates) 268 257 outp += sprintf(outp, " %%pc2"); 269 258 if (do_nhm_cstates) ··· 278 255 outp += sprintf(outp, " %%pc6"); 279 256 if (do_snb_cstates) 280 257 outp += sprintf(outp, " %%pc7"); 258 + 259 + if (do_rapl & RAPL_PKG) 260 + outp += sprintf(outp, " Pkg_W"); 261 + if (do_rapl & RAPL_CORES) 262 + outp += sprintf(outp, " Cor_W"); 263 + if (do_rapl & RAPL_GFX) 264 + outp += sprintf(outp, " GFX_W"); 265 + if (do_rapl & RAPL_DRAM) 266 + outp += sprintf(outp, " RAM_W"); 267 + if (do_rapl & RAPL_PKG_PERF_STATUS) 268 + outp += sprintf(outp, " PKG_%%"); 269 + if (do_rapl & RAPL_DRAM_PERF_STATUS) 270 + outp += sprintf(outp, " RAM_%%"); 281 271 282 272 outp += sprintf(outp, "\n"); 283 273 } ··· 321 285 fprintf(stderr, "c3: %016llX\n", c->c3); 322 286 fprintf(stderr, "c6: %016llX\n", c->c6); 323 287 fprintf(stderr, "c7: %016llX\n", c->c7); 288 + fprintf(stderr, "DTS: %dC\n", c->core_temp_c); 324 289 } 325 290 326 291 if (p) { ··· 330 293 fprintf(stderr, "pc3: %016llX\n", p->pc3); 331 294 fprintf(stderr, "pc6: %016llX\n", p->pc6); 332 295 fprintf(stderr, "pc7: %016llX\n", p->pc7); 296 + fprintf(stderr, "Joules PKG: %0X\n", p->energy_pkg); 297 + fprintf(stderr, "Joules COR: %0X\n", p->energy_cores); 298 + fprintf(stderr, "Joules GFX: %0X\n", p->energy_gfx); 299 + fprintf(stderr, "Joules RAM: %0X\n", p->energy_dram); 300 + fprintf(stderr, "Throttle PKG: %0X\n", p->rapl_pkg_perf_status); 301 + fprintf(stderr, "Throttle RAM: %0X\n", p->rapl_dram_perf_status); 302 + fprintf(stderr, "PTM: %dC\n", p->pkg_temp_c); 333 303 } 334 304 return 0; 335 305 } ··· 346 302 * package: "pk" 2 columns %2d 347 303 * core: "cor" 3 columns %3d 348 304 * CPU: "CPU" 3 columns %3d 305 + * Pkg_W: %6.2 306 + * Cor_W: %6.2 307 + * GFX_W: %5.2 308 + * RAM_W: %5.2 349 309 * GHz: "GHz" 3 columns %3.2 350 310 * TSC: "TSC" 3 columns %3.2 351 311 * percentage " %pc3" %6.2 312 + * Perf Status percentage: %5.2 313 + * "CTMP" 4 columns %4d 352 314 */ 353 315 int format_counters(struct thread_data *t, struct core_data *c, 354 316 struct pkg_data *p) 355 317 { 356 318 double interval_float; 319 + char *fmt5, *fmt6; 357 320 358 321 /* if showing only 1st thread in core and this isn't one, bail out */ 359 322 if (show_core_only && !(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) ··· 400 349 if (show_cpu) 401 350 outp += sprintf(outp, " %3d", t->cpu_id); 402 351 } 403 - 404 352 /* %c0 */ 405 353 if (do_nhm_cstates) { 406 354 if (show_pkg || show_core || show_cpu) ··· 464 414 if (do_snb_cstates) 465 415 outp += sprintf(outp, " %6.2f", 100.0 * c->c7/t->tsc); 466 416 417 + if (do_dts) 418 + outp += sprintf(outp, " %4d", c->core_temp_c); 419 + 467 420 /* print per-package data only for 1st core in package */ 468 421 if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 469 422 goto done; 423 + 424 + if (do_ptm) 425 + outp += sprintf(outp, " %4d", p->pkg_temp_c); 470 426 471 427 if (do_snb_cstates) 472 428 outp += sprintf(outp, " %6.2f", 100.0 * p->pc2/t->tsc); ··· 482 426 outp += sprintf(outp, " %6.2f", 100.0 * p->pc6/t->tsc); 483 427 if (do_snb_cstates) 484 428 outp += sprintf(outp, " %6.2f", 100.0 * p->pc7/t->tsc); 429 + 430 + /* 431 + * If measurement interval exceeds minimum RAPL Joule Counter range, 432 + * indicate that results are suspect by printing "**" in fraction place. 433 + */ 434 + if (interval_float < rapl_joule_counter_range) { 435 + fmt5 = " %5.2f"; 436 + fmt6 = " %6.2f"; 437 + } else { 438 + fmt5 = " %3.0f**"; 439 + fmt6 = " %4.0f**"; 440 + } 441 + 442 + if (do_rapl & RAPL_PKG) 443 + outp += sprintf(outp, fmt6, p->energy_pkg * rapl_energy_units / interval_float); 444 + if (do_rapl & RAPL_CORES) 445 + outp += sprintf(outp, fmt6, p->energy_cores * rapl_energy_units / interval_float); 446 + if (do_rapl & RAPL_GFX) 447 + outp += sprintf(outp, fmt5, p->energy_gfx * rapl_energy_units / interval_float); 448 + if (do_rapl & RAPL_DRAM) 449 + outp += sprintf(outp, fmt5, p->energy_dram * rapl_energy_units / interval_float); 450 + if (do_rapl & RAPL_PKG_PERF_STATUS ) 451 + outp += sprintf(outp, fmt5, 100.0 * p->rapl_pkg_perf_status * rapl_time_units / interval_float); 452 + if (do_rapl & RAPL_DRAM_PERF_STATUS ) 453 + outp += sprintf(outp, fmt5, 100.0 * p->rapl_dram_perf_status * rapl_time_units / interval_float); 454 + 485 455 done: 486 456 outp += sprintf(outp, "\n"); 487 457 ··· 517 435 void flush_stdout() 518 436 { 519 437 fputs(output_buffer, stdout); 438 + fflush(stdout); 520 439 outp = output_buffer; 521 440 } 522 441 void flush_stderr() ··· 544 461 for_all_cpus(format_counters, t, c, p); 545 462 } 546 463 464 + #define DELTA_WRAP32(new, old) \ 465 + if (new > old) { \ 466 + old = new - old; \ 467 + } else { \ 468 + old = 0x100000000 + new - old; \ 469 + } 470 + 547 471 void 548 472 delta_package(struct pkg_data *new, struct pkg_data *old) 549 473 { ··· 558 468 old->pc3 = new->pc3 - old->pc3; 559 469 old->pc6 = new->pc6 - old->pc6; 560 470 old->pc7 = new->pc7 - old->pc7; 471 + old->pkg_temp_c = new->pkg_temp_c; 472 + 473 + DELTA_WRAP32(new->energy_pkg, old->energy_pkg); 474 + DELTA_WRAP32(new->energy_cores, old->energy_cores); 475 + DELTA_WRAP32(new->energy_gfx, old->energy_gfx); 476 + DELTA_WRAP32(new->energy_dram, old->energy_dram); 477 + DELTA_WRAP32(new->rapl_pkg_perf_status, old->rapl_pkg_perf_status); 478 + DELTA_WRAP32(new->rapl_dram_perf_status, old->rapl_dram_perf_status); 561 479 } 562 480 563 481 void ··· 574 476 old->c3 = new->c3 - old->c3; 575 477 old->c6 = new->c6 - old->c6; 576 478 old->c7 = new->c7 - old->c7; 479 + old->core_temp_c = new->core_temp_c; 577 480 } 578 481 579 482 /* ··· 681 582 c->c3 = 0; 682 583 c->c6 = 0; 683 584 c->c7 = 0; 585 + c->core_temp_c = 0; 684 586 685 587 p->pc2 = 0; 686 588 p->pc3 = 0; 687 589 p->pc6 = 0; 688 590 p->pc7 = 0; 591 + 592 + p->energy_pkg = 0; 593 + p->energy_dram = 0; 594 + p->energy_cores = 0; 595 + p->energy_gfx = 0; 596 + p->rapl_pkg_perf_status = 0; 597 + p->rapl_dram_perf_status = 0; 598 + p->pkg_temp_c = 0; 689 599 } 690 600 int sum_counters(struct thread_data *t, struct core_data *c, 691 601 struct pkg_data *p) ··· 715 607 average.cores.c6 += c->c6; 716 608 average.cores.c7 += c->c7; 717 609 610 + average.cores.core_temp_c = MAX(average.cores.core_temp_c, c->core_temp_c); 611 + 718 612 /* sum per-pkg values only for 1st core in pkg */ 719 613 if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 720 614 return 0; ··· 726 616 average.packages.pc6 += p->pc6; 727 617 average.packages.pc7 += p->pc7; 728 618 619 + average.packages.energy_pkg += p->energy_pkg; 620 + average.packages.energy_dram += p->energy_dram; 621 + average.packages.energy_cores += p->energy_cores; 622 + average.packages.energy_gfx += p->energy_gfx; 623 + 624 + average.packages.pkg_temp_c = MAX(average.packages.pkg_temp_c, p->pkg_temp_c); 625 + 626 + average.packages.rapl_pkg_perf_status += p->rapl_pkg_perf_status; 627 + average.packages.rapl_dram_perf_status += p->rapl_dram_perf_status; 729 628 return 0; 730 629 } 731 630 /* ··· 786 667 int get_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p) 787 668 { 788 669 int cpu = t->cpu_id; 670 + unsigned long long msr; 789 671 790 - if (cpu_migrate(cpu)) 672 + if (cpu_migrate(cpu)) { 673 + fprintf(stderr, "Could not migrate to CPU %d\n", cpu); 791 674 return -1; 675 + } 792 676 793 677 t->tsc = rdtsc(); /* we are running on local CPU of interest */ 794 678 795 679 if (has_aperf) { 796 - if (get_msr(cpu, MSR_APERF, &t->aperf)) 680 + if (get_msr(cpu, MSR_IA32_APERF, &t->aperf)) 797 681 return -3; 798 - if (get_msr(cpu, MSR_MPERF, &t->mperf)) 682 + if (get_msr(cpu, MSR_IA32_MPERF, &t->mperf)) 799 683 return -4; 800 684 } 801 685 802 686 if (extra_delta_offset32) { 803 - if (get_msr(cpu, extra_delta_offset32, &t->extra_delta32)) 687 + if (get_msr(cpu, extra_delta_offset32, &msr)) 804 688 return -5; 805 - t->extra_delta32 &= 0xFFFFFFFF; 689 + t->extra_delta32 = msr & 0xFFFFFFFF; 806 690 } 807 691 808 692 if (extra_delta_offset64) ··· 813 691 return -5; 814 692 815 693 if (extra_msr_offset32) { 816 - if (get_msr(cpu, extra_msr_offset32, &t->extra_msr32)) 694 + if (get_msr(cpu, extra_msr_offset32, &msr)) 817 695 return -5; 818 - t->extra_msr32 &= 0xFFFFFFFF; 696 + t->extra_msr32 = msr & 0xFFFFFFFF; 819 697 } 820 698 821 699 if (extra_msr_offset64) ··· 837 715 if (get_msr(cpu, MSR_CORE_C7_RESIDENCY, &c->c7)) 838 716 return -8; 839 717 718 + if (do_dts) { 719 + if (get_msr(cpu, MSR_IA32_THERM_STATUS, &msr)) 720 + return -9; 721 + c->core_temp_c = tcc_activation_temp - ((msr >> 16) & 0x7F); 722 + } 723 + 724 + 840 725 /* collect package counters only for 1st core in package */ 841 726 if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 842 727 return 0; ··· 860 731 if (get_msr(cpu, MSR_PKG_C7_RESIDENCY, &p->pc7)) 861 732 return -12; 862 733 } 734 + if (do_rapl & RAPL_PKG) { 735 + if (get_msr(cpu, MSR_PKG_ENERGY_STATUS, &msr)) 736 + return -13; 737 + p->energy_pkg = msr & 0xFFFFFFFF; 738 + } 739 + if (do_rapl & RAPL_CORES) { 740 + if (get_msr(cpu, MSR_PP0_ENERGY_STATUS, &msr)) 741 + return -14; 742 + p->energy_cores = msr & 0xFFFFFFFF; 743 + } 744 + if (do_rapl & RAPL_DRAM) { 745 + if (get_msr(cpu, MSR_DRAM_ENERGY_STATUS, &msr)) 746 + return -15; 747 + p->energy_dram = msr & 0xFFFFFFFF; 748 + } 749 + if (do_rapl & RAPL_GFX) { 750 + if (get_msr(cpu, MSR_PP1_ENERGY_STATUS, &msr)) 751 + return -16; 752 + p->energy_gfx = msr & 0xFFFFFFFF; 753 + } 754 + if (do_rapl & RAPL_PKG_PERF_STATUS) { 755 + if (get_msr(cpu, MSR_PKG_PERF_STATUS, &msr)) 756 + return -16; 757 + p->rapl_pkg_perf_status = msr & 0xFFFFFFFF; 758 + } 759 + if (do_rapl & RAPL_DRAM_PERF_STATUS) { 760 + if (get_msr(cpu, MSR_DRAM_PERF_STATUS, &msr)) 761 + return -16; 762 + p->rapl_dram_perf_status = msr & 0xFFFFFFFF; 763 + } 764 + if (do_ptm) { 765 + if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_STATUS, &msr)) 766 + return -17; 767 + p->pkg_temp_c = tcc_activation_temp - ((msr >> 16) & 0x7F); 768 + } 863 769 return 0; 864 770 } 865 771 ··· 906 742 if (!do_nehalem_platform_info) 907 743 return; 908 744 909 - get_msr(0, MSR_NEHALEM_PLATFORM_INFO, &msr); 745 + get_msr(0, MSR_NHM_PLATFORM_INFO, &msr); 910 746 911 - if (verbose > 1) 912 - fprintf(stderr, "MSR_NEHALEM_PLATFORM_INFO: 0x%llx\n", msr); 747 + if (verbose) 748 + fprintf(stderr, "cpu0: MSR_NHM_PLATFORM_INFO: 0x%08llx\n", msr); 913 749 914 750 ratio = (msr >> 40) & 0xFF; 915 751 fprintf(stderr, "%d * %.0f = %.0f MHz max efficiency\n", ··· 924 760 925 761 get_msr(0, MSR_IVT_TURBO_RATIO_LIMIT, &msr); 926 762 927 - if (verbose > 1) 928 - fprintf(stderr, "MSR_IVT_TURBO_RATIO_LIMIT: 0x%llx\n", msr); 763 + if (verbose) 764 + fprintf(stderr, "cpu0: MSR_IVT_TURBO_RATIO_LIMIT: 0x%08llx\n", msr); 929 765 930 766 ratio = (msr >> 56) & 0xFF; 931 767 if (ratio) ··· 968 804 ratio, bclk, ratio * bclk); 969 805 970 806 print_nhm_turbo_ratio_limits: 807 + get_msr(0, MSR_NHM_SNB_PKG_CST_CFG_CTL, &msr); 808 + 809 + #define SNB_C1_AUTO_UNDEMOTE (1UL << 27) 810 + #define SNB_C3_AUTO_UNDEMOTE (1UL << 28) 811 + 812 + fprintf(stderr, "cpu0: MSR_NHM_SNB_PKG_CST_CFG_CTL: 0x%08llx", msr); 813 + 814 + fprintf(stderr, " (%s%s%s%s%slocked: pkg-cstate-limit=%d: ", 815 + (msr & SNB_C3_AUTO_UNDEMOTE) ? "UNdemote-C3, " : "", 816 + (msr & SNB_C1_AUTO_UNDEMOTE) ? "UNdemote-C1, " : "", 817 + (msr & NHM_C3_AUTO_DEMOTE) ? "demote-C3, " : "", 818 + (msr & NHM_C1_AUTO_DEMOTE) ? "demote-C1, " : "", 819 + (msr & (1 << 15)) ? "" : "UN", 820 + (unsigned int)msr & 7); 821 + 822 + 823 + switch(msr & 0x7) { 824 + case 0: 825 + fprintf(stderr, "pc0"); 826 + break; 827 + case 1: 828 + fprintf(stderr, do_snb_cstates ? "pc2" : "pc0"); 829 + break; 830 + case 2: 831 + fprintf(stderr, do_snb_cstates ? "pc6-noret" : "pc3"); 832 + break; 833 + case 3: 834 + fprintf(stderr, "pc6"); 835 + break; 836 + case 4: 837 + fprintf(stderr, "pc7"); 838 + break; 839 + case 5: 840 + fprintf(stderr, do_snb_cstates ? "pc7s" : "invalid"); 841 + break; 842 + case 7: 843 + fprintf(stderr, "unlimited"); 844 + break; 845 + default: 846 + fprintf(stderr, "invalid"); 847 + } 848 + fprintf(stderr, ")\n"); 971 849 972 850 if (!do_nehalem_turbo_ratio_limit) 973 851 return; 974 852 975 - get_msr(0, MSR_NEHALEM_TURBO_RATIO_LIMIT, &msr); 853 + get_msr(0, MSR_NHM_TURBO_RATIO_LIMIT, &msr); 976 854 977 - if (verbose > 1) 978 - fprintf(stderr, "MSR_NEHALEM_TURBO_RATIO_LIMIT: 0x%llx\n", msr); 855 + if (verbose) 856 + fprintf(stderr, "cpu0: MSR_NHM_TURBO_RATIO_LIMIT: 0x%08llx\n", msr); 979 857 980 858 ratio = (msr >> 56) & 0xFF; 981 859 if (ratio) ··· 1306 1100 void turbostat_loop() 1307 1101 { 1308 1102 int retval; 1103 + int restarted = 0; 1309 1104 1310 1105 restart: 1106 + restarted++; 1107 + 1311 1108 retval = for_all_cpus(get_counters, EVEN_COUNTERS); 1312 1109 if (retval < -1) { 1313 1110 exit(retval); 1314 1111 } else if (retval == -1) { 1112 + if (restarted > 1) { 1113 + exit(retval); 1114 + } 1315 1115 re_initialize(); 1316 1116 goto restart; 1317 1117 } 1118 + restarted = 0; 1318 1119 gettimeofday(&tv_even, (struct timezone *)NULL); 1319 1120 1320 1121 while (1) { ··· 1420 1207 } 1421 1208 } 1422 1209 1210 + /* 1211 + * print_epb() 1212 + * Decode the ENERGY_PERF_BIAS MSR 1213 + */ 1214 + int print_epb(struct thread_data *t, struct core_data *c, struct pkg_data *p) 1215 + { 1216 + unsigned long long msr; 1217 + char *epb_string; 1218 + int cpu; 1219 + 1220 + if (!has_epb) 1221 + return 0; 1222 + 1223 + cpu = t->cpu_id; 1224 + 1225 + /* EPB is per-package */ 1226 + if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 1227 + return 0; 1228 + 1229 + if (cpu_migrate(cpu)) { 1230 + fprintf(stderr, "Could not migrate to CPU %d\n", cpu); 1231 + return -1; 1232 + } 1233 + 1234 + if (get_msr(cpu, MSR_IA32_ENERGY_PERF_BIAS, &msr)) 1235 + return 0; 1236 + 1237 + switch (msr & 0x7) { 1238 + case ENERGY_PERF_BIAS_PERFORMANCE: 1239 + epb_string = "performance"; 1240 + break; 1241 + case ENERGY_PERF_BIAS_NORMAL: 1242 + epb_string = "balanced"; 1243 + break; 1244 + case ENERGY_PERF_BIAS_POWERSAVE: 1245 + epb_string = "powersave"; 1246 + break; 1247 + default: 1248 + epb_string = "custom"; 1249 + break; 1250 + } 1251 + fprintf(stderr, "cpu%d: MSR_IA32_ENERGY_PERF_BIAS: 0x%08llx (%s)\n", cpu, msr, epb_string); 1252 + 1253 + return 0; 1254 + } 1255 + 1256 + #define RAPL_POWER_GRANULARITY 0x7FFF /* 15 bit power granularity */ 1257 + #define RAPL_TIME_GRANULARITY 0x3F /* 6 bit time granularity */ 1258 + 1259 + /* 1260 + * rapl_probe() 1261 + * 1262 + * sets do_rapl 1263 + */ 1264 + void rapl_probe(unsigned int family, unsigned int model) 1265 + { 1266 + unsigned long long msr; 1267 + double tdp; 1268 + 1269 + if (!genuine_intel) 1270 + return; 1271 + 1272 + if (family != 6) 1273 + return; 1274 + 1275 + switch (model) { 1276 + case 0x2A: 1277 + case 0x3A: 1278 + do_rapl = RAPL_PKG | RAPL_CORES | RAPL_GFX; 1279 + break; 1280 + case 0x2D: 1281 + case 0x3E: 1282 + do_rapl = RAPL_PKG | RAPL_CORES | RAPL_DRAM | RAPL_PKG_PERF_STATUS | RAPL_DRAM_PERF_STATUS; 1283 + break; 1284 + default: 1285 + return; 1286 + } 1287 + 1288 + /* units on package 0, verify later other packages match */ 1289 + if (get_msr(0, MSR_RAPL_POWER_UNIT, &msr)) 1290 + return; 1291 + 1292 + rapl_power_units = 1.0 / (1 << (msr & 0xF)); 1293 + rapl_energy_units = 1.0 / (1 << (msr >> 8 & 0x1F)); 1294 + rapl_time_units = 1.0 / (1 << (msr >> 16 & 0xF)); 1295 + 1296 + /* get TDP to determine energy counter range */ 1297 + if (get_msr(0, MSR_PKG_POWER_INFO, &msr)) 1298 + return; 1299 + 1300 + tdp = ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units; 1301 + 1302 + rapl_joule_counter_range = 0xFFFFFFFF * rapl_energy_units / tdp; 1303 + 1304 + if (verbose) 1305 + fprintf(stderr, "RAPL: %.0f sec. Joule Counter Range\n", rapl_joule_counter_range); 1306 + 1307 + return; 1308 + } 1309 + 1310 + int print_thermal(struct thread_data *t, struct core_data *c, struct pkg_data *p) 1311 + { 1312 + unsigned long long msr; 1313 + unsigned int dts; 1314 + int cpu; 1315 + 1316 + if (!(do_dts || do_ptm)) 1317 + return 0; 1318 + 1319 + cpu = t->cpu_id; 1320 + 1321 + /* DTS is per-core, no need to print for each thread */ 1322 + if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) 1323 + return 0; 1324 + 1325 + if (cpu_migrate(cpu)) { 1326 + fprintf(stderr, "Could not migrate to CPU %d\n", cpu); 1327 + return -1; 1328 + } 1329 + 1330 + if (do_ptm && (t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) { 1331 + if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_STATUS, &msr)) 1332 + return 0; 1333 + 1334 + dts = (msr >> 16) & 0x7F; 1335 + fprintf(stderr, "cpu%d: MSR_IA32_PACKAGE_THERM_STATUS: 0x%08llx (%d C)\n", 1336 + cpu, msr, tcc_activation_temp - dts); 1337 + 1338 + #ifdef THERM_DEBUG 1339 + if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_INTERRUPT, &msr)) 1340 + return 0; 1341 + 1342 + dts = (msr >> 16) & 0x7F; 1343 + dts2 = (msr >> 8) & 0x7F; 1344 + fprintf(stderr, "cpu%d: MSR_IA32_PACKAGE_THERM_INTERRUPT: 0x%08llx (%d C, %d C)\n", 1345 + cpu, msr, tcc_activation_temp - dts, tcc_activation_temp - dts2); 1346 + #endif 1347 + } 1348 + 1349 + 1350 + if (do_dts) { 1351 + unsigned int resolution; 1352 + 1353 + if (get_msr(cpu, MSR_IA32_THERM_STATUS, &msr)) 1354 + return 0; 1355 + 1356 + dts = (msr >> 16) & 0x7F; 1357 + resolution = (msr >> 27) & 0xF; 1358 + fprintf(stderr, "cpu%d: MSR_IA32_THERM_STATUS: 0x%08llx (%d C +/- %d)\n", 1359 + cpu, msr, tcc_activation_temp - dts, resolution); 1360 + 1361 + #ifdef THERM_DEBUG 1362 + if (get_msr(cpu, MSR_IA32_THERM_INTERRUPT, &msr)) 1363 + return 0; 1364 + 1365 + dts = (msr >> 16) & 0x7F; 1366 + dts2 = (msr >> 8) & 0x7F; 1367 + fprintf(stderr, "cpu%d: MSR_IA32_THERM_INTERRUPT: 0x%08llx (%d C, %d C)\n", 1368 + cpu, msr, tcc_activation_temp - dts, tcc_activation_temp - dts2); 1369 + #endif 1370 + } 1371 + 1372 + return 0; 1373 + } 1374 + 1375 + void print_power_limit_msr(int cpu, unsigned long long msr, char *label) 1376 + { 1377 + fprintf(stderr, "cpu%d: %s: %sabled (%f Watts, %f sec, clamp %sabled)\n", 1378 + cpu, label, 1379 + ((msr >> 15) & 1) ? "EN" : "DIS", 1380 + ((msr >> 0) & 0x7FFF) * rapl_power_units, 1381 + (1.0 + (((msr >> 22) & 0x3)/4.0)) * (1 << ((msr >> 17) & 0x1F)) * rapl_time_units, 1382 + (((msr >> 16) & 1) ? "EN" : "DIS")); 1383 + 1384 + return; 1385 + } 1386 + 1387 + int print_rapl(struct thread_data *t, struct core_data *c, struct pkg_data *p) 1388 + { 1389 + unsigned long long msr; 1390 + int cpu; 1391 + double local_rapl_power_units, local_rapl_energy_units, local_rapl_time_units; 1392 + 1393 + if (!do_rapl) 1394 + return 0; 1395 + 1396 + /* RAPL counters are per package, so print only for 1st thread/package */ 1397 + if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 1398 + return 0; 1399 + 1400 + cpu = t->cpu_id; 1401 + if (cpu_migrate(cpu)) { 1402 + fprintf(stderr, "Could not migrate to CPU %d\n", cpu); 1403 + return -1; 1404 + } 1405 + 1406 + if (get_msr(cpu, MSR_RAPL_POWER_UNIT, &msr)) 1407 + return -1; 1408 + 1409 + local_rapl_power_units = 1.0 / (1 << (msr & 0xF)); 1410 + local_rapl_energy_units = 1.0 / (1 << (msr >> 8 & 0x1F)); 1411 + local_rapl_time_units = 1.0 / (1 << (msr >> 16 & 0xF)); 1412 + 1413 + if (local_rapl_power_units != rapl_power_units) 1414 + fprintf(stderr, "cpu%d, ERROR: Power units mis-match\n", cpu); 1415 + if (local_rapl_energy_units != rapl_energy_units) 1416 + fprintf(stderr, "cpu%d, ERROR: Energy units mis-match\n", cpu); 1417 + if (local_rapl_time_units != rapl_time_units) 1418 + fprintf(stderr, "cpu%d, ERROR: Time units mis-match\n", cpu); 1419 + 1420 + if (verbose) { 1421 + fprintf(stderr, "cpu%d: MSR_RAPL_POWER_UNIT: 0x%08llx " 1422 + "(%f Watts, %f Joules, %f sec.)\n", cpu, msr, 1423 + local_rapl_power_units, local_rapl_energy_units, local_rapl_time_units); 1424 + } 1425 + if (do_rapl & RAPL_PKG) { 1426 + if (get_msr(cpu, MSR_PKG_POWER_INFO, &msr)) 1427 + return -5; 1428 + 1429 + 1430 + fprintf(stderr, "cpu%d: MSR_PKG_POWER_INFO: 0x%08llx (%.0f W TDP, RAPL %.0f - %.0f W, %f sec.)\n", 1431 + cpu, msr, 1432 + ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units, 1433 + ((msr >> 16) & RAPL_POWER_GRANULARITY) * rapl_power_units, 1434 + ((msr >> 32) & RAPL_POWER_GRANULARITY) * rapl_power_units, 1435 + ((msr >> 48) & RAPL_TIME_GRANULARITY) * rapl_time_units); 1436 + 1437 + if (get_msr(cpu, MSR_PKG_POWER_LIMIT, &msr)) 1438 + return -9; 1439 + 1440 + fprintf(stderr, "cpu%d: MSR_PKG_POWER_LIMIT: 0x%08llx (%slocked)\n", 1441 + cpu, msr, (msr >> 63) & 1 ? "": "UN"); 1442 + 1443 + print_power_limit_msr(cpu, msr, "PKG Limit #1"); 1444 + fprintf(stderr, "cpu%d: PKG Limit #2: %sabled (%f Watts, %f* sec, clamp %sabled)\n", 1445 + cpu, 1446 + ((msr >> 47) & 1) ? "EN" : "DIS", 1447 + ((msr >> 32) & 0x7FFF) * rapl_power_units, 1448 + (1.0 + (((msr >> 54) & 0x3)/4.0)) * (1 << ((msr >> 49) & 0x1F)) * rapl_time_units, 1449 + ((msr >> 48) & 1) ? "EN" : "DIS"); 1450 + } 1451 + 1452 + if (do_rapl & RAPL_DRAM) { 1453 + if (get_msr(cpu, MSR_DRAM_POWER_INFO, &msr)) 1454 + return -6; 1455 + 1456 + 1457 + fprintf(stderr, "cpu%d: MSR_DRAM_POWER_INFO,: 0x%08llx (%.0f W TDP, RAPL %.0f - %.0f W, %f sec.)\n", 1458 + cpu, msr, 1459 + ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units, 1460 + ((msr >> 16) & RAPL_POWER_GRANULARITY) * rapl_power_units, 1461 + ((msr >> 32) & RAPL_POWER_GRANULARITY) * rapl_power_units, 1462 + ((msr >> 48) & RAPL_TIME_GRANULARITY) * rapl_time_units); 1463 + 1464 + 1465 + if (get_msr(cpu, MSR_DRAM_POWER_LIMIT, &msr)) 1466 + return -9; 1467 + fprintf(stderr, "cpu%d: MSR_DRAM_POWER_LIMIT: 0x%08llx (%slocked)\n", 1468 + cpu, msr, (msr >> 31) & 1 ? "": "UN"); 1469 + 1470 + print_power_limit_msr(cpu, msr, "DRAM Limit"); 1471 + } 1472 + if (do_rapl & RAPL_CORES) { 1473 + if (verbose) { 1474 + if (get_msr(cpu, MSR_PP0_POLICY, &msr)) 1475 + return -7; 1476 + 1477 + fprintf(stderr, "cpu%d: MSR_PP0_POLICY: %lld\n", cpu, msr & 0xF); 1478 + 1479 + if (get_msr(cpu, MSR_PP0_POWER_LIMIT, &msr)) 1480 + return -9; 1481 + fprintf(stderr, "cpu%d: MSR_PP0_POWER_LIMIT: 0x%08llx (%slocked)\n", 1482 + cpu, msr, (msr >> 31) & 1 ? "": "UN"); 1483 + print_power_limit_msr(cpu, msr, "Cores Limit"); 1484 + } 1485 + } 1486 + if (do_rapl & RAPL_GFX) { 1487 + if (verbose) { 1488 + if (get_msr(cpu, MSR_PP1_POLICY, &msr)) 1489 + return -8; 1490 + 1491 + fprintf(stderr, "cpu%d: MSR_PP1_POLICY: %lld\n", cpu, msr & 0xF); 1492 + 1493 + if (get_msr(cpu, MSR_PP1_POWER_LIMIT, &msr)) 1494 + return -9; 1495 + fprintf(stderr, "cpu%d: MSR_PP1_POWER_LIMIT: 0x%08llx (%slocked)\n", 1496 + cpu, msr, (msr >> 31) & 1 ? "": "UN"); 1497 + print_power_limit_msr(cpu, msr, "GFX Limit"); 1498 + } 1499 + } 1500 + return 0; 1501 + } 1502 + 1423 1503 1424 1504 int is_snb(unsigned int family, unsigned int model) 1425 1505 { ··· 1737 1231 return 133.33; 1738 1232 } 1739 1233 1234 + /* 1235 + * MSR_IA32_TEMPERATURE_TARGET indicates the temperature where 1236 + * the Thermal Control Circuit (TCC) activates. 1237 + * This is usually equal to tjMax. 1238 + * 1239 + * Older processors do not have this MSR, so there we guess, 1240 + * but also allow cmdline over-ride with -T. 1241 + * 1242 + * Several MSR temperature values are in units of degrees-C 1243 + * below this value, including the Digital Thermal Sensor (DTS), 1244 + * Package Thermal Management Sensor (PTM), and thermal event thresholds. 1245 + */ 1246 + int set_temperature_target(struct thread_data *t, struct core_data *c, struct pkg_data *p) 1247 + { 1248 + unsigned long long msr; 1249 + unsigned int target_c_local; 1250 + int cpu; 1251 + 1252 + /* tcc_activation_temp is used only for dts or ptm */ 1253 + if (!(do_dts || do_ptm)) 1254 + return 0; 1255 + 1256 + /* this is a per-package concept */ 1257 + if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 1258 + return 0; 1259 + 1260 + cpu = t->cpu_id; 1261 + if (cpu_migrate(cpu)) { 1262 + fprintf(stderr, "Could not migrate to CPU %d\n", cpu); 1263 + return -1; 1264 + } 1265 + 1266 + if (tcc_activation_temp_override != 0) { 1267 + tcc_activation_temp = tcc_activation_temp_override; 1268 + fprintf(stderr, "cpu%d: Using cmdline TCC Target (%d C)\n", 1269 + cpu, tcc_activation_temp); 1270 + return 0; 1271 + } 1272 + 1273 + /* Temperature Target MSR is Nehalem and newer only */ 1274 + if (!do_nehalem_platform_info) 1275 + goto guess; 1276 + 1277 + if (get_msr(0, MSR_IA32_TEMPERATURE_TARGET, &msr)) 1278 + goto guess; 1279 + 1280 + target_c_local = (msr >> 16) & 0x7F; 1281 + 1282 + if (verbose) 1283 + fprintf(stderr, "cpu%d: MSR_IA32_TEMPERATURE_TARGET: 0x%08llx (%d C)\n", 1284 + cpu, msr, target_c_local); 1285 + 1286 + if (target_c_local < 85 || target_c_local > 120) 1287 + goto guess; 1288 + 1289 + tcc_activation_temp = target_c_local; 1290 + 1291 + return 0; 1292 + 1293 + guess: 1294 + tcc_activation_temp = TJMAX_DEFAULT; 1295 + fprintf(stderr, "cpu%d: Guessing tjMax %d C, Please use -T to specify\n", 1296 + cpu, tcc_activation_temp); 1297 + 1298 + return 0; 1299 + } 1740 1300 void check_cpuid() 1741 1301 { 1742 1302 unsigned int eax, ebx, ecx, edx, max_level; ··· 1816 1244 genuine_intel = 1; 1817 1245 1818 1246 if (verbose) 1819 - fprintf(stderr, "%.4s%.4s%.4s ", 1247 + fprintf(stderr, "CPUID(0): %.4s%.4s%.4s ", 1820 1248 (char *)&ebx, (char *)&edx, (char *)&ecx); 1821 1249 1822 1250 asm("cpuid" : "=a" (fms), "=c" (ecx), "=d" (edx) : "a" (1) : "ebx"); ··· 1867 1295 1868 1296 asm("cpuid" : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx) : "a" (0x6)); 1869 1297 has_aperf = ecx & (1 << 0); 1870 - if (!has_aperf) { 1871 - fprintf(stderr, "No APERF MSR\n"); 1872 - exit(1); 1873 - } 1298 + do_dts = eax & (1 << 0); 1299 + do_ptm = eax & (1 << 6); 1300 + has_epb = ecx & (1 << 3); 1301 + 1302 + if (verbose) 1303 + fprintf(stderr, "CPUID(6): %s%s%s%s\n", 1304 + has_aperf ? "APERF" : "No APERF!", 1305 + do_dts ? ", DTS" : "", 1306 + do_ptm ? ", PTM": "", 1307 + has_epb ? ", EPB": ""); 1308 + 1309 + if (!has_aperf) 1310 + exit(-1); 1874 1311 1875 1312 do_nehalem_platform_info = genuine_intel && has_invariant_tsc; 1876 1313 do_nhm_cstates = genuine_intel; /* all Intel w/ non-stop TSC have NHM counters */ ··· 1888 1307 1889 1308 do_nehalem_turbo_ratio_limit = has_nehalem_turbo_ratio_limit(family, model); 1890 1309 do_ivt_turbo_ratio_limit = has_ivt_turbo_ratio_limit(family, model); 1310 + rapl_probe(family, model); 1311 + 1312 + return; 1891 1313 } 1892 1314 1893 1315 1894 1316 void usage() 1895 1317 { 1896 - fprintf(stderr, "%s: [-v][-p|-P|-S][-c MSR# | -s]][-C MSR#][-m MSR#][-M MSR#][-i interval_sec | command ...]\n", 1318 + fprintf(stderr, "%s: [-v][-R][-T][-p|-P|-S][-c MSR# | -s]][-C MSR#][-m MSR#][-M MSR#][-i interval_sec | command ...]\n", 1897 1319 progname); 1898 1320 exit(1); 1899 1321 } ··· 2132 1548 2133 1549 if (verbose) 2134 1550 print_verbose_header(); 1551 + 1552 + if (verbose) 1553 + for_all_cpus(print_epb, ODD_COUNTERS); 1554 + 1555 + if (verbose) 1556 + for_all_cpus(print_rapl, ODD_COUNTERS); 1557 + 1558 + for_all_cpus(set_temperature_target, ODD_COUNTERS); 1559 + 1560 + if (verbose) 1561 + for_all_cpus(print_thermal, ODD_COUNTERS); 2135 1562 } 2136 1563 2137 1564 int fork_it(char **argv) ··· 2199 1604 2200 1605 progname = argv[0]; 2201 1606 2202 - while ((opt = getopt(argc, argv, "+pPSvi:sc:sC:m:M:")) != -1) { 1607 + while ((opt = getopt(argc, argv, "+pPSvi:sc:sC:m:M:RT:")) != -1) { 2203 1608 switch (opt) { 2204 1609 case 'p': 2205 1610 show_core_only++; ··· 2231 1636 case 'M': 2232 1637 sscanf(optarg, "%x", &extra_msr_offset64); 2233 1638 break; 1639 + case 'R': 1640 + rapl_verbose++; 1641 + break; 1642 + case 'T': 1643 + tcc_activation_temp_override = atoi(optarg); 1644 + break; 2234 1645 default: 2235 1646 usage(); 2236 1647 } ··· 2247 1646 { 2248 1647 cmdline(argc, argv); 2249 1648 2250 - if (verbose > 1) 2251 - fprintf(stderr, "turbostat v2.1 October 6, 2012" 1649 + if (verbose) 1650 + fprintf(stderr, "turbostat v3.0 November 23, 2012" 2252 1651 " - Len Brown <lenb@kernel.org>\n"); 2253 1652 2254 1653 turbostat_init();

+4 -2

tools/power/x86/x86_energy_perf_policy/Makefile

··· 1 + DESTDIR ?= 2 + 1 3 x86_energy_perf_policy : x86_energy_perf_policy.c 2 4 3 5 clean : 4 6 rm -f x86_energy_perf_policy 5 7 6 8 install : 7 - install x86_energy_perf_policy /usr/bin/ 8 - install x86_energy_perf_policy.8 /usr/share/man/man8/ 9 + install x86_energy_perf_policy ${DESTDIR}/usr/bin/ 10 + install x86_energy_perf_policy.8 ${DESTDIR}/usr/share/man/man8/

+1 -1

tools/power/x86/x86_energy_perf_policy/x86_energy_perf_policy.c

··· 289 289 "cpu%u %*d %*d %*d %*d %*d %*d %*d %*d %*d %*d\n", 290 290 &cpu); 291 291 if (retval != 1) 292 - return; 292 + break; 293 293 294 294 func(cpu); 295 295 }