tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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drm/panel: sitronix-st7703: transition to mipi_dsi wrapped functions

Use functions introduced in commit 966e397e4f60 ("drm/mipi-dsi:
Introduce mipi_dsi_*_write_seq_multi()") and commit f79d6d28d8fe
("drm/mipi-dsi: wrap more functions for streamline handling") for
sitronix-st7703 based panels.

Signed-off-by: Tejas Vipin <tejasvipin76@gmail.com>
Reviewed-by: Guido Günther <agx@sigxcpu.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20240626045244.48858-1-tejasvipin76@gmail.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20240626045244.48858-1-tejasvipin76@gmail.com

authored by

Tejas Vipin and committed by
Neil Armstrong 68145ceb d5316cdd

+392 -428
+392 -428
drivers/gpu/drm/panel/panel-sitronix-st7703.c
··· 69 69 unsigned int lanes; 70 70 unsigned long mode_flags; 71 71 enum mipi_dsi_pixel_format format; 72 - int (*init_sequence)(struct st7703 *ctx); 72 + void (*init_sequence)(struct mipi_dsi_multi_context *dsi_ctx); 73 73 }; 74 74 75 75 static inline struct st7703 *panel_to_st7703(struct drm_panel *panel) ··· 77 77 return container_of(panel, struct st7703, panel); 78 78 } 79 79 80 - static int jh057n_init_sequence(struct st7703 *ctx) 80 + static void jh057n_init_sequence(struct mipi_dsi_multi_context *dsi_ctx) 81 81 { 82 - struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev); 83 - 84 82 /* 85 83 * Init sequence was supplied by the panel vendor. Most of the commands 86 84 * resemble the ST7703 but the number of parameters often don't match 87 85 * so it's likely a clone. 88 86 */ 89 - mipi_dsi_generic_write_seq(dsi, ST7703_CMD_SETEXTC, 90 - 0xF1, 0x12, 0x83); 91 - mipi_dsi_generic_write_seq(dsi, ST7703_CMD_SETRGBIF, 92 - 0x10, 0x10, 0x05, 0x05, 0x03, 0xFF, 0x00, 0x00, 93 - 0x00, 0x00); 94 - mipi_dsi_generic_write_seq(dsi, ST7703_CMD_SETSCR, 95 - 0x73, 0x73, 0x50, 0x50, 0x00, 0x00, 0x08, 0x70, 96 - 0x00); 97 - mipi_dsi_generic_write_seq(dsi, ST7703_CMD_SETVDC, 0x4E); 98 - mipi_dsi_generic_write_seq(dsi, ST7703_CMD_SETPANEL, 0x0B); 99 - mipi_dsi_generic_write_seq(dsi, ST7703_CMD_SETCYC, 0x80); 100 - mipi_dsi_generic_write_seq(dsi, ST7703_CMD_SETDISP, 0xF0, 0x12, 0x30); 101 - mipi_dsi_generic_write_seq(dsi, ST7703_CMD_SETEQ, 102 - 0x07, 0x07, 0x0B, 0x0B, 0x03, 0x0B, 0x00, 0x00, 103 - 0x00, 0x00, 0xFF, 0x00, 0xC0, 0x10); 104 - mipi_dsi_generic_write_seq(dsi, ST7703_CMD_SETBGP, 0x08, 0x08); 105 - msleep(20); 87 + mipi_dsi_generic_write_seq_multi(dsi_ctx, ST7703_CMD_SETEXTC, 88 + 0xF1, 0x12, 0x83); 89 + mipi_dsi_generic_write_seq_multi(dsi_ctx, ST7703_CMD_SETRGBIF, 90 + 0x10, 0x10, 0x05, 0x05, 0x03, 0xFF, 0x00, 0x00, 91 + 0x00, 0x00); 92 + mipi_dsi_generic_write_seq_multi(dsi_ctx, ST7703_CMD_SETSCR, 93 + 0x73, 0x73, 0x50, 0x50, 0x00, 0x00, 0x08, 0x70, 94 + 0x00); 95 + mipi_dsi_generic_write_seq_multi(dsi_ctx, ST7703_CMD_SETVDC, 0x4E); 96 + mipi_dsi_generic_write_seq_multi(dsi_ctx, ST7703_CMD_SETPANEL, 0x0B); 97 + mipi_dsi_generic_write_seq_multi(dsi_ctx, ST7703_CMD_SETCYC, 0x80); 98 + mipi_dsi_generic_write_seq_multi(dsi_ctx, ST7703_CMD_SETDISP, 0xF0, 0x12, 0x30); 99 + mipi_dsi_generic_write_seq_multi(dsi_ctx, ST7703_CMD_SETEQ, 100 + 0x07, 0x07, 0x0B, 0x0B, 0x03, 0x0B, 0x00, 0x00, 101 + 0x00, 0x00, 0xFF, 0x00, 0xC0, 0x10); 102 + mipi_dsi_generic_write_seq_multi(dsi_ctx, ST7703_CMD_SETBGP, 0x08, 0x08); 103 + mipi_dsi_msleep(dsi_ctx, 20); 106 104 107 - mipi_dsi_generic_write_seq(dsi, ST7703_CMD_SETVCOM, 0x3F, 0x3F); 108 - mipi_dsi_generic_write_seq(dsi, ST7703_CMD_UNKNOWN_BF, 0x02, 0x11, 0x00); 109 - mipi_dsi_generic_write_seq(dsi, ST7703_CMD_SETGIP1, 110 - 0x82, 0x10, 0x06, 0x05, 0x9E, 0x0A, 0xA5, 0x12, 111 - 0x31, 0x23, 0x37, 0x83, 0x04, 0xBC, 0x27, 0x38, 112 - 0x0C, 0x00, 0x03, 0x00, 0x00, 0x00, 0x0C, 0x00, 113 - 0x03, 0x00, 0x00, 0x00, 0x75, 0x75, 0x31, 0x88, 114 - 0x88, 0x88, 0x88, 0x88, 0x88, 0x13, 0x88, 0x64, 115 - 0x64, 0x20, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 116 - 0x02, 0x88, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 117 - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00); 118 - mipi_dsi_generic_write_seq(dsi, ST7703_CMD_SETGIP2, 119 - 0x02, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 120 - 0x00, 0x00, 0x00, 0x00, 0x02, 0x46, 0x02, 0x88, 121 - 0x88, 0x88, 0x88, 0x88, 0x88, 0x64, 0x88, 0x13, 122 - 0x57, 0x13, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 123 - 0x75, 0x88, 0x23, 0x14, 0x00, 0x00, 0x02, 0x00, 124 - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 125 - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x0A, 126 - 0xA5, 0x00, 0x00, 0x00, 0x00); 127 - mipi_dsi_generic_write_seq(dsi, ST7703_CMD_SETGAMMA, 128 - 0x00, 0x09, 0x0E, 0x29, 0x2D, 0x3C, 0x41, 0x37, 129 - 0x07, 0x0B, 0x0D, 0x10, 0x11, 0x0F, 0x10, 0x11, 130 - 0x18, 0x00, 0x09, 0x0E, 0x29, 0x2D, 0x3C, 0x41, 131 - 0x37, 0x07, 0x0B, 0x0D, 0x10, 0x11, 0x0F, 0x10, 132 - 0x11, 0x18); 133 - msleep(20); 134 - 135 - return 0; 105 + mipi_dsi_generic_write_seq_multi(dsi_ctx, ST7703_CMD_SETVCOM, 0x3F, 0x3F); 106 + mipi_dsi_generic_write_seq_multi(dsi_ctx, ST7703_CMD_UNKNOWN_BF, 0x02, 0x11, 0x00); 107 + mipi_dsi_generic_write_seq_multi(dsi_ctx, ST7703_CMD_SETGIP1, 108 + 0x82, 0x10, 0x06, 0x05, 0x9E, 0x0A, 0xA5, 0x12, 109 + 0x31, 0x23, 0x37, 0x83, 0x04, 0xBC, 0x27, 0x38, 110 + 0x0C, 0x00, 0x03, 0x00, 0x00, 0x00, 0x0C, 0x00, 111 + 0x03, 0x00, 0x00, 0x00, 0x75, 0x75, 0x31, 0x88, 112 + 0x88, 0x88, 0x88, 0x88, 0x88, 0x13, 0x88, 0x64, 113 + 0x64, 0x20, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 114 + 0x02, 0x88, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 115 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00); 116 + mipi_dsi_generic_write_seq_multi(dsi_ctx, ST7703_CMD_SETGIP2, 117 + 0x02, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 118 + 0x00, 0x00, 0x00, 0x00, 0x02, 0x46, 0x02, 0x88, 119 + 0x88, 0x88, 0x88, 0x88, 0x88, 0x64, 0x88, 0x13, 120 + 0x57, 0x13, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 121 + 0x75, 0x88, 0x23, 0x14, 0x00, 0x00, 0x02, 0x00, 122 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 123 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x0A, 124 + 0xA5, 0x00, 0x00, 0x00, 0x00); 125 + mipi_dsi_generic_write_seq_multi(dsi_ctx, ST7703_CMD_SETGAMMA, 126 + 0x00, 0x09, 0x0E, 0x29, 0x2D, 0x3C, 0x41, 0x37, 127 + 0x07, 0x0B, 0x0D, 0x10, 0x11, 0x0F, 0x10, 0x11, 128 + 0x18, 0x00, 0x09, 0x0E, 0x29, 0x2D, 0x3C, 0x41, 129 + 0x37, 0x07, 0x0B, 0x0D, 0x10, 0x11, 0x0F, 0x10, 130 + 0x11, 0x18); 131 + mipi_dsi_msleep(dsi_ctx, 20); 136 132 } 137 133 138 134 static const struct drm_display_mode jh057n00900_mode = { ··· 155 159 .init_sequence = jh057n_init_sequence, 156 160 }; 157 161 158 - static int xbd599_init_sequence(struct st7703 *ctx) 162 + static void xbd599_init_sequence(struct mipi_dsi_multi_context *dsi_ctx) 159 163 { 160 - struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev); 161 - 162 164 /* 163 165 * Init sequence was supplied by the panel vendor. 164 166 */ 165 167 166 168 /* Magic sequence to unlock user commands below. */ 167 - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETEXTC, 0xF1, 0x12, 0x83); 169 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETEXTC, 0xF1, 0x12, 0x83); 168 170 169 - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETMIPI, 170 - 0x33, /* VC_main = 0, Lane_Number = 3 (4 lanes) */ 171 - 0x81, /* DSI_LDO_SEL = 1.7V, RTERM = 90 Ohm */ 172 - 0x05, /* IHSRX = x6 (Low High Speed driving ability) */ 173 - 0xF9, /* TX_CLK_SEL = fDSICLK/16 */ 174 - 0x0E, /* HFP_OSC (min. HFP number in DSI mode) */ 175 - 0x0E, /* HBP_OSC (min. HBP number in DSI mode) */ 176 - /* The rest is undocumented in ST7703 datasheet */ 177 - 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 178 - 0x44, 0x25, 0x00, 0x91, 0x0a, 0x00, 0x00, 0x02, 179 - 0x4F, 0x11, 0x00, 0x00, 0x37); 171 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETMIPI, 172 + 0x33, /* VC_main = 0, Lane_Number = 3 (4 lanes) */ 173 + 0x81, /* DSI_LDO_SEL = 1.7V, RTERM = 90 Ohm */ 174 + 0x05, /* IHSRX = x6 (Low High Speed driving ability) */ 175 + 0xF9, /* TX_CLK_SEL = fDSICLK/16 */ 176 + 0x0E, /* HFP_OSC (min. HFP number in DSI mode) */ 177 + 0x0E, /* HBP_OSC (min. HBP number in DSI mode) */ 178 + /* The rest is undocumented in ST7703 datasheet */ 179 + 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 180 + 0x44, 0x25, 0x00, 0x91, 0x0a, 0x00, 0x00, 0x02, 181 + 0x4F, 0x11, 0x00, 0x00, 0x37); 180 182 181 - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETPOWER_EXT, 182 - 0x25, /* PCCS = 2, ECP_DC_DIV = 1/4 HSYNC */ 183 - 0x22, /* DT = 15ms XDK_ECP = x2 */ 184 - 0x20, /* PFM_DC_DIV = /1 */ 185 - 0x03 /* ECP_SYNC_EN = 1, VGX_SYNC_EN = 1 */); 183 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETPOWER_EXT, 184 + 0x25, /* PCCS = 2, ECP_DC_DIV = 1/4 HSYNC */ 185 + 0x22, /* DT = 15ms XDK_ECP = x2 */ 186 + 0x20, /* PFM_DC_DIV = /1 */ 187 + 0x03 /* ECP_SYNC_EN = 1, VGX_SYNC_EN = 1 */); 186 188 187 189 /* RGB I/F porch timing */ 188 - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETRGBIF, 189 - 0x10, /* VBP_RGB_GEN */ 190 - 0x10, /* VFP_RGB_GEN */ 191 - 0x05, /* DE_BP_RGB_GEN */ 192 - 0x05, /* DE_FP_RGB_GEN */ 193 - /* The rest is undocumented in ST7703 datasheet */ 194 - 0x03, 0xFF, 195 - 0x00, 0x00, 196 - 0x00, 0x00); 190 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETRGBIF, 191 + 0x10, /* VBP_RGB_GEN */ 192 + 0x10, /* VFP_RGB_GEN */ 193 + 0x05, /* DE_BP_RGB_GEN */ 194 + 0x05, /* DE_FP_RGB_GEN */ 195 + /* The rest is undocumented in ST7703 datasheet */ 196 + 0x03, 0xFF, 197 + 0x00, 0x00, 198 + 0x00, 0x00); 197 199 198 200 /* Source driving settings. */ 199 - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETSCR, 200 - 0x73, /* N_POPON */ 201 - 0x73, /* N_NOPON */ 202 - 0x50, /* I_POPON */ 203 - 0x50, /* I_NOPON */ 204 - 0x00, /* SCR[31,24] */ 205 - 0xC0, /* SCR[23,16] */ 206 - 0x08, /* SCR[15,8] */ 207 - 0x70, /* SCR[7,0] */ 208 - 0x00 /* Undocumented */); 201 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETSCR, 202 + 0x73, /* N_POPON */ 203 + 0x73, /* N_NOPON */ 204 + 0x50, /* I_POPON */ 205 + 0x50, /* I_NOPON */ 206 + 0x00, /* SCR[31,24] */ 207 + 0xC0, /* SCR[23,16] */ 208 + 0x08, /* SCR[15,8] */ 209 + 0x70, /* SCR[7,0] */ 210 + 0x00 /* Undocumented */); 209 211 210 212 /* NVDDD_SEL = -1.8V, VDDD_SEL = out of range (possibly 1.9V?) */ 211 - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETVDC, 0x4E); 213 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETVDC, 0x4E); 212 214 213 215 /* 214 216 * SS_PANEL = 1 (reverse scan), GS_PANEL = 0 (normal scan) 215 217 * REV_PANEL = 1 (normally black panel), BGR_PANEL = 1 (BGR) 216 218 */ 217 - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETPANEL, 0x0B); 219 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETPANEL, 0x0B); 218 220 219 221 /* Zig-Zag Type C column inversion. */ 220 - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETCYC, 0x80); 222 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETCYC, 0x80); 221 223 222 224 /* Set display resolution. */ 223 - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETDISP, 224 - 0xF0, /* NL = 240 */ 225 - 0x12, /* RES_V_LSB = 0, BLK_CON = VSSD, 226 - * RESO_SEL = 720RGB 227 - */ 228 - 0xF0 /* WHITE_GND_EN = 1 (GND), 229 - * WHITE_FRAME_SEL = 7 frames, 230 - * ISC = 0 frames 231 - */); 225 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETDISP, 226 + 0xF0, /* NL = 240 */ 227 + 0x12, /* RES_V_LSB = 0, BLK_CON = VSSD, 228 + * RESO_SEL = 720RGB 229 + */ 230 + 0xF0 /* WHITE_GND_EN = 1 (GND), 231 + * WHITE_FRAME_SEL = 7 frames, 232 + * ISC = 0 frames 233 + */); 232 234 233 - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETEQ, 234 - 0x00, /* PNOEQ */ 235 - 0x00, /* NNOEQ */ 236 - 0x0B, /* PEQGND */ 237 - 0x0B, /* NEQGND */ 238 - 0x10, /* PEQVCI */ 239 - 0x10, /* NEQVCI */ 240 - 0x00, /* PEQVCI1 */ 241 - 0x00, /* NEQVCI1 */ 242 - 0x00, /* reserved */ 243 - 0x00, /* reserved */ 244 - 0xFF, /* reserved */ 245 - 0x00, /* reserved */ 246 - 0xC0, /* ESD_DET_DATA_WHITE = 1, ESD_WHITE_EN = 1 */ 247 - 0x10 /* SLPIN_OPTION = 1 (no need vsync after sleep-in) 248 - * VEDIO_NO_CHECK_EN = 0 249 - * ESD_WHITE_GND_EN = 0 250 - * ESD_DET_TIME_SEL = 0 frames 251 - */); 235 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETEQ, 236 + 0x00, /* PNOEQ */ 237 + 0x00, /* NNOEQ */ 238 + 0x0B, /* PEQGND */ 239 + 0x0B, /* NEQGND */ 240 + 0x10, /* PEQVCI */ 241 + 0x10, /* NEQVCI */ 242 + 0x00, /* PEQVCI1 */ 243 + 0x00, /* NEQVCI1 */ 244 + 0x00, /* reserved */ 245 + 0x00, /* reserved */ 246 + 0xFF, /* reserved */ 247 + 0x00, /* reserved */ 248 + 0xC0, /* ESD_DET_DATA_WHITE = 1, ESD_WHITE_EN = 1 */ 249 + 0x10 /* SLPIN_OPTION = 1 (no need vsync after sleep-in) 250 + * VEDIO_NO_CHECK_EN = 0 251 + * ESD_WHITE_GND_EN = 0 252 + * ESD_DET_TIME_SEL = 0 frames 253 + */); 252 254 253 - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETECO, 0x01, 0x00, 0xFF, 0xFF, 0x00); 255 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETECO, 0x01, 0x00, 0xFF, 0xFF, 0x00); 254 256 255 - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETPOWER, 256 - 0x74, /* VBTHS, VBTLS: VGH = 17V, VBL = -11V */ 257 - 0x00, /* FBOFF_VGH = 0, FBOFF_VGL = 0 */ 258 - 0x32, /* VRP */ 259 - 0x32, /* VRN */ 260 - 0x77, /* reserved */ 261 - 0xF1, /* APS = 1 (small), 262 - * VGL_DET_EN = 1, VGH_DET_EN = 1, 263 - * VGL_TURBO = 1, VGH_TURBO = 1 264 - */ 265 - 0xFF, /* VGH1_L_DIV, VGL1_L_DIV (1.5MHz) */ 266 - 0xFF, /* VGH1_R_DIV, VGL1_R_DIV (1.5MHz) */ 267 - 0xCC, /* VGH2_L_DIV, VGL2_L_DIV (2.6MHz) */ 268 - 0xCC, /* VGH2_R_DIV, VGL2_R_DIV (2.6MHz) */ 269 - 0x77, /* VGH3_L_DIV, VGL3_L_DIV (4.5MHz) */ 270 - 0x77 /* VGH3_R_DIV, VGL3_R_DIV (4.5MHz) */); 257 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETPOWER, 258 + 0x74, /* VBTHS, VBTLS: VGH = 17V, VBL = -11V */ 259 + 0x00, /* FBOFF_VGH = 0, FBOFF_VGL = 0 */ 260 + 0x32, /* VRP */ 261 + 0x32, /* VRN */ 262 + 0x77, /* reserved */ 263 + 0xF1, /* APS = 1 (small), 264 + * VGL_DET_EN = 1, VGH_DET_EN = 1, 265 + * VGL_TURBO = 1, VGH_TURBO = 1 266 + */ 267 + 0xFF, /* VGH1_L_DIV, VGL1_L_DIV (1.5MHz) */ 268 + 0xFF, /* VGH1_R_DIV, VGL1_R_DIV (1.5MHz) */ 269 + 0xCC, /* VGH2_L_DIV, VGL2_L_DIV (2.6MHz) */ 270 + 0xCC, /* VGH2_R_DIV, VGL2_R_DIV (2.6MHz) */ 271 + 0x77, /* VGH3_L_DIV, VGL3_L_DIV (4.5MHz) */ 272 + 0x77 /* VGH3_R_DIV, VGL3_R_DIV (4.5MHz) */); 271 273 272 274 /* Reference voltage. */ 273 - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETBGP, 274 - 0x07, /* VREF_SEL = 4.2V */ 275 - 0x07 /* NVREF_SEL = 4.2V */); 275 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETBGP, 276 + 0x07, /* VREF_SEL = 4.2V */ 277 + 0x07 /* NVREF_SEL = 4.2V */); 276 278 277 - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETVCOM, 278 - 0x2C, /* VCOMDC_F = -0.67V */ 279 - 0x2C /* VCOMDC_B = -0.67V */); 279 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETVCOM, 280 + 0x2C, /* VCOMDC_F = -0.67V */ 281 + 0x2C /* VCOMDC_B = -0.67V */); 280 282 281 283 /* Undocumented command. */ 282 - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_UNKNOWN_BF, 0x02, 0x11, 0x00); 284 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_UNKNOWN_BF, 0x02, 0x11, 0x00); 283 285 284 286 /* This command is to set forward GIP timing. */ 285 - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETGIP1, 286 - 0x82, 0x10, 0x06, 0x05, 0xA2, 0x0A, 0xA5, 0x12, 287 - 0x31, 0x23, 0x37, 0x83, 0x04, 0xBC, 0x27, 0x38, 288 - 0x0C, 0x00, 0x03, 0x00, 0x00, 0x00, 0x0C, 0x00, 289 - 0x03, 0x00, 0x00, 0x00, 0x75, 0x75, 0x31, 0x88, 290 - 0x88, 0x88, 0x88, 0x88, 0x88, 0x13, 0x88, 0x64, 291 - 0x64, 0x20, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 292 - 0x02, 0x88, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 293 - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00); 287 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETGIP1, 288 + 0x82, 0x10, 0x06, 0x05, 0xA2, 0x0A, 0xA5, 0x12, 289 + 0x31, 0x23, 0x37, 0x83, 0x04, 0xBC, 0x27, 0x38, 290 + 0x0C, 0x00, 0x03, 0x00, 0x00, 0x00, 0x0C, 0x00, 291 + 0x03, 0x00, 0x00, 0x00, 0x75, 0x75, 0x31, 0x88, 292 + 0x88, 0x88, 0x88, 0x88, 0x88, 0x13, 0x88, 0x64, 293 + 0x64, 0x20, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 294 + 0x02, 0x88, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 295 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00); 294 296 295 297 /* This command is to set backward GIP timing. */ 296 - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETGIP2, 297 - 0x02, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 298 - 0x00, 0x00, 0x00, 0x00, 0x02, 0x46, 0x02, 0x88, 299 - 0x88, 0x88, 0x88, 0x88, 0x88, 0x64, 0x88, 0x13, 300 - 0x57, 0x13, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 301 - 0x75, 0x88, 0x23, 0x14, 0x00, 0x00, 0x02, 0x00, 302 - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 303 - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0A, 304 - 0xA5, 0x00, 0x00, 0x00, 0x00); 298 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETGIP2, 299 + 0x02, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 300 + 0x00, 0x00, 0x00, 0x00, 0x02, 0x46, 0x02, 0x88, 301 + 0x88, 0x88, 0x88, 0x88, 0x88, 0x64, 0x88, 0x13, 302 + 0x57, 0x13, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 303 + 0x75, 0x88, 0x23, 0x14, 0x00, 0x00, 0x02, 0x00, 304 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 305 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0A, 306 + 0xA5, 0x00, 0x00, 0x00, 0x00); 305 307 306 308 /* Adjust the gamma characteristics of the panel. */ 307 - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETGAMMA, 308 - 0x00, 0x09, 0x0D, 0x23, 0x27, 0x3C, 0x41, 0x35, 309 - 0x07, 0x0D, 0x0E, 0x12, 0x13, 0x10, 0x12, 0x12, 310 - 0x18, 0x00, 0x09, 0x0D, 0x23, 0x27, 0x3C, 0x41, 311 - 0x35, 0x07, 0x0D, 0x0E, 0x12, 0x13, 0x10, 0x12, 312 - 0x12, 0x18); 313 - 314 - return 0; 309 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETGAMMA, 310 + 0x00, 0x09, 0x0D, 0x23, 0x27, 0x3C, 0x41, 0x35, 311 + 0x07, 0x0D, 0x0E, 0x12, 0x13, 0x10, 0x12, 0x12, 312 + 0x18, 0x00, 0x09, 0x0D, 0x23, 0x27, 0x3C, 0x41, 313 + 0x35, 0x07, 0x0D, 0x0E, 0x12, 0x13, 0x10, 0x12, 314 + 0x12, 0x18); 315 315 } 316 316 317 317 static const struct drm_display_mode xbd599_mode = { ··· 333 341 .init_sequence = xbd599_init_sequence, 334 342 }; 335 343 336 - static int rg353v2_init_sequence(struct st7703 *ctx) 344 + static void rg353v2_init_sequence(struct mipi_dsi_multi_context *dsi_ctx) 337 345 { 338 - struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev); 339 - 340 346 /* 341 347 * Init sequence was supplied by the panel vendor. 342 348 */ 343 349 344 - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETEXTC, 0xf1, 0x12, 0x83); 345 - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETAPID, 0x00, 0x00, 0x00, 346 - 0xda, 0x80); 347 - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETDISP, 0x00, 0x13, 0x70); 348 - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETRGBIF, 0x10, 0x10, 0x28, 349 - 0x28, 0x03, 0xff, 0x00, 0x00, 0x00, 0x00); 350 - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETCYC, 0x80); 351 - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETBGP, 0x0a, 0x0a); 352 - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETVCOM, 0x92, 0x92); 353 - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETPOWER_EXT, 0x25, 0x22, 354 - 0xf0, 0x63); 355 - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETMIPI, 0x33, 0x81, 0x05, 356 - 0xf9, 0x0e, 0x0e, 0x20, 0x00, 0x00, 0x00, 0x00, 357 - 0x00, 0x00, 0x00, 0x44, 0x25, 0x00, 0x90, 0x0a, 358 - 0x00, 0x00, 0x01, 0x4f, 0x01, 0x00, 0x00, 0x37); 359 - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETVDC, 0x47); 360 - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_UNKNOWN_BF, 0x02, 0x11, 0x00); 361 - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETSCR, 0x73, 0x73, 0x50, 0x50, 362 - 0x00, 0x00, 0x12, 0x50, 0x00); 363 - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETPOWER, 0x53, 0xc0, 0x32, 364 - 0x32, 0x77, 0xe1, 0xdd, 0xdd, 0x77, 0x77, 0x33, 365 - 0x33); 366 - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETECO, 0x82, 0x00, 0xbf, 0xff, 367 - 0x00, 0xff); 368 - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETIO, 0xb8, 0x00, 0x0a, 0x00, 369 - 0x00, 0x00); 370 - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETCABC, 0x10, 0x40, 0x1e, 371 - 0x02); 372 - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETPANEL, 0x0b); 373 - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETGAMMA, 0x00, 0x07, 0x0d, 374 - 0x37, 0x35, 0x3f, 0x41, 0x44, 0x06, 0x0c, 0x0d, 375 - 0x0f, 0x11, 0x10, 0x12, 0x14, 0x1a, 0x00, 0x07, 376 - 0x0d, 0x37, 0x35, 0x3f, 0x41, 0x44, 0x06, 0x0c, 377 - 0x0d, 0x0f, 0x11, 0x10, 0x12, 0x14, 0x1a); 378 - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETEQ, 0x07, 0x07, 0x0b, 0x0b, 379 - 0x0b, 0x0b, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 380 - 0xc0, 0x10); 381 - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETGIP1, 0xc8, 0x10, 0x02, 0x00, 382 - 0x00, 0xb0, 0xb1, 0x11, 0x31, 0x23, 0x28, 0x80, 383 - 0xb0, 0xb1, 0x27, 0x08, 0x00, 0x04, 0x02, 0x00, 384 - 0x00, 0x00, 0x00, 0x04, 0x02, 0x00, 0x00, 0x00, 385 - 0x88, 0x88, 0xba, 0x60, 0x24, 0x08, 0x88, 0x88, 386 - 0x88, 0x88, 0x88, 0x88, 0x88, 0xba, 0x71, 0x35, 387 - 0x18, 0x88, 0x88, 0x88, 0x88, 0x88, 0x00, 0x00, 388 - 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 389 - 0x00, 0x00, 0x00); 390 - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETGIP2, 0x97, 0x0a, 0x82, 0x02, 391 - 0x03, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 392 - 0x81, 0x88, 0xba, 0x17, 0x53, 0x88, 0x88, 0x88, 393 - 0x88, 0x88, 0x88, 0x80, 0x88, 0xba, 0x06, 0x42, 394 - 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x23, 0x00, 395 - 0x00, 0x02, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 396 - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 397 - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 398 - 0x00); 399 - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_UNKNOWN_EF, 0xff, 0xff, 0x01); 400 - 401 - return 0; 350 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETEXTC, 0xf1, 0x12, 0x83); 351 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETAPID, 0x00, 0x00, 0x00, 352 + 0xda, 0x80); 353 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETDISP, 0x00, 0x13, 0x70); 354 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETRGBIF, 0x10, 0x10, 0x28, 355 + 0x28, 0x03, 0xff, 0x00, 0x00, 0x00, 0x00); 356 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETCYC, 0x80); 357 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETBGP, 0x0a, 0x0a); 358 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETVCOM, 0x92, 0x92); 359 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETPOWER_EXT, 0x25, 0x22, 360 + 0xf0, 0x63); 361 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETMIPI, 0x33, 0x81, 0x05, 362 + 0xf9, 0x0e, 0x0e, 0x20, 0x00, 0x00, 0x00, 0x00, 363 + 0x00, 0x00, 0x00, 0x44, 0x25, 0x00, 0x90, 0x0a, 364 + 0x00, 0x00, 0x01, 0x4f, 0x01, 0x00, 0x00, 0x37); 365 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETVDC, 0x47); 366 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_UNKNOWN_BF, 0x02, 0x11, 0x00); 367 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETSCR, 0x73, 0x73, 0x50, 0x50, 368 + 0x00, 0x00, 0x12, 0x50, 0x00); 369 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETPOWER, 0x53, 0xc0, 0x32, 370 + 0x32, 0x77, 0xe1, 0xdd, 0xdd, 0x77, 0x77, 0x33, 371 + 0x33); 372 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETECO, 0x82, 0x00, 0xbf, 0xff, 373 + 0x00, 0xff); 374 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETIO, 0xb8, 0x00, 0x0a, 0x00, 375 + 0x00, 0x00); 376 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETCABC, 0x10, 0x40, 0x1e, 377 + 0x02); 378 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETPANEL, 0x0b); 379 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETGAMMA, 0x00, 0x07, 0x0d, 380 + 0x37, 0x35, 0x3f, 0x41, 0x44, 0x06, 0x0c, 0x0d, 381 + 0x0f, 0x11, 0x10, 0x12, 0x14, 0x1a, 0x00, 0x07, 382 + 0x0d, 0x37, 0x35, 0x3f, 0x41, 0x44, 0x06, 0x0c, 383 + 0x0d, 0x0f, 0x11, 0x10, 0x12, 0x14, 0x1a); 384 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETEQ, 0x07, 0x07, 0x0b, 0x0b, 385 + 0x0b, 0x0b, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 386 + 0xc0, 0x10); 387 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETGIP1, 0xc8, 0x10, 0x02, 0x00, 388 + 0x00, 0xb0, 0xb1, 0x11, 0x31, 0x23, 0x28, 0x80, 389 + 0xb0, 0xb1, 0x27, 0x08, 0x00, 0x04, 0x02, 0x00, 390 + 0x00, 0x00, 0x00, 0x04, 0x02, 0x00, 0x00, 0x00, 391 + 0x88, 0x88, 0xba, 0x60, 0x24, 0x08, 0x88, 0x88, 392 + 0x88, 0x88, 0x88, 0x88, 0x88, 0xba, 0x71, 0x35, 393 + 0x18, 0x88, 0x88, 0x88, 0x88, 0x88, 0x00, 0x00, 394 + 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 395 + 0x00, 0x00, 0x00); 396 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETGIP2, 0x97, 0x0a, 0x82, 0x02, 397 + 0x03, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 398 + 0x81, 0x88, 0xba, 0x17, 0x53, 0x88, 0x88, 0x88, 399 + 0x88, 0x88, 0x88, 0x80, 0x88, 0xba, 0x06, 0x42, 400 + 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x23, 0x00, 401 + 0x00, 0x02, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 402 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 403 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 404 + 0x00); 405 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_UNKNOWN_EF, 0xff, 0xff, 0x01); 402 406 } 403 407 404 408 static const struct drm_display_mode rg353v2_mode = { ··· 421 433 .init_sequence = rg353v2_init_sequence, 422 434 }; 423 435 424 - static int rgb30panel_init_sequence(struct st7703 *ctx) 436 + static void rgb30panel_init_sequence(struct mipi_dsi_multi_context *dsi_ctx) 425 437 { 426 - struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev); 427 - 428 438 /* Init sequence extracted from Powkiddy RGB30 BSP kernel. */ 429 439 430 440 /* 431 441 * For some reason this specific panel must be taken out of sleep 432 442 * before the full init sequence, or else it will not display. 433 443 */ 434 - mipi_dsi_dcs_exit_sleep_mode(dsi); 435 - msleep(250); 444 + mipi_dsi_dcs_exit_sleep_mode_multi(dsi_ctx); 445 + mipi_dsi_msleep(dsi_ctx, 250); 436 446 437 - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETEXTC, 0xf1, 0x12, 0x83); 438 - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETMIPI, 0x33, 0x81, 0x05, 0xf9, 439 - 0x0e, 0x0e, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 440 - 0x00, 0x00, 0x44, 0x25, 0x00, 0x90, 0x0a, 0x00, 441 - 0x00, 0x01, 0x4f, 0x01, 0x00, 0x00, 0x37); 442 - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETPOWER_EXT, 0x25, 0x22, 0xf0, 443 - 0x63); 444 - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_UNKNOWN_BF, 0x02, 0x11, 0x00); 445 - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETRGBIF, 0x10, 0x10, 0x28, 446 - 0x28, 0x03, 0xff, 0x00, 0x00, 0x00, 0x00); 447 - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETSCR, 0x73, 0x73, 0x50, 0x50, 448 - 0x00, 0x00, 0x12, 0x70, 0x00); 449 - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETVDC, 0x46); 450 - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETPANEL, 0x0b); 451 - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETCYC, 0x80); 452 - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETDISP, 0x3c, 0x12, 0x30); 453 - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETEQ, 0x07, 0x07, 0x0b, 0x0b, 454 - 0x03, 0x0b, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 455 - 0xc0, 0x10); 456 - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETPOWER, 0x36, 0x00, 0x32, 457 - 0x32, 0x77, 0xf1, 0xcc, 0xcc, 0x77, 0x77, 0x33, 458 - 0x33); 459 - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETBGP, 0x0a, 0x0a); 460 - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETVCOM, 0x88, 0x88); 461 - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETGIP1, 0xc8, 0x10, 0x0a, 0x10, 462 - 0x0f, 0xa1, 0x80, 0x12, 0x31, 0x23, 0x47, 0x86, 463 - 0xa1, 0x80, 0x47, 0x08, 0x00, 0x00, 0x0d, 0x00, 464 - 0x00, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x00, 0x00, 465 - 0x48, 0x02, 0x8b, 0xaf, 0x46, 0x02, 0x88, 0x88, 466 - 0x88, 0x88, 0x88, 0x48, 0x13, 0x8b, 0xaf, 0x57, 467 - 0x13, 0x88, 0x88, 0x88, 0x88, 0x88, 0x00, 0x00, 468 - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 469 - 0x00, 0x00, 0x00); 470 - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETGIP2, 0x96, 0x12, 0x01, 0x01, 471 - 0x01, 0x78, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 472 - 0x4f, 0x31, 0x8b, 0xa8, 0x31, 0x75, 0x88, 0x88, 473 - 0x88, 0x88, 0x88, 0x4f, 0x20, 0x8b, 0xa8, 0x20, 474 - 0x64, 0x88, 0x88, 0x88, 0x88, 0x88, 0x23, 0x00, 475 - 0x00, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 476 - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 477 - 0x00, 0x00, 0x40, 0xa1, 0x80, 0x00, 0x00, 0x00, 478 - 0x00); 479 - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETGAMMA, 0x00, 0x0a, 0x0f, 480 - 0x29, 0x3b, 0x3f, 0x42, 0x39, 0x06, 0x0d, 0x10, 481 - 0x13, 0x15, 0x14, 0x15, 0x10, 0x17, 0x00, 0x0a, 482 - 0x0f, 0x29, 0x3b, 0x3f, 0x42, 0x39, 0x06, 0x0d, 483 - 0x10, 0x13, 0x15, 0x14, 0x15, 0x10, 0x17); 484 - 485 - return 0; 447 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETEXTC, 0xf1, 0x12, 0x83); 448 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETMIPI, 0x33, 0x81, 0x05, 0xf9, 449 + 0x0e, 0x0e, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 450 + 0x00, 0x00, 0x44, 0x25, 0x00, 0x90, 0x0a, 0x00, 451 + 0x00, 0x01, 0x4f, 0x01, 0x00, 0x00, 0x37); 452 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETPOWER_EXT, 0x25, 0x22, 0xf0, 453 + 0x63); 454 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_UNKNOWN_BF, 0x02, 0x11, 0x00); 455 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETRGBIF, 0x10, 0x10, 0x28, 456 + 0x28, 0x03, 0xff, 0x00, 0x00, 0x00, 0x00); 457 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETSCR, 0x73, 0x73, 0x50, 0x50, 458 + 0x00, 0x00, 0x12, 0x70, 0x00); 459 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETVDC, 0x46); 460 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETPANEL, 0x0b); 461 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETCYC, 0x80); 462 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETDISP, 0x3c, 0x12, 0x30); 463 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETEQ, 0x07, 0x07, 0x0b, 0x0b, 464 + 0x03, 0x0b, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 465 + 0xc0, 0x10); 466 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETPOWER, 0x36, 0x00, 0x32, 467 + 0x32, 0x77, 0xf1, 0xcc, 0xcc, 0x77, 0x77, 0x33, 468 + 0x33); 469 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETBGP, 0x0a, 0x0a); 470 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETVCOM, 0x88, 0x88); 471 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETGIP1, 0xc8, 0x10, 0x0a, 0x10, 472 + 0x0f, 0xa1, 0x80, 0x12, 0x31, 0x23, 0x47, 0x86, 473 + 0xa1, 0x80, 0x47, 0x08, 0x00, 0x00, 0x0d, 0x00, 474 + 0x00, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x00, 0x00, 475 + 0x48, 0x02, 0x8b, 0xaf, 0x46, 0x02, 0x88, 0x88, 476 + 0x88, 0x88, 0x88, 0x48, 0x13, 0x8b, 0xaf, 0x57, 477 + 0x13, 0x88, 0x88, 0x88, 0x88, 0x88, 0x00, 0x00, 478 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 479 + 0x00, 0x00, 0x00); 480 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETGIP2, 0x96, 0x12, 0x01, 0x01, 481 + 0x01, 0x78, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 482 + 0x4f, 0x31, 0x8b, 0xa8, 0x31, 0x75, 0x88, 0x88, 483 + 0x88, 0x88, 0x88, 0x4f, 0x20, 0x8b, 0xa8, 0x20, 484 + 0x64, 0x88, 0x88, 0x88, 0x88, 0x88, 0x23, 0x00, 485 + 0x00, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 486 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 487 + 0x00, 0x00, 0x40, 0xa1, 0x80, 0x00, 0x00, 0x00, 488 + 0x00); 489 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETGAMMA, 0x00, 0x0a, 0x0f, 490 + 0x29, 0x3b, 0x3f, 0x42, 0x39, 0x06, 0x0d, 0x10, 491 + 0x13, 0x15, 0x14, 0x15, 0x10, 0x17, 0x00, 0x0a, 492 + 0x0f, 0x29, 0x3b, 0x3f, 0x42, 0x39, 0x06, 0x0d, 493 + 0x10, 0x13, 0x15, 0x14, 0x15, 0x10, 0x17); 486 494 } 487 495 488 496 static const struct drm_display_mode rgb30panel_mode = { ··· 505 521 .init_sequence = rgb30panel_init_sequence, 506 522 }; 507 523 508 - static int rgb10max3_panel_init_sequence(struct st7703 *ctx) 524 + static void rgb10max3_panel_init_sequence(struct mipi_dsi_multi_context *dsi_ctx) 509 525 { 510 - struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev); 511 - 512 526 /* Init sequence extracted from Powkiddy RGB10MAX3 BSP kernel. */ 513 527 514 - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETEXTC, 0xf1, 0x12, 0x83); 515 - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETAPID, 0x00, 0x00, 0x00, 0xda, 516 - 0x80); 517 - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETDISP, 0xc8, 0x02, 0x30); 518 - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETRGBIF, 0x10, 0x10, 0x28, 519 - 0x28, 0x03, 0xff, 0x00, 0x00, 0x00, 0x00); 520 - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETCYC, 0x80); 521 - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETBGP, 0x04, 0x04); 522 - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETVCOM, 0x78, 0x78); 523 - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETPOWER_EXT, 0x25, 0x22, 0xf0, 524 - 0x63); 525 - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETMIPI, 0x33, 0x81, 0x05, 0xf9, 526 - 0x0e, 0x0e, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 527 - 0x00, 0x00, 0x44, 0x25, 0x00, 0x90, 0x0a, 0x00, 528 - 0x00, 0x01, 0x4f, 0x01, 0x00, 0x00, 0x37); 529 - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETVDC, 0x47); 530 - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_UNKNOWN_BF, 0x02, 0x11, 0x00); 531 - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETSCR, 0x73, 0x73, 0x50, 0x50, 532 - 0x00, 0x00, 0x12, 0x70, 0x00); 533 - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETPOWER, 0x25, 0x00, 0x32, 534 - 0x32, 0x77, 0xe1, 0xff, 0xff, 0xcc, 0xcc, 0x77, 535 - 0x77); 536 - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETECO, 0x82, 0x00, 0xbf, 0xff, 537 - 0x00, 0xff); 538 - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETIO, 0xb8, 0x00, 0x0a, 0x00, 539 - 0x00, 0x00); 540 - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETCABC, 0x10, 0x40, 0x1e, 541 - 0x02); 542 - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETPANEL, 0x0b); 543 - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETGAMMA, 0x00, 0x04, 0x07, 544 - 0x2a, 0x39, 0x3f, 0x36, 0x31, 0x06, 0x0b, 0x0e, 545 - 0x12, 0x14, 0x12, 0x13, 0x0f, 0x17, 0x00, 0x04, 546 - 0x07, 0x2a, 0x39, 0x3f, 0x36, 0x31, 0x06, 0x0b, 547 - 0x0e, 0x12, 0x14, 0x12, 0x13, 0x0f, 0x17); 548 - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETEQ, 0x03, 0x03, 0x03, 0x03, 549 - 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0xff, 0x80, 550 - 0xc0, 0x10); 551 - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETGIP1, 0xc8, 0x10, 0x08, 0x00, 552 - 0x00, 0x41, 0xf8, 0x12, 0x31, 0x23, 0x37, 0x86, 553 - 0x11, 0xc8, 0x37, 0x2a, 0x00, 0x00, 0x0c, 0x00, 554 - 0x00, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x00, 555 - 0x88, 0x20, 0x46, 0x02, 0x88, 0x88, 0x88, 0x88, 556 - 0x88, 0x88, 0xff, 0x88, 0x31, 0x57, 0x13, 0x88, 557 - 0x88, 0x88, 0x88, 0x88, 0x88, 0xff, 0x00, 0x00, 558 - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 559 - 0x00, 0x00, 0x00); 560 - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETGIP2, 0x00, 0x1a, 0x00, 0x00, 561 - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 562 - 0x8f, 0x13, 0x31, 0x75, 0x88, 0x88, 0x88, 0x88, 563 - 0x88, 0x88, 0xf8, 0x8f, 0x02, 0x20, 0x64, 0x88, 564 - 0x88, 0x88, 0x88, 0x88, 0x88, 0xf8, 0x00, 0x00, 565 - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 566 - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 567 - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 568 - 0x00); 569 - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_UNKNOWN_EF, 0xff, 0xff, 0x01); 570 - 571 - return 0; 528 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETEXTC, 0xf1, 0x12, 0x83); 529 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETAPID, 0x00, 0x00, 0x00, 0xda, 530 + 0x80); 531 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETDISP, 0xc8, 0x02, 0x30); 532 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETRGBIF, 0x10, 0x10, 0x28, 533 + 0x28, 0x03, 0xff, 0x00, 0x00, 0x00, 0x00); 534 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETCYC, 0x80); 535 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETBGP, 0x04, 0x04); 536 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETVCOM, 0x78, 0x78); 537 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETPOWER_EXT, 0x25, 0x22, 0xf0, 538 + 0x63); 539 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETMIPI, 0x33, 0x81, 0x05, 0xf9, 540 + 0x0e, 0x0e, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 541 + 0x00, 0x00, 0x44, 0x25, 0x00, 0x90, 0x0a, 0x00, 542 + 0x00, 0x01, 0x4f, 0x01, 0x00, 0x00, 0x37); 543 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETVDC, 0x47); 544 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_UNKNOWN_BF, 0x02, 0x11, 0x00); 545 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETSCR, 0x73, 0x73, 0x50, 0x50, 546 + 0x00, 0x00, 0x12, 0x70, 0x00); 547 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETPOWER, 0x25, 0x00, 0x32, 548 + 0x32, 0x77, 0xe1, 0xff, 0xff, 0xcc, 0xcc, 0x77, 549 + 0x77); 550 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETECO, 0x82, 0x00, 0xbf, 0xff, 551 + 0x00, 0xff); 552 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETIO, 0xb8, 0x00, 0x0a, 0x00, 553 + 0x00, 0x00); 554 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETCABC, 0x10, 0x40, 0x1e, 555 + 0x02); 556 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETPANEL, 0x0b); 557 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETGAMMA, 0x00, 0x04, 0x07, 558 + 0x2a, 0x39, 0x3f, 0x36, 0x31, 0x06, 0x0b, 0x0e, 559 + 0x12, 0x14, 0x12, 0x13, 0x0f, 0x17, 0x00, 0x04, 560 + 0x07, 0x2a, 0x39, 0x3f, 0x36, 0x31, 0x06, 0x0b, 561 + 0x0e, 0x12, 0x14, 0x12, 0x13, 0x0f, 0x17); 562 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETEQ, 0x03, 0x03, 0x03, 0x03, 563 + 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0xff, 0x80, 564 + 0xc0, 0x10); 565 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETGIP1, 0xc8, 0x10, 0x08, 0x00, 566 + 0x00, 0x41, 0xf8, 0x12, 0x31, 0x23, 0x37, 0x86, 567 + 0x11, 0xc8, 0x37, 0x2a, 0x00, 0x00, 0x0c, 0x00, 568 + 0x00, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x00, 569 + 0x88, 0x20, 0x46, 0x02, 0x88, 0x88, 0x88, 0x88, 570 + 0x88, 0x88, 0xff, 0x88, 0x31, 0x57, 0x13, 0x88, 571 + 0x88, 0x88, 0x88, 0x88, 0x88, 0xff, 0x00, 0x00, 572 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 573 + 0x00, 0x00, 0x00); 574 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETGIP2, 0x00, 0x1a, 0x00, 0x00, 575 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 576 + 0x8f, 0x13, 0x31, 0x75, 0x88, 0x88, 0x88, 0x88, 577 + 0x88, 0x88, 0xf8, 0x8f, 0x02, 0x20, 0x64, 0x88, 578 + 0x88, 0x88, 0x88, 0x88, 0x88, 0xf8, 0x00, 0x00, 579 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 580 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 581 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 582 + 0x00); 583 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_UNKNOWN_EF, 0xff, 0xff, 0x01); 572 584 } 573 585 574 586 static const struct drm_display_mode rgb10max3_panel_mode = { ··· 591 611 .init_sequence = rgb10max3_panel_init_sequence, 592 612 }; 593 613 594 - static int gameforcechi_init_sequence(struct st7703 *ctx) 614 + static void gameforcechi_init_sequence(struct mipi_dsi_multi_context *dsi_ctx) 595 615 { 596 - struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev); 597 - 598 616 /* 599 617 * Init sequence was supplied by the panel vendor. Panel will not 600 618 * respond to commands until it is brought out of sleep mode first. 601 619 */ 602 620 603 - mipi_dsi_dcs_exit_sleep_mode(dsi); 604 - msleep(250); 621 + mipi_dsi_dcs_exit_sleep_mode_multi(dsi_ctx); 622 + mipi_dsi_msleep(dsi_ctx, 250); 605 623 606 - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETEXTC, 0xf1, 0x12, 0x83); 607 - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETMIPI, 0x31, 0x81, 0x05, 0xf9, 608 - 0x0e, 0x0e, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 609 - 0x00, 0x00, 0x44, 0x25, 0x00, 0x91, 0x0a, 0x00, 610 - 0x00, 0x02, 0x4f, 0xd1, 0x00, 0x00, 0x37); 611 - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETPOWER_EXT, 0x25); 612 - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_UNKNOWN_BF, 0x02, 0x11, 0x00); 613 - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETRGBIF, 0x0c, 0x10, 0x0a, 614 - 0x50, 0x03, 0xff, 0x00, 0x00, 0x00, 0x00); 615 - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETSCR, 0x73, 0x73, 0x50, 0x50, 616 - 0x00, 0x00, 0x08, 0x70, 0x00); 617 - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETVDC, 0x46); 618 - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETPANEL, 0x0b); 619 - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETCYC, 0x80); 620 - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETDISP, 0x00, 0x13, 0xf0); 621 - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETEQ, 0x07, 0x07, 0x0b, 0x0b, 622 - 0x03, 0x0b, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 623 - 0xc0, 0x10); 624 - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETPOWER, 0x53, 0x00, 0x1e, 625 - 0x1e, 0x77, 0xe1, 0xcc, 0xdd, 0x67, 0x77, 0x33, 626 - 0x33); 627 - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETBGP, 0x10, 0x10); 628 - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETVCOM, 0x6c, 0x7c); 629 - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETGIP1, 0x08, 0x00, 0x0e, 0x00, 630 - 0x00, 0xb0, 0xb1, 0x11, 0x31, 0x23, 0x28, 0x10, 631 - 0xb0, 0xb1, 0x27, 0x08, 0x00, 0x04, 0x02, 0x00, 632 - 0x00, 0x00, 0x00, 0x04, 0x02, 0x00, 0x00, 0x00, 633 - 0x88, 0x88, 0xba, 0x60, 0x24, 0x08, 0x88, 0x88, 634 - 0x88, 0x88, 0x88, 0x88, 0x88, 0xba, 0x71, 0x35, 635 - 0x18, 0x88, 0x88, 0x88, 0x88, 0x88, 0x00, 0x00, 636 - 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 637 - 0x00, 0x00, 0x00); 638 - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETGIP2, 0x97, 0x0a, 0x82, 0x02, 639 - 0x13, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 640 - 0x80, 0x88, 0xba, 0x17, 0x53, 0x88, 0x88, 0x88, 641 - 0x88, 0x88, 0x88, 0x81, 0x88, 0xba, 0x06, 0x42, 642 - 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x23, 0x10, 643 - 0x00, 0x02, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 644 - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 645 - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 646 - 0x00); 647 - mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETGAMMA, 0x00, 0x07, 0x0b, 648 - 0x27, 0x2d, 0x3f, 0x3b, 0x37, 0x05, 0x0a, 0x0b, 649 - 0x0f, 0x11, 0x0f, 0x12, 0x12, 0x18, 0x00, 0x07, 650 - 0x0b, 0x27, 0x2d, 0x3f, 0x3b, 0x37, 0x05, 0xa0, 651 - 0x0b, 0x0f, 0x11, 0x0f, 0x12, 0x12, 0x18); 652 - 653 - return 0; 624 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETEXTC, 0xf1, 0x12, 0x83); 625 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETMIPI, 0x31, 0x81, 0x05, 0xf9, 626 + 0x0e, 0x0e, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 627 + 0x00, 0x00, 0x44, 0x25, 0x00, 0x91, 0x0a, 0x00, 628 + 0x00, 0x02, 0x4f, 0xd1, 0x00, 0x00, 0x37); 629 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETPOWER_EXT, 0x25); 630 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_UNKNOWN_BF, 0x02, 0x11, 0x00); 631 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETRGBIF, 0x0c, 0x10, 0x0a, 632 + 0x50, 0x03, 0xff, 0x00, 0x00, 0x00, 0x00); 633 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETSCR, 0x73, 0x73, 0x50, 0x50, 634 + 0x00, 0x00, 0x08, 0x70, 0x00); 635 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETVDC, 0x46); 636 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETPANEL, 0x0b); 637 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETCYC, 0x80); 638 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETDISP, 0x00, 0x13, 0xf0); 639 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETEQ, 0x07, 0x07, 0x0b, 0x0b, 640 + 0x03, 0x0b, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 641 + 0xc0, 0x10); 642 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETPOWER, 0x53, 0x00, 0x1e, 643 + 0x1e, 0x77, 0xe1, 0xcc, 0xdd, 0x67, 0x77, 0x33, 644 + 0x33); 645 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETBGP, 0x10, 0x10); 646 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETVCOM, 0x6c, 0x7c); 647 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETGIP1, 0x08, 0x00, 0x0e, 0x00, 648 + 0x00, 0xb0, 0xb1, 0x11, 0x31, 0x23, 0x28, 0x10, 649 + 0xb0, 0xb1, 0x27, 0x08, 0x00, 0x04, 0x02, 0x00, 650 + 0x00, 0x00, 0x00, 0x04, 0x02, 0x00, 0x00, 0x00, 651 + 0x88, 0x88, 0xba, 0x60, 0x24, 0x08, 0x88, 0x88, 652 + 0x88, 0x88, 0x88, 0x88, 0x88, 0xba, 0x71, 0x35, 653 + 0x18, 0x88, 0x88, 0x88, 0x88, 0x88, 0x00, 0x00, 654 + 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 655 + 0x00, 0x00, 0x00); 656 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETGIP2, 0x97, 0x0a, 0x82, 0x02, 657 + 0x13, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 658 + 0x80, 0x88, 0xba, 0x17, 0x53, 0x88, 0x88, 0x88, 659 + 0x88, 0x88, 0x88, 0x81, 0x88, 0xba, 0x06, 0x42, 660 + 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x23, 0x10, 661 + 0x00, 0x02, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 662 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 663 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 664 + 0x00); 665 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETGAMMA, 0x00, 0x07, 0x0b, 666 + 0x27, 0x2d, 0x3f, 0x3b, 0x37, 0x05, 0x0a, 0x0b, 667 + 0x0f, 0x11, 0x0f, 0x12, 0x12, 0x18, 0x00, 0x07, 668 + 0x0b, 0x27, 0x2d, 0x3f, 0x3b, 0x37, 0x05, 0xa0, 669 + 0x0b, 0x0f, 0x11, 0x0f, 0x12, 0x12, 0x18); 654 670 } 655 671 656 672 static const struct drm_display_mode gameforcechi_mode = { ··· 677 701 { 678 702 struct st7703 *ctx = panel_to_st7703(panel); 679 703 struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev); 680 - int ret; 704 + struct mipi_dsi_multi_context dsi_ctx = {.dsi = dsi}; 681 705 682 - ret = ctx->desc->init_sequence(ctx); 683 - if (ret < 0) { 684 - dev_err(ctx->dev, "Panel init sequence failed: %d\n", ret); 685 - return ret; 686 - } 706 + ctx->desc->init_sequence(&dsi_ctx); 687 707 688 - ret = mipi_dsi_dcs_exit_sleep_mode(dsi); 689 - if (ret < 0) { 690 - dev_err(ctx->dev, "Failed to exit sleep mode: %d\n", ret); 691 - return ret; 692 - } 708 + mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx); 693 709 694 710 /* It takes the controller 120 msec to wake up after sleep. */ 695 - msleep(120); 711 + mipi_dsi_msleep(&dsi_ctx, 120); 696 712 697 - ret = mipi_dsi_dcs_set_display_on(dsi); 698 - if (ret) 699 - return ret; 713 + mipi_dsi_dcs_set_display_on_multi(&dsi_ctx); 700 714 701 - dev_dbg(ctx->dev, "Panel init sequence done\n"); 715 + if (!dsi_ctx.accum_err) 716 + dev_dbg(ctx->dev, "Panel init sequence done\n"); 702 717 703 - return 0; 718 + return dsi_ctx.accum_err; 704 719 } 705 720 706 721 static int st7703_disable(struct drm_panel *panel) 707 722 { 708 723 struct st7703 *ctx = panel_to_st7703(panel); 709 724 struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev); 710 - int ret; 725 + struct mipi_dsi_multi_context dsi_ctx = {.dsi = dsi}; 711 726 712 - ret = mipi_dsi_dcs_set_display_off(dsi); 713 - if (ret < 0) 714 - dev_err(ctx->dev, "Failed to turn off the display: %d\n", ret); 727 + mipi_dsi_dcs_set_display_off_multi(&dsi_ctx); 715 728 716 - ret = mipi_dsi_dcs_enter_sleep_mode(dsi); 717 - if (ret < 0) 718 - dev_err(ctx->dev, "Failed to enter sleep mode: %d\n", ret); 729 + mipi_dsi_dcs_enter_sleep_mode_multi(&dsi_ctx); 719 730 720 731 /* It takes the controller 120 msec to enter sleep mode. */ 721 - msleep(120); 732 + mipi_dsi_msleep(&dsi_ctx, 120); 722 733 723 - return 0; 734 + return dsi_ctx.accum_err; 724 735 } 725 736 726 737 static int st7703_unprepare(struct drm_panel *panel) ··· 803 840 { 804 841 struct st7703 *ctx = data; 805 842 struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev); 843 + struct mipi_dsi_multi_context dsi_ctx = {.dsi = dsi}; 806 844 807 845 dev_dbg(ctx->dev, "Setting all pixels on\n"); 808 - mipi_dsi_generic_write_seq(dsi, ST7703_CMD_ALL_PIXEL_ON); 809 - msleep(val * 1000); 846 + mipi_dsi_generic_write_seq_multi(&dsi_ctx, ST7703_CMD_ALL_PIXEL_ON); 847 + mipi_dsi_msleep(&dsi_ctx, val * 1000); 810 848 811 849 /* 812 850 * Reset the panel to get video back. NOTE: This isn't a ··· 820 856 drm_panel_prepare(&ctx->panel); 821 857 drm_panel_enable(&ctx->panel); 822 858 823 - return 0; 859 + return dsi_ctx.accum_err; 824 860 } 825 861 826 862 DEFINE_SIMPLE_ATTRIBUTE(allpixelson_fops, NULL,