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Merge patch series "ufs: host: ufs-qcom: Add support for SM8550"

Abel Vesa <abel.vesa@linaro.org> says:

This patchset adds UFS HC support for the new Qualcomm SM8550 SoC.

Link: https://lore.kernel.org/r/20230119151406.4168685-1-abel.vesa@linaro.org
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>

Martin K. Petersen 67e6216d 49f262bc

+13 -3
+2
Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
··· 33 33 - qcom,sm8250-ufshc 34 34 - qcom,sm8350-ufshc 35 35 - qcom,sm8450-ufshc 36 + - qcom,sm8550-ufshc 36 37 - const: qcom,ufshc 37 38 - const: jedec,ufs-2.0 38 39 ··· 106 105 - qcom,sm8250-ufshc 107 106 - qcom,sm8350-ufshc 108 107 - qcom,sm8450-ufshc 108 + - qcom,sm8550-ufshc 109 109 then: 110 110 properties: 111 111 clocks:
+6 -2
drivers/ufs/host/ufs-qcom.c
··· 224 224 ufshcd_rmwl(host->hba, QUNIPRO_SEL, 225 225 ufs_qcom_cap_qunipro(host) ? QUNIPRO_SEL : 0, 226 226 REG_UFS_CFG1); 227 + 228 + if (host->hw_ver.major == 0x05) 229 + ufshcd_rmwl(host->hba, QUNIPRO_G4_SEL, 0, REG_UFS_CFG0); 230 + 227 231 /* make sure above configuration is applied before we return */ 228 232 mb(); 229 233 } ··· 517 513 mb(); 518 514 } 519 515 520 - if (update_link_startup_timer) { 516 + if (update_link_startup_timer && host->hw_ver.major != 0x5) { 521 517 ufshcd_writel(hba, ((core_clk_rate / MSEC_PER_SEC) * 100), 522 - REG_UFS_PA_LINK_STARTUP_TIMER); 518 + REG_UFS_CFG0); 523 519 /* 524 520 * make sure that this configuration is applied before 525 521 * we return
+5 -1
drivers/ufs/host/ufs-qcom.h
··· 36 36 REG_UFS_PA_ERR_CODE = 0xCC, 37 37 /* On older UFS revisions, this register is called "RETRY_TIMER_REG" */ 38 38 REG_UFS_PARAM0 = 0xD0, 39 - REG_UFS_PA_LINK_STARTUP_TIMER = 0xD8, 39 + /* On older UFS revisions, this register is called "REG_UFS_PA_LINK_STARTUP_TIMER" */ 40 + REG_UFS_CFG0 = 0xD8, 40 41 REG_UFS_CFG1 = 0xDC, 41 42 REG_UFS_CFG2 = 0xE0, 42 43 REG_UFS_HW_VERSION = 0xE4, ··· 80 79 81 80 #define UFS_CNTLR_2_x_x_VEN_REGS_OFFSET(x) (0x000 + x) 82 81 #define UFS_CNTLR_3_x_x_VEN_REGS_OFFSET(x) (0x400 + x) 82 + 83 + /* bit definitions for REG_UFS_CFG0 register */ 84 + #define QUNIPRO_G4_SEL BIT(5) 83 85 84 86 /* bit definitions for REG_UFS_CFG1 register */ 85 87 #define QUNIPRO_SEL BIT(0)