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dt-bindings: dmaengine: Document qcom,gpi dma binding
Add devicetree binding documentation for GPI DMA controller
implemented on Qualcomm SoCs
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20201109085450.24843-2-vkoul@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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Documentation/devicetree/bindings/dma/qcom,gpi.yaml
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Documentation/devicetree/bindings/dma/qcom,gpi.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/dma/qcom,gpi.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Technologies Inc GPI DMA controller
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maintainers:
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- Vinod Koul <vkoul@kernel.org>
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description: |
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QCOM GPI DMA controller provides DMA capabilities for
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peripheral buses such as I2C, UART, and SPI.
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allOf:
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- $ref: "dma-controller.yaml#"
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properties:
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compatible:
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enum:
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- qcom,sdm845-gpi-dma
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reg:
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maxItems: 1
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interrupts:
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description:
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Interrupt lines for each GPI instance
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maxItems: 13
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"#dma-cells":
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const: 3
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description: >
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DMA clients must use the format described in dma.txt, giving a phandle
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to the DMA controller plus the following 3 integer cells:
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- channel: if set to 0xffffffff, any available channel will be allocated
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for the client. Otherwise, the exact channel specified will be used.
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- seid: serial id of the client as defined in the SoC documentation.
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- client: type of the client as defined in dt-bindings/dma/qcom-gpi.h
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iommus:
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maxItems: 1
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dma-channels:
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maximum: 31
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dma-channel-mask:
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maxItems: 1
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required:
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- compatible
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- reg
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- interrupts
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- "#dma-cells"
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- iommus
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- dma-channels
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- dma-channel-mask
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/dma/qcom-gpi.h>
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gpi_dma0: dma-controller@800000 {
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compatible = "qcom,gpi-dma";
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#dma-cells = <3>;
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reg = <0x00800000 0x60000>;
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iommus = <&apps_smmu 0x0016 0x0>;
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dma-channels = <13>;
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dma-channel-mask = <0xfa>;
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interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
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};
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...
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include/dt-bindings/dma/qcom-gpi.h
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include/dt-bindings/dma/qcom-gpi.h
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/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
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/* Copyright (c) 2020, Linaro Ltd. */
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#ifndef __DT_BINDINGS_DMA_QCOM_GPI_H__
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#define __DT_BINDINGS_DMA_QCOM_GPI_H__
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#define QCOM_GPI_SPI 1
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#define QCOM_GPI_UART 2
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#define QCOM_GPI_I2C 3
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#endif /* __DT_BINDINGS_DMA_QCOM_GPI_H__ */