PCI/pwrctrl: Add optional slot clock for PCI slots

Add the ability to enable optional slot clock into the pwrctrl driver.
This is used to enable slot clock in split-clock topologies, where the PCIe
host/controller supply and PCIe slot supply are not provided by the same
clock. The PCIe host/controller clock should be described in the controller
node as the controller clock, while the slot clock should be described in
controller bridge/slot subnode.

Example DT snippet:

&pcicontroller {
clocks = <&clk_dif 0>; /* PCIe controller clock */

pci@0,0 {
#address-cells = <3>;
#size-cells = <2>;
reg = <0x0 0x0 0x0 0x0 0x0>;
compatible = "pciclass,0604";
device_type = "pci";
clocks = <&clk_dif 1>; /* PCIe slot clock */
vpcie3v3-supply = <&reg_3p3v>;
ranges;
};
};

Example clock topology:
____________ ____________
| PCIe host | | PCIe slot |
| | | |
| PCIe RX<|==================|>PCIe TX |
| PCIe TX<|==================|>PCIe RX |
| | | |
| PCIe CLK<|======.. ..======|>PCIe CLK |
'------------' || || '------------'
|| ||
____________ || ||
| 9FGV0441 | || ||
| | || ||
| CLK DIF0<|======'' ||
| CLK DIF1<|==========''
| CLK DIF2<|
| CLK DIF3<|
'------------'

Immutable commit for Geert Uytterhoeven <[e-mail]>

Signed-off-by: Marek Vasut <[e-mail]>
Signed-off-by: Bjorn Helgaas <[e-mail]>
Reviewed-by: Anand Moon <[e-mail]>
Reviewed-by: Manivannan Sadhasivam <[e-mail]>
Reviewed-by: Geert Uytterhoeven <[e-mail]>
Acked-by: Bartosz Golaszewski <[e-mail]>

drivers/pci/pwrctrl/slot.c

···
  * Author: Manivannan Sadhasivam <[e-mail]>
  */
 
+#include <linux/clk.h>
 #include <linux/device.h>
 #include <linux/mod_devicetable.h>
 #include <linux/module.h>
···
 {
 	struct pci_pwrctrl_slot_data *slot;
 	struct device *dev = &pdev->dev;
+	struct clk *clk;
 	int ret;
 
 	slot = devm_kzalloc(dev, sizeof(*slot), GFP_KERNEL);
···
 				       slot);
 	if (ret)
 		goto err_regulator_disable;
+
+	clk = devm_clk_get_optional_enabled(dev, NULL);
+	if (IS_ERR(clk)) {
+		return dev_err_probe(dev, PTR_ERR(clk),
+				     "Failed to enable slot clock\n");
+	}
 
 	pci_pwrctrl_init(&slot->ctx, dev);