MIPS: Loongson: Fix cpu_probe_loongson() again

Commit 7db5e9e9e5e6c10d7d ("MIPS: loongson64: fix FTLB configuration")
move decode_configs() from the beginning of cpu_probe_loongson() to the
end in order to fix FTLB configuration. However, it breaks the CPUCFG
decoding because decode_configs() use "c->options = xxxx" rather than
"c->options |= xxxx", all information get from CPUCFG by decode_cpucfg()
is lost.

This causes error when creating a KVM guest on Loongson-3A4000:
Exception Code: 4 not handled @ PC: 0000000087ad5981, inst: 0xcb7a1898 BadVaddr: 0x0 Status: 0x0

Fix this by moving the c->cputype setting to the beginning and moving
decode_configs() after that.

Fixes: 7db5e9e9e5e6c10d7d ("MIPS: loongson64: fix FTLB configuration")
Cc: stable@vger.kernel.org
Cc: Huang Pei <huangpei@loongson.cn>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>

authored by Huacai Chen and committed by Thomas Bogendoerfer 65fee014 e47084e1

+3 -6
+3 -6
arch/mips/kernel/cpu-probe.c
··· 1677 1678 static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu) 1679 { 1680 /* All Loongson processors covered here define ExcCode 16 as GSExc. */ 1681 c->options |= MIPS_CPU_GSEXCEX; 1682 1683 switch (c->processor_id & PRID_IMP_MASK) { ··· 1690 case PRID_REV_LOONGSON2K_R1_1: 1691 case PRID_REV_LOONGSON2K_R1_2: 1692 case PRID_REV_LOONGSON2K_R1_3: 1693 - c->cputype = CPU_LOONGSON64; 1694 __cpu_name[cpu] = "Loongson-2K"; 1695 set_elf_platform(cpu, "gs264e"); 1696 set_isa(c, MIPS_CPU_ISA_M64R2); ··· 1702 switch (c->processor_id & PRID_REV_MASK) { 1703 case PRID_REV_LOONGSON3A_R2_0: 1704 case PRID_REV_LOONGSON3A_R2_1: 1705 - c->cputype = CPU_LOONGSON64; 1706 __cpu_name[cpu] = "ICT Loongson-3"; 1707 set_elf_platform(cpu, "loongson3a"); 1708 set_isa(c, MIPS_CPU_ISA_M64R2); 1709 break; 1710 case PRID_REV_LOONGSON3A_R3_0: 1711 case PRID_REV_LOONGSON3A_R3_1: 1712 - c->cputype = CPU_LOONGSON64; 1713 __cpu_name[cpu] = "ICT Loongson-3"; 1714 set_elf_platform(cpu, "loongson3a"); 1715 set_isa(c, MIPS_CPU_ISA_M64R2); ··· 1727 c->ases &= ~MIPS_ASE_VZ; /* VZ of Loongson-3A2000/3000 is incomplete */ 1728 break; 1729 case PRID_IMP_LOONGSON_64G: 1730 - c->cputype = CPU_LOONGSON64; 1731 __cpu_name[cpu] = "ICT Loongson-3"; 1732 set_elf_platform(cpu, "loongson3a"); 1733 set_isa(c, MIPS_CPU_ISA_M64R2); ··· 1736 panic("Unknown Loongson Processor ID!"); 1737 break; 1738 } 1739 - 1740 - decode_configs(c); 1741 } 1742 #else 1743 static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu) { }
··· 1677 1678 static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu) 1679 { 1680 + c->cputype = CPU_LOONGSON64; 1681 + 1682 /* All Loongson processors covered here define ExcCode 16 as GSExc. */ 1683 + decode_configs(c); 1684 c->options |= MIPS_CPU_GSEXCEX; 1685 1686 switch (c->processor_id & PRID_IMP_MASK) { ··· 1687 case PRID_REV_LOONGSON2K_R1_1: 1688 case PRID_REV_LOONGSON2K_R1_2: 1689 case PRID_REV_LOONGSON2K_R1_3: 1690 __cpu_name[cpu] = "Loongson-2K"; 1691 set_elf_platform(cpu, "gs264e"); 1692 set_isa(c, MIPS_CPU_ISA_M64R2); ··· 1700 switch (c->processor_id & PRID_REV_MASK) { 1701 case PRID_REV_LOONGSON3A_R2_0: 1702 case PRID_REV_LOONGSON3A_R2_1: 1703 __cpu_name[cpu] = "ICT Loongson-3"; 1704 set_elf_platform(cpu, "loongson3a"); 1705 set_isa(c, MIPS_CPU_ISA_M64R2); 1706 break; 1707 case PRID_REV_LOONGSON3A_R3_0: 1708 case PRID_REV_LOONGSON3A_R3_1: 1709 __cpu_name[cpu] = "ICT Loongson-3"; 1710 set_elf_platform(cpu, "loongson3a"); 1711 set_isa(c, MIPS_CPU_ISA_M64R2); ··· 1727 c->ases &= ~MIPS_ASE_VZ; /* VZ of Loongson-3A2000/3000 is incomplete */ 1728 break; 1729 case PRID_IMP_LOONGSON_64G: 1730 __cpu_name[cpu] = "ICT Loongson-3"; 1731 set_elf_platform(cpu, "loongson3a"); 1732 set_isa(c, MIPS_CPU_ISA_M64R2); ··· 1737 panic("Unknown Loongson Processor ID!"); 1738 break; 1739 } 1740 } 1741 #else 1742 static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu) { }