Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

clk: socfpga: agilex: Add bounds-checking coverage for struct stratix10_clock_data

In order to gain the bounds-checking coverage that __counted_by provides
to flexible-array members at run-time via CONFIG_UBSAN_BOUNDS (for array
indexing) and CONFIG_FORTIFY_SOURCE (for strcpy/memcpy-family functions),
we must make sure that the counter member, in this case `num`, is updated
before the first access to the flex-array member, in this case array `hws`.

commit f316cdff8d67 ("clk: Annotate struct clk_hw_onecell_data with
__counted_by") introduced `__counted_by` for `struct clk_hw_onecell_data`
together with changes to relocate some of assignments of counter `num`
before `hws` is accessed:

include/linux/clk-provider.h:
1380 struct clk_hw_onecell_data {
1381 unsigned int num;
1382 struct clk_hw *hws[] __counted_by(num);
1383 };

However, this structure is used as a member in other structs, in this
case in `struct sstratix10_clock_data`:

drivers/clk/socfpga/stratix10-clk.h:
9 struct stratix10_clock_data {
10 void __iomem *base;
11
12 /* Must be last */
13 struct clk_hw_onecell_data clk_data;
14 };

Hence, we need to move the assignments to `clk_data->clk_data.num` after
allocations for `struct stratix10_clock_data` and before accessing the
flexible array `clk_data->clk_data.hws`. And, as assignments for both
`clk_data->clk_data.num` and `clk_data->base` are originally adjacent to
each other, relocate both assignments together.

Reviewed-by: Kees Cook <keescook@chromium.org>
Signed-off-by: Gustavo A. R. Silva <gustavoars@kernel.org>
Link: https://lore.kernel.org/r/385c516c498e07eb9a521107e16a7efd26e86ea5.1698117815.git.gustavoars@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

authored by

Gustavo A. R. Silva and committed by
Stephen Boyd
65f9e1be d761bb01

+9 -9
+6 -6
drivers/clk/socfpga/clk-agilex.c
··· 471 471 if (!clk_data) 472 472 return -ENOMEM; 473 473 474 + clk_data->clk_data.num = num_clks; 475 + clk_data->base = base; 476 + 474 477 for (i = 0; i < num_clks; i++) 475 478 clk_data->clk_data.hws[i] = ERR_PTR(-ENOENT); 476 - 477 - clk_data->base = base; 478 - clk_data->clk_data.num = num_clks; 479 479 480 480 agilex_clk_register_pll(agilex_pll_clks, ARRAY_SIZE(agilex_pll_clks), clk_data); 481 481 ··· 511 511 if (!clk_data) 512 512 return -ENOMEM; 513 513 514 - for (i = 0; i < num_clks; i++) 515 - clk_data->clk_data.hws[i] = ERR_PTR(-ENOENT); 516 - 517 514 clk_data->base = base; 518 515 clk_data->clk_data.num = num_clks; 516 + 517 + for (i = 0; i < num_clks; i++) 518 + clk_data->clk_data.hws[i] = ERR_PTR(-ENOENT); 519 519 520 520 n5x_clk_register_pll(agilex_pll_clks, ARRAY_SIZE(agilex_pll_clks), clk_data); 521 521
+3 -3
drivers/clk/socfpga/clk-s10.c
··· 402 402 if (!clk_data) 403 403 return -ENOMEM; 404 404 405 - for (i = 0; i < num_clks; i++) 406 - clk_data->clk_data.hws[i] = ERR_PTR(-ENOENT); 407 - 408 405 clk_data->base = base; 409 406 clk_data->clk_data.num = num_clks; 407 + 408 + for (i = 0; i < num_clks; i++) 409 + clk_data->clk_data.hws[i] = ERR_PTR(-ENOENT); 410 410 411 411 s10_clk_register_pll(s10_pll_clks, ARRAY_SIZE(s10_pll_clks), clk_data); 412 412