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linux
gpio: mpfs: add CoreGPIO support
coreGPIO, which the "hard" core in PolarFire SoC is based on, has
different offsets for inp/outp. Add some match_data handling to account
for the differences.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20241113-jovial-atlantic-cd07f05eb2e5@spud
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
authored by
Conor Dooley
and committed by
Bartosz Golaszewski
65e93637
8bcbd037
+33
-5
+33
-5
drivers/gpio/gpio-mpfs.c
+33
-5
drivers/gpio/gpio-mpfs.c
···
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#include <linux/init.h>
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#include <linux/mod_devicetable.h>
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#include <linux/platform_device.h>
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#include <linux/property.h>
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#include <linux/regmap.h>
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#include <linux/spinlock.h>
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···
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#define MPFS_GPIO_TYPE_INT_LEVEL_HIGH 0x00
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#define MPFS_GPIO_TYPE_INT_MASK GENMASK(7, 5)
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#define MPFS_IRQ_REG 0x80
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#define MPFS_INP_REG 0x84
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#define COREGPIO_INP_REG 0x90
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#define MPFS_OUTP_REG 0x88
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#define COREGPIO_OUTP_REG 0xA0
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struct mpfs_gpio_reg_offsets {
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u8 inp;
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u8 outp;
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};
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struct mpfs_gpio_chip {
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struct regmap *regs;
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const struct mpfs_gpio_reg_offsets *offsets;
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struct gpio_chip gc;
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};
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regmap_update_bits(mpfs_gpio->regs, MPFS_GPIO_CTRL(gpio_index),
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MPFS_GPIO_DIR_MASK, MPFS_GPIO_EN_IN);
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regmap_update_bits(mpfs_gpio->regs, MPFS_OUTP_REG, BIT(gpio_index),
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regmap_update_bits(mpfs_gpio->regs, mpfs_gpio->offsets->outp, BIT(gpio_index),
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value << gpio_index);
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return 0;
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struct mpfs_gpio_chip *mpfs_gpio = gpiochip_get_data(gc);
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if (mpfs_gpio_get_direction(gc, gpio_index) == GPIO_LINE_DIRECTION_OUT)
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return regmap_test_bits(mpfs_gpio->regs, MPFS_OUTP_REG, BIT(gpio_index));
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return regmap_test_bits(mpfs_gpio->regs, mpfs_gpio->offsets->outp, BIT(gpio_index));
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else
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return regmap_test_bits(mpfs_gpio->regs, MPFS_INP_REG, BIT(gpio_index));
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return regmap_test_bits(mpfs_gpio->regs, mpfs_gpio->offsets->inp, BIT(gpio_index));
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}
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static void mpfs_gpio_set(struct gpio_chip *gc, unsigned int gpio_index, int value)
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mpfs_gpio_get(gc, gpio_index);
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regmap_update_bits(mpfs_gpio->regs, MPFS_OUTP_REG, BIT(gpio_index),
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regmap_update_bits(mpfs_gpio->regs, mpfs_gpio->offsets->outp, BIT(gpio_index),
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value << gpio_index);
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mpfs_gpio_get(gc, gpio_index);
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mpfs_gpio = devm_kzalloc(dev, sizeof(*mpfs_gpio), GFP_KERNEL);
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if (!mpfs_gpio)
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return -ENOMEM;
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mpfs_gpio->offsets = device_get_match_data(&pdev->dev);
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base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(base))
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return devm_gpiochip_add_data(dev, &mpfs_gpio->gc, mpfs_gpio);
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}
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static const struct mpfs_gpio_reg_offsets mpfs_reg_offsets = {
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.inp = MPFS_INP_REG,
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.outp = MPFS_OUTP_REG,
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};
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static const struct mpfs_gpio_reg_offsets coregpio_reg_offsets = {
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.inp = COREGPIO_INP_REG,
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.outp = COREGPIO_OUTP_REG,
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};
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static const struct of_device_id mpfs_gpio_of_ids[] = {
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{ .compatible = "microchip,mpfs-gpio", },
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{
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.compatible = "microchip,mpfs-gpio",
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.data = &mpfs_reg_offsets,
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}, {
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.compatible = "microchip,coregpio-rtl-v3",
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.data = &coregpio_reg_offsets,
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},
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{ /* end of list */ }
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};
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