tjh.dev / kernel
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Blackfin: bf51x: fix alternative portmux options

The BF51x's alternative portmux Kconfig options were copy & pasted from
the BF52x, but never tweaked to reflect it. So drop the old options as
they were never used (and were simply wrong), and add the BF51x specific
pieces to the Kconfig and header.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>

Mike Frysinger 65cd3b53 fdfb0bec

+88 -46
+52 -32
arch/blackfin/mach-bf518/Kconfig
··· 11 11 comment "Alternative Multiplexing Scheme" 12 12 13 13 choice 14 - prompt "SPORT0" 15 - default BF518_SPORT0_PORTG 14 + prompt "PWM Channel Pins" 15 + default BF518_PWM_ALL_PORTF 16 16 help 17 - Select PORT used for SPORT0. See Hardware Reference Manual 17 + Select pins used for the PWM channels: 18 + PWM_AH PWM_AL PWM_BH PWM_BL PWM_CH PWM_CL 18 19 19 - config BF518_SPORT0_PORTF 20 - bool "PORT F" 21 - help 22 - PORT F 20 + See the Hardware Reference Manual for more details. 23 21 24 - config BF518_SPORT0_PORTG 25 - bool "PORT G" 22 + config BF518_PWM_ALL_PORTF 23 + bool "PF1 - PF6" 26 24 help 27 - PORT G 25 + PF{1,2,3,4,5,6} <-> PWM_{AH,AL,BH,BL,CH,CL} 26 + 27 + config BF518_PWM_PORTF_PORTG 28 + bool "PF11 - PF14 / PG1 - PG2" 29 + help 30 + PF{11,12,13,14} <-> PWM_{AH,AL,BH,BL} 31 + PG{1,2} <-> PWM_{CH,CL} 32 + 28 33 endchoice 29 34 30 35 choice 31 - prompt "SPORT0 TSCLK Location" 32 - depends on BF518_SPORT0_PORTG 33 - default BF518_SPORT0_TSCLK_PG10 36 + prompt "PWM Sync Pin" 37 + default BF518_PWM_SYNC_PF7 34 38 help 35 - Select PIN used for SPORT0_TSCLK. See Hardware Reference Manual 39 + Select the pin used for PWM_SYNC. 36 40 37 - config BF518_SPORT0_TSCLK_PG10 38 - bool "PORT PG10" 39 - help 40 - PORT PG10 41 + See the Hardware Reference Manual for more details. 41 42 42 - config BF518_SPORT0_TSCLK_PG14 43 - bool "PORT PG14" 44 - help 45 - PORT PG14 43 + config BF518_PWM_SYNC_PF7 44 + bool "PF7" 45 + config BF518_PWM_SYNC_PF15 46 + bool "PF15" 46 47 endchoice 47 48 48 49 choice 49 - prompt "UART1" 50 - default BF518_UART1_PORTF 50 + prompt "PWM Trip B Pin" 51 + default BF518_PWM_TRIPB_PG10 51 52 help 52 - Select PORT used for UART1. See Hardware Reference Manual 53 + Select the pin used for PWM_TRIPB. 53 54 54 - config BF518_UART1_PORTF 55 - bool "PORT F" 56 - help 57 - PORT F 55 + See the Hardware Reference Manual for more details. 58 56 59 - config BF518_UART1_PORTG 60 - bool "PORT G" 57 + config BF518_PWM_TRIPB_PG10 58 + bool "PG10" 59 + config BF518_PWM_TRIPB_PG14 60 + bool "PG14" 61 + endchoice 62 + 63 + choice 64 + prompt "PPI / Timer Pins" 65 + default BF518_PPI_TMR_PG5 61 66 help 62 - PORT G 67 + Select pins used for PPI/Timer: 68 + PPICLK PPIFS1 PPIFS2 69 + TMRCLK TMR0 TMR1 70 + 71 + See the Hardware Reference Manual for more details. 72 + 73 + config BF518_PPI_TMR_PG5 74 + bool "PG5 - PG7" 75 + help 76 + PG{5,6,7} <-> {PPICLK/TMRCLK,TMR0/PPIFS1,TMR1/PPIFS2} 77 + 78 + config BF518_PPI_TMR_PG12 79 + bool "PG12 - PG14" 80 + help 81 + PG{12,13,14} <-> {PPICLK/TMRCLK,TMR0/PPIFS1,TMR1/PPIFS2} 82 + 63 83 endchoice 64 84 65 85 comment "Hysteresis/Schmitt Trigger Control"
+36 -14
arch/blackfin/mach-bf518/include/mach/portmux.h
··· 81 81 #define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1)) 82 82 #define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1)) 83 83 84 + #ifndef CONFIG_BF518_PPI_TMR_PG12 85 + #define P_PPI0_CLK (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(1)) 86 + #define P_PPI0_FS1 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(1)) 87 + #define P_PPI0_FS2 (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(1)) 88 + #else 84 89 #define P_PPI0_CLK (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(1)) 85 90 #define P_PPI0_FS1 (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(1)) 86 91 #define P_PPI0_FS2 (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(1)) 92 + #endif 87 93 #define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(1)) 88 94 89 95 /* SPI Port Mux */ ··· 145 139 #define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(1)) 146 140 147 141 /* Timer */ 142 + #ifndef CONFIG_BF518_PPI_TMR_PG12 148 143 #define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(2)) 149 144 #define P_TMR0 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(2)) 150 145 #define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(2)) 146 + #else 147 + #define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(2)) 148 + #define P_TMR0 (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(2)) 149 + #define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(2)) 150 + #endif 151 151 #define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(2)) 152 152 #define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(2)) 153 153 #define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(2)) ··· 170 158 #define P_TWI0_SDA (P_DONTCARE) 171 159 172 160 /* PWM */ 173 - #define P_PWM0_AH (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(2)) 174 - #define P_PWM0_AL (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(2)) 175 - #define P_PWM0_BH (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(2)) 176 - #define P_PWM0_BL (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(2)) 177 - #define P_PWM0_CH (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(2)) 178 - #define P_PWM0_CL (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(2)) 179 - #define P_PWM0_SYNC (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(2)) 161 + #ifndef CONFIG_BF518_PWM_PORTF_PORTG 162 + #define P_PWM_AH (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(2)) 163 + #define P_PWM_AL (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(2)) 164 + #define P_PWM_BH (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(2)) 165 + #define P_PWM_BL (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(2)) 166 + #define P_PWM_CH (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(2)) 167 + #define P_PWM_CL (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(2)) 168 + #else 169 + #define P_PWM_AH (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(2)) 170 + #define P_PWM_AL (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(2)) 171 + #define P_PWM_BH (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(2)) 172 + #define P_PWM_BL (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(2)) 173 + #define P_PWM_CH (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(2)) 174 + #define P_PWM_CL (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(2)) 175 + #endif 180 176 181 - #define P_PWM1_AH (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(2)) 182 - #define P_PWM1_AL (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(2)) 183 - #define P_PWM1_BH (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(2)) 184 - #define P_PWM1_BL (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(2)) 185 - #define P_PWM1_CH (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(2)) 186 - #define P_PWM1_CL (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(2)) 187 - #define P_PWM1_SYNC (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(2)) 177 + #ifndef CONFIG_BF518_PWM_SYNC_PF15 178 + #define P_PWM_SYNC (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(2)) 179 + #else 180 + #define P_PWM_SYNC (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(2)) 181 + #endif 188 182 183 + #ifndef CONFIG_BF518_PWM_TRIPB_PG14 184 + #define P_PWM_TRIPB (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(2)) 185 + #else 189 186 #define P_PWM_TRIPB (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(2)) 187 + #endif 190 188 191 189 /* RSI */ 192 190 #define P_RSI_DATA0 (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(1))