tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
ARM: dts: omap3 clock data
This patch creates a unique node for each clock in the OMAP3 power,
reset and clock manager (PRCM).
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
authored by
Tero Kristo
and committed by
Mike Turquette
657fc11c
ea291c98
+2844
+128
arch/arm/boot/dts/am35xx-clocks.dtsi
+128
arch/arm/boot/dts/am35xx-clocks.dtsi
···
1
+
/*
2
+
* Device Tree Source for OMAP3 clock data
3
+
*
4
+
* Copyright (C) 2013 Texas Instruments, Inc.
5
+
*
6
+
* This program is free software; you can redistribute it and/or modify
7
+
* it under the terms of the GNU General Public License version 2 as
8
+
* published by the Free Software Foundation.
9
+
*/
10
+
&scrm_clocks {
11
+
emac_ick: emac_ick {
12
+
#clock-cells = <0>;
13
+
compatible = "ti,am35xx-gate-clock";
14
+
clocks = <&ipss_ick>;
15
+
reg = <0x059c>;
16
+
ti,bit-shift = <1>;
17
+
};
18
+
19
+
emac_fck: emac_fck {
20
+
#clock-cells = <0>;
21
+
compatible = "ti,gate-clock";
22
+
clocks = <&rmii_ck>;
23
+
reg = <0x059c>;
24
+
ti,bit-shift = <9>;
25
+
};
26
+
27
+
vpfe_ick: vpfe_ick {
28
+
#clock-cells = <0>;
29
+
compatible = "ti,am35xx-gate-clock";
30
+
clocks = <&ipss_ick>;
31
+
reg = <0x059c>;
32
+
ti,bit-shift = <2>;
33
+
};
34
+
35
+
vpfe_fck: vpfe_fck {
36
+
#clock-cells = <0>;
37
+
compatible = "ti,gate-clock";
38
+
clocks = <&pclk_ck>;
39
+
reg = <0x059c>;
40
+
ti,bit-shift = <10>;
41
+
};
42
+
43
+
hsotgusb_ick_am35xx: hsotgusb_ick_am35xx {
44
+
#clock-cells = <0>;
45
+
compatible = "ti,am35xx-gate-clock";
46
+
clocks = <&ipss_ick>;
47
+
reg = <0x059c>;
48
+
ti,bit-shift = <0>;
49
+
};
50
+
51
+
hsotgusb_fck_am35xx: hsotgusb_fck_am35xx {
52
+
#clock-cells = <0>;
53
+
compatible = "ti,gate-clock";
54
+
clocks = <&sys_ck>;
55
+
reg = <0x059c>;
56
+
ti,bit-shift = <8>;
57
+
};
58
+
59
+
hecc_ck: hecc_ck {
60
+
#clock-cells = <0>;
61
+
compatible = "ti,am35xx-gate-clock";
62
+
clocks = <&sys_ck>;
63
+
reg = <0x059c>;
64
+
ti,bit-shift = <3>;
65
+
};
66
+
};
67
+
&cm_clocks {
68
+
ipss_ick: ipss_ick {
69
+
#clock-cells = <0>;
70
+
compatible = "ti,am35xx-interface-clock";
71
+
clocks = <&core_l3_ick>;
72
+
reg = <0x0a10>;
73
+
ti,bit-shift = <4>;
74
+
};
75
+
76
+
rmii_ck: rmii_ck {
77
+
#clock-cells = <0>;
78
+
compatible = "fixed-clock";
79
+
clock-frequency = <50000000>;
80
+
};
81
+
82
+
pclk_ck: pclk_ck {
83
+
#clock-cells = <0>;
84
+
compatible = "fixed-clock";
85
+
clock-frequency = <27000000>;
86
+
};
87
+
88
+
uart4_ick_am35xx: uart4_ick_am35xx {
89
+
#clock-cells = <0>;
90
+
compatible = "ti,omap3-interface-clock";
91
+
clocks = <&core_l4_ick>;
92
+
reg = <0x0a10>;
93
+
ti,bit-shift = <23>;
94
+
};
95
+
96
+
uart4_fck_am35xx: uart4_fck_am35xx {
97
+
#clock-cells = <0>;
98
+
compatible = "ti,wait-gate-clock";
99
+
clocks = <&core_48m_fck>;
100
+
reg = <0x0a00>;
101
+
ti,bit-shift = <23>;
102
+
};
103
+
};
104
+
105
+
&cm_clockdomains {
106
+
core_l3_clkdm: core_l3_clkdm {
107
+
compatible = "ti,clockdomain";
108
+
clocks = <&sdrc_ick>, <&ipss_ick>, <&emac_ick>, <&vpfe_ick>,
109
+
<&hsotgusb_ick_am35xx>, <&hsotgusb_fck_am35xx>,
110
+
<&hecc_ck>;
111
+
};
112
+
113
+
core_l4_clkdm: core_l4_clkdm {
114
+
compatible = "ti,clockdomain";
115
+
clocks = <&cpefuse_fck>, <&ts_fck>, <&usbtll_fck>,
116
+
<&usbtll_ick>, <&mmchs3_ick>, <&mmchs3_fck>,
117
+
<&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
118
+
<&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
119
+
<&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
120
+
<&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
121
+
<&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
122
+
<&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
123
+
<&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
124
+
<&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
125
+
<&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>,
126
+
<&uart4_ick_am35xx>, <&uart4_fck_am35xx>;
127
+
};
128
+
};
+41
arch/arm/boot/dts/omap3.dtsi
+41
arch/arm/boot/dts/omap3.dtsi
···
89
89
interrupts = <0>;
90
90
};
91
91
92
+
prm: prm@48306000 {
93
+
compatible = "ti,omap3-prm";
94
+
reg = <0x48306000 0x4000>;
95
+
96
+
prm_clocks: clocks {
97
+
#address-cells = <1>;
98
+
#size-cells = <0>;
99
+
};
100
+
101
+
prm_clockdomains: clockdomains {
102
+
};
103
+
};
104
+
105
+
cm: cm@48004000 {
106
+
compatible = "ti,omap3-cm";
107
+
reg = <0x48004000 0x4000>;
108
+
109
+
cm_clocks: clocks {
110
+
#address-cells = <1>;
111
+
#size-cells = <0>;
112
+
};
113
+
114
+
cm_clockdomains: clockdomains {
115
+
};
116
+
};
117
+
118
+
scrm: scrm@48002000 {
119
+
compatible = "ti,omap3-scrm";
120
+
reg = <0x48002000 0x2000>;
121
+
122
+
scrm_clocks: clocks {
123
+
#address-cells = <1>;
124
+
#size-cells = <0>;
125
+
};
126
+
127
+
scrm_clockdomains: clockdomains {
128
+
};
129
+
};
130
+
92
131
counter32k: counter@48320000 {
93
132
compatible = "ti,omap-counter32k";
94
133
reg = <0x48320000 0x20>;
···
671
632
};
672
633
};
673
634
};
635
+
636
+
/include/ "omap3xxx-clocks.dtsi"
+208
arch/arm/boot/dts/omap3430es1-clocks.dtsi
+208
arch/arm/boot/dts/omap3430es1-clocks.dtsi
···
1
+
/*
2
+
* Device Tree Source for OMAP3430 ES1 clock data
3
+
*
4
+
* Copyright (C) 2013 Texas Instruments, Inc.
5
+
*
6
+
* This program is free software; you can redistribute it and/or modify
7
+
* it under the terms of the GNU General Public License version 2 as
8
+
* published by the Free Software Foundation.
9
+
*/
10
+
&cm_clocks {
11
+
gfx_l3_ck: gfx_l3_ck {
12
+
#clock-cells = <0>;
13
+
compatible = "ti,wait-gate-clock";
14
+
clocks = <&l3_ick>;
15
+
reg = <0x0b10>;
16
+
ti,bit-shift = <0>;
17
+
};
18
+
19
+
gfx_l3_fck: gfx_l3_fck {
20
+
#clock-cells = <0>;
21
+
compatible = "ti,divider-clock";
22
+
clocks = <&l3_ick>;
23
+
ti,max-div = <7>;
24
+
reg = <0x0b40>;
25
+
ti,index-starts-at-one;
26
+
};
27
+
28
+
gfx_l3_ick: gfx_l3_ick {
29
+
#clock-cells = <0>;
30
+
compatible = "fixed-factor-clock";
31
+
clocks = <&gfx_l3_ck>;
32
+
clock-mult = <1>;
33
+
clock-div = <1>;
34
+
};
35
+
36
+
gfx_cg1_ck: gfx_cg1_ck {
37
+
#clock-cells = <0>;
38
+
compatible = "ti,wait-gate-clock";
39
+
clocks = <&gfx_l3_fck>;
40
+
reg = <0x0b00>;
41
+
ti,bit-shift = <1>;
42
+
};
43
+
44
+
gfx_cg2_ck: gfx_cg2_ck {
45
+
#clock-cells = <0>;
46
+
compatible = "ti,wait-gate-clock";
47
+
clocks = <&gfx_l3_fck>;
48
+
reg = <0x0b00>;
49
+
ti,bit-shift = <2>;
50
+
};
51
+
52
+
d2d_26m_fck: d2d_26m_fck {
53
+
#clock-cells = <0>;
54
+
compatible = "ti,wait-gate-clock";
55
+
clocks = <&sys_ck>;
56
+
reg = <0x0a00>;
57
+
ti,bit-shift = <3>;
58
+
};
59
+
60
+
fshostusb_fck: fshostusb_fck {
61
+
#clock-cells = <0>;
62
+
compatible = "ti,wait-gate-clock";
63
+
clocks = <&core_48m_fck>;
64
+
reg = <0x0a00>;
65
+
ti,bit-shift = <5>;
66
+
};
67
+
68
+
ssi_ssr_gate_fck_3430es1: ssi_ssr_gate_fck_3430es1 {
69
+
#clock-cells = <0>;
70
+
compatible = "ti,composite-no-wait-gate-clock";
71
+
clocks = <&corex2_fck>;
72
+
ti,bit-shift = <0>;
73
+
reg = <0x0a00>;
74
+
};
75
+
76
+
ssi_ssr_div_fck_3430es1: ssi_ssr_div_fck_3430es1 {
77
+
#clock-cells = <0>;
78
+
compatible = "ti,composite-divider-clock";
79
+
clocks = <&corex2_fck>;
80
+
ti,bit-shift = <8>;
81
+
reg = <0x0a40>;
82
+
ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
83
+
};
84
+
85
+
ssi_ssr_fck_3430es1: ssi_ssr_fck_3430es1 {
86
+
#clock-cells = <0>;
87
+
compatible = "ti,composite-clock";
88
+
clocks = <&ssi_ssr_gate_fck_3430es1>, <&ssi_ssr_div_fck_3430es1>;
89
+
};
90
+
91
+
ssi_sst_fck_3430es1: ssi_sst_fck_3430es1 {
92
+
#clock-cells = <0>;
93
+
compatible = "fixed-factor-clock";
94
+
clocks = <&ssi_ssr_fck_3430es1>;
95
+
clock-mult = <1>;
96
+
clock-div = <2>;
97
+
};
98
+
99
+
hsotgusb_ick_3430es1: hsotgusb_ick_3430es1 {
100
+
#clock-cells = <0>;
101
+
compatible = "ti,omap3-no-wait-interface-clock";
102
+
clocks = <&core_l3_ick>;
103
+
reg = <0x0a10>;
104
+
ti,bit-shift = <4>;
105
+
};
106
+
107
+
fac_ick: fac_ick {
108
+
#clock-cells = <0>;
109
+
compatible = "ti,omap3-interface-clock";
110
+
clocks = <&core_l4_ick>;
111
+
reg = <0x0a10>;
112
+
ti,bit-shift = <8>;
113
+
};
114
+
115
+
ssi_l4_ick: ssi_l4_ick {
116
+
#clock-cells = <0>;
117
+
compatible = "fixed-factor-clock";
118
+
clocks = <&l4_ick>;
119
+
clock-mult = <1>;
120
+
clock-div = <1>;
121
+
};
122
+
123
+
ssi_ick_3430es1: ssi_ick_3430es1 {
124
+
#clock-cells = <0>;
125
+
compatible = "ti,omap3-no-wait-interface-clock";
126
+
clocks = <&ssi_l4_ick>;
127
+
reg = <0x0a10>;
128
+
ti,bit-shift = <0>;
129
+
};
130
+
131
+
usb_l4_gate_ick: usb_l4_gate_ick {
132
+
#clock-cells = <0>;
133
+
compatible = "ti,composite-interface-clock";
134
+
clocks = <&l4_ick>;
135
+
ti,bit-shift = <5>;
136
+
reg = <0x0a10>;
137
+
};
138
+
139
+
usb_l4_div_ick: usb_l4_div_ick {
140
+
#clock-cells = <0>;
141
+
compatible = "ti,composite-divider-clock";
142
+
clocks = <&l4_ick>;
143
+
ti,bit-shift = <4>;
144
+
ti,max-div = <1>;
145
+
reg = <0x0a40>;
146
+
ti,index-starts-at-one;
147
+
};
148
+
149
+
usb_l4_ick: usb_l4_ick {
150
+
#clock-cells = <0>;
151
+
compatible = "ti,composite-clock";
152
+
clocks = <&usb_l4_gate_ick>, <&usb_l4_div_ick>;
153
+
};
154
+
155
+
dss1_alwon_fck_3430es1: dss1_alwon_fck_3430es1 {
156
+
#clock-cells = <0>;
157
+
compatible = "ti,gate-clock";
158
+
clocks = <&dpll4_m4x2_ck>;
159
+
ti,bit-shift = <0>;
160
+
reg = <0x0e00>;
161
+
ti,set-rate-parent;
162
+
};
163
+
164
+
dss_ick_3430es1: dss_ick_3430es1 {
165
+
#clock-cells = <0>;
166
+
compatible = "ti,omap3-no-wait-interface-clock";
167
+
clocks = <&l4_ick>;
168
+
reg = <0x0e10>;
169
+
ti,bit-shift = <0>;
170
+
};
171
+
};
172
+
173
+
&cm_clockdomains {
174
+
core_l3_clkdm: core_l3_clkdm {
175
+
compatible = "ti,clockdomain";
176
+
clocks = <&sdrc_ick>, <&hsotgusb_ick_3430es1>;
177
+
};
178
+
179
+
gfx_3430es1_clkdm: gfx_3430es1_clkdm {
180
+
compatible = "ti,clockdomain";
181
+
clocks = <&gfx_l3_ck>, <&gfx_cg1_ck>, <&gfx_cg2_ck>;
182
+
};
183
+
184
+
dss_clkdm: dss_clkdm {
185
+
compatible = "ti,clockdomain";
186
+
clocks = <&dss_tv_fck>, <&dss_96m_fck>, <&dss2_alwon_fck>,
187
+
<&dss1_alwon_fck_3430es1>, <&dss_ick_3430es1>;
188
+
};
189
+
190
+
d2d_clkdm: d2d_clkdm {
191
+
compatible = "ti,clockdomain";
192
+
clocks = <&d2d_26m_fck>;
193
+
};
194
+
195
+
core_l4_clkdm: core_l4_clkdm {
196
+
compatible = "ti,clockdomain";
197
+
clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
198
+
<&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
199
+
<&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
200
+
<&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
201
+
<&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
202
+
<&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
203
+
<&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
204
+
<&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
205
+
<&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>,
206
+
<&fshostusb_fck>, <&fac_ick>, <&ssi_ick_3430es1>;
207
+
};
208
+
};
+268
arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi
+268
arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi
···
1
+
/*
2
+
* Device Tree Source for OMAP34XX/OMAP36XX clock data
3
+
*
4
+
* Copyright (C) 2013 Texas Instruments, Inc.
5
+
*
6
+
* This program is free software; you can redistribute it and/or modify
7
+
* it under the terms of the GNU General Public License version 2 as
8
+
* published by the Free Software Foundation.
9
+
*/
10
+
&cm_clocks {
11
+
security_l4_ick2: security_l4_ick2 {
12
+
#clock-cells = <0>;
13
+
compatible = "fixed-factor-clock";
14
+
clocks = <&l4_ick>;
15
+
clock-mult = <1>;
16
+
clock-div = <1>;
17
+
};
18
+
19
+
aes1_ick: aes1_ick {
20
+
#clock-cells = <0>;
21
+
compatible = "ti,omap3-interface-clock";
22
+
clocks = <&security_l4_ick2>;
23
+
ti,bit-shift = <3>;
24
+
reg = <0x0a14>;
25
+
};
26
+
27
+
rng_ick: rng_ick {
28
+
#clock-cells = <0>;
29
+
compatible = "ti,omap3-interface-clock";
30
+
clocks = <&security_l4_ick2>;
31
+
reg = <0x0a14>;
32
+
ti,bit-shift = <2>;
33
+
};
34
+
35
+
sha11_ick: sha11_ick {
36
+
#clock-cells = <0>;
37
+
compatible = "ti,omap3-interface-clock";
38
+
clocks = <&security_l4_ick2>;
39
+
reg = <0x0a14>;
40
+
ti,bit-shift = <1>;
41
+
};
42
+
43
+
des1_ick: des1_ick {
44
+
#clock-cells = <0>;
45
+
compatible = "ti,omap3-interface-clock";
46
+
clocks = <&security_l4_ick2>;
47
+
reg = <0x0a14>;
48
+
ti,bit-shift = <0>;
49
+
};
50
+
51
+
cam_mclk: cam_mclk {
52
+
#clock-cells = <0>;
53
+
compatible = "ti,gate-clock";
54
+
clocks = <&dpll4_m5x2_ck>;
55
+
ti,bit-shift = <0>;
56
+
reg = <0x0f00>;
57
+
ti,set-rate-parent;
58
+
};
59
+
60
+
cam_ick: cam_ick {
61
+
#clock-cells = <0>;
62
+
compatible = "ti,omap3-no-wait-interface-clock";
63
+
clocks = <&l4_ick>;
64
+
reg = <0x0f10>;
65
+
ti,bit-shift = <0>;
66
+
};
67
+
68
+
csi2_96m_fck: csi2_96m_fck {
69
+
#clock-cells = <0>;
70
+
compatible = "ti,gate-clock";
71
+
clocks = <&core_96m_fck>;
72
+
reg = <0x0f00>;
73
+
ti,bit-shift = <1>;
74
+
};
75
+
76
+
security_l3_ick: security_l3_ick {
77
+
#clock-cells = <0>;
78
+
compatible = "fixed-factor-clock";
79
+
clocks = <&l3_ick>;
80
+
clock-mult = <1>;
81
+
clock-div = <1>;
82
+
};
83
+
84
+
pka_ick: pka_ick {
85
+
#clock-cells = <0>;
86
+
compatible = "ti,omap3-interface-clock";
87
+
clocks = <&security_l3_ick>;
88
+
reg = <0x0a14>;
89
+
ti,bit-shift = <4>;
90
+
};
91
+
92
+
icr_ick: icr_ick {
93
+
#clock-cells = <0>;
94
+
compatible = "ti,omap3-interface-clock";
95
+
clocks = <&core_l4_ick>;
96
+
reg = <0x0a10>;
97
+
ti,bit-shift = <29>;
98
+
};
99
+
100
+
des2_ick: des2_ick {
101
+
#clock-cells = <0>;
102
+
compatible = "ti,omap3-interface-clock";
103
+
clocks = <&core_l4_ick>;
104
+
reg = <0x0a10>;
105
+
ti,bit-shift = <26>;
106
+
};
107
+
108
+
mspro_ick: mspro_ick {
109
+
#clock-cells = <0>;
110
+
compatible = "ti,omap3-interface-clock";
111
+
clocks = <&core_l4_ick>;
112
+
reg = <0x0a10>;
113
+
ti,bit-shift = <23>;
114
+
};
115
+
116
+
mailboxes_ick: mailboxes_ick {
117
+
#clock-cells = <0>;
118
+
compatible = "ti,omap3-interface-clock";
119
+
clocks = <&core_l4_ick>;
120
+
reg = <0x0a10>;
121
+
ti,bit-shift = <7>;
122
+
};
123
+
124
+
ssi_l4_ick: ssi_l4_ick {
125
+
#clock-cells = <0>;
126
+
compatible = "fixed-factor-clock";
127
+
clocks = <&l4_ick>;
128
+
clock-mult = <1>;
129
+
clock-div = <1>;
130
+
};
131
+
132
+
sr1_fck: sr1_fck {
133
+
#clock-cells = <0>;
134
+
compatible = "ti,wait-gate-clock";
135
+
clocks = <&sys_ck>;
136
+
reg = <0x0c00>;
137
+
ti,bit-shift = <6>;
138
+
};
139
+
140
+
sr2_fck: sr2_fck {
141
+
#clock-cells = <0>;
142
+
compatible = "ti,wait-gate-clock";
143
+
clocks = <&sys_ck>;
144
+
reg = <0x0c00>;
145
+
ti,bit-shift = <7>;
146
+
};
147
+
148
+
sr_l4_ick: sr_l4_ick {
149
+
#clock-cells = <0>;
150
+
compatible = "fixed-factor-clock";
151
+
clocks = <&l4_ick>;
152
+
clock-mult = <1>;
153
+
clock-div = <1>;
154
+
};
155
+
156
+
dpll2_fck: dpll2_fck {
157
+
#clock-cells = <0>;
158
+
compatible = "ti,divider-clock";
159
+
clocks = <&core_ck>;
160
+
ti,bit-shift = <19>;
161
+
ti,max-div = <7>;
162
+
reg = <0x0040>;
163
+
ti,index-starts-at-one;
164
+
};
165
+
166
+
dpll2_ck: dpll2_ck {
167
+
#clock-cells = <0>;
168
+
compatible = "ti,omap3-dpll-clock";
169
+
clocks = <&sys_ck>, <&dpll2_fck>;
170
+
reg = <0x0004>, <0x0024>, <0x0040>, <0x0034>;
171
+
ti,low-power-stop;
172
+
ti,lock;
173
+
ti,low-power-bypass;
174
+
};
175
+
176
+
dpll2_m2_ck: dpll2_m2_ck {
177
+
#clock-cells = <0>;
178
+
compatible = "ti,divider-clock";
179
+
clocks = <&dpll2_ck>;
180
+
ti,max-div = <31>;
181
+
reg = <0x0044>;
182
+
ti,index-starts-at-one;
183
+
};
184
+
185
+
iva2_ck: iva2_ck {
186
+
#clock-cells = <0>;
187
+
compatible = "ti,wait-gate-clock";
188
+
clocks = <&dpll2_m2_ck>;
189
+
reg = <0x0000>;
190
+
ti,bit-shift = <0>;
191
+
};
192
+
193
+
modem_fck: modem_fck {
194
+
#clock-cells = <0>;
195
+
compatible = "ti,omap3-interface-clock";
196
+
clocks = <&sys_ck>;
197
+
reg = <0x0a00>;
198
+
ti,bit-shift = <31>;
199
+
};
200
+
201
+
sad2d_ick: sad2d_ick {
202
+
#clock-cells = <0>;
203
+
compatible = "ti,omap3-interface-clock";
204
+
clocks = <&l3_ick>;
205
+
reg = <0x0a10>;
206
+
ti,bit-shift = <3>;
207
+
};
208
+
209
+
mad2d_ick: mad2d_ick {
210
+
#clock-cells = <0>;
211
+
compatible = "ti,omap3-interface-clock";
212
+
clocks = <&l3_ick>;
213
+
reg = <0x0a18>;
214
+
ti,bit-shift = <3>;
215
+
};
216
+
217
+
mspro_fck: mspro_fck {
218
+
#clock-cells = <0>;
219
+
compatible = "ti,wait-gate-clock";
220
+
clocks = <&core_96m_fck>;
221
+
reg = <0x0a00>;
222
+
ti,bit-shift = <23>;
223
+
};
224
+
};
225
+
226
+
&cm_clockdomains {
227
+
cam_clkdm: cam_clkdm {
228
+
compatible = "ti,clockdomain";
229
+
clocks = <&cam_ick>, <&csi2_96m_fck>;
230
+
};
231
+
232
+
iva2_clkdm: iva2_clkdm {
233
+
compatible = "ti,clockdomain";
234
+
clocks = <&iva2_ck>;
235
+
};
236
+
237
+
dpll2_clkdm: dpll2_clkdm {
238
+
compatible = "ti,clockdomain";
239
+
clocks = <&dpll2_ck>;
240
+
};
241
+
242
+
wkup_clkdm: wkup_clkdm {
243
+
compatible = "ti,clockdomain";
244
+
clocks = <&gpio1_dbck>, <&wdt2_fck>, <&wdt2_ick>, <&wdt1_ick>,
245
+
<&gpio1_ick>, <&omap_32ksync_ick>, <&gpt12_ick>,
246
+
<&gpt1_ick>, <&sr1_fck>, <&sr2_fck>;
247
+
};
248
+
249
+
d2d_clkdm: d2d_clkdm {
250
+
compatible = "ti,clockdomain";
251
+
clocks = <&modem_fck>, <&sad2d_ick>, <&mad2d_ick>;
252
+
};
253
+
254
+
core_l4_clkdm: core_l4_clkdm {
255
+
compatible = "ti,clockdomain";
256
+
clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
257
+
<&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
258
+
<&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
259
+
<&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
260
+
<&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
261
+
<&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
262
+
<&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
263
+
<&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
264
+
<&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>, <&icr_ick>,
265
+
<&des2_ick>, <&mspro_ick>, <&mailboxes_ick>,
266
+
<&mspro_fck>;
267
+
};
268
+
};
+4
arch/arm/boot/dts/omap34xx.dtsi
+4
arch/arm/boot/dts/omap34xx.dtsi
+242
arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi
+242
arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi
···
1
+
/*
2
+
* Device Tree Source for OMAP36xx/AM35xx/OMAP34xx clock data
3
+
*
4
+
* Copyright (C) 2013 Texas Instruments, Inc.
5
+
*
6
+
* This program is free software; you can redistribute it and/or modify
7
+
* it under the terms of the GNU General Public License version 2 as
8
+
* published by the Free Software Foundation.
9
+
*/
10
+
&prm_clocks {
11
+
corex2_d3_fck: corex2_d3_fck {
12
+
#clock-cells = <0>;
13
+
compatible = "fixed-factor-clock";
14
+
clocks = <&corex2_fck>;
15
+
clock-mult = <1>;
16
+
clock-div = <3>;
17
+
};
18
+
19
+
corex2_d5_fck: corex2_d5_fck {
20
+
#clock-cells = <0>;
21
+
compatible = "fixed-factor-clock";
22
+
clocks = <&corex2_fck>;
23
+
clock-mult = <1>;
24
+
clock-div = <5>;
25
+
};
26
+
};
27
+
&cm_clocks {
28
+
dpll5_ck: dpll5_ck {
29
+
#clock-cells = <0>;
30
+
compatible = "ti,omap3-dpll-clock";
31
+
clocks = <&sys_ck>, <&sys_ck>;
32
+
reg = <0x0d04>, <0x0d24>, <0x0d4c>, <0x0d34>;
33
+
ti,low-power-stop;
34
+
ti,lock;
35
+
};
36
+
37
+
dpll5_m2_ck: dpll5_m2_ck {
38
+
#clock-cells = <0>;
39
+
compatible = "ti,divider-clock";
40
+
clocks = <&dpll5_ck>;
41
+
ti,max-div = <31>;
42
+
reg = <0x0d50>;
43
+
ti,index-starts-at-one;
44
+
};
45
+
46
+
sgx_gate_fck: sgx_gate_fck {
47
+
#clock-cells = <0>;
48
+
compatible = "ti,composite-gate-clock";
49
+
clocks = <&core_ck>;
50
+
ti,bit-shift = <1>;
51
+
reg = <0x0b00>;
52
+
};
53
+
54
+
core_d3_ck: core_d3_ck {
55
+
#clock-cells = <0>;
56
+
compatible = "fixed-factor-clock";
57
+
clocks = <&core_ck>;
58
+
clock-mult = <1>;
59
+
clock-div = <3>;
60
+
};
61
+
62
+
core_d4_ck: core_d4_ck {
63
+
#clock-cells = <0>;
64
+
compatible = "fixed-factor-clock";
65
+
clocks = <&core_ck>;
66
+
clock-mult = <1>;
67
+
clock-div = <4>;
68
+
};
69
+
70
+
core_d6_ck: core_d6_ck {
71
+
#clock-cells = <0>;
72
+
compatible = "fixed-factor-clock";
73
+
clocks = <&core_ck>;
74
+
clock-mult = <1>;
75
+
clock-div = <6>;
76
+
};
77
+
78
+
omap_192m_alwon_fck: omap_192m_alwon_fck {
79
+
#clock-cells = <0>;
80
+
compatible = "fixed-factor-clock";
81
+
clocks = <&dpll4_m2x2_ck>;
82
+
clock-mult = <1>;
83
+
clock-div = <1>;
84
+
};
85
+
86
+
core_d2_ck: core_d2_ck {
87
+
#clock-cells = <0>;
88
+
compatible = "fixed-factor-clock";
89
+
clocks = <&core_ck>;
90
+
clock-mult = <1>;
91
+
clock-div = <2>;
92
+
};
93
+
94
+
sgx_mux_fck: sgx_mux_fck {
95
+
#clock-cells = <0>;
96
+
compatible = "ti,composite-mux-clock";
97
+
clocks = <&core_d3_ck>, <&core_d4_ck>, <&core_d6_ck>, <&cm_96m_fck>, <&omap_192m_alwon_fck>, <&core_d2_ck>, <&corex2_d3_fck>, <&corex2_d5_fck>;
98
+
reg = <0x0b40>;
99
+
};
100
+
101
+
sgx_fck: sgx_fck {
102
+
#clock-cells = <0>;
103
+
compatible = "ti,composite-clock";
104
+
clocks = <&sgx_gate_fck>, <&sgx_mux_fck>;
105
+
};
106
+
107
+
sgx_ick: sgx_ick {
108
+
#clock-cells = <0>;
109
+
compatible = "ti,wait-gate-clock";
110
+
clocks = <&l3_ick>;
111
+
reg = <0x0b10>;
112
+
ti,bit-shift = <0>;
113
+
};
114
+
115
+
cpefuse_fck: cpefuse_fck {
116
+
#clock-cells = <0>;
117
+
compatible = "ti,gate-clock";
118
+
clocks = <&sys_ck>;
119
+
reg = <0x0a08>;
120
+
ti,bit-shift = <0>;
121
+
};
122
+
123
+
ts_fck: ts_fck {
124
+
#clock-cells = <0>;
125
+
compatible = "ti,gate-clock";
126
+
clocks = <&omap_32k_fck>;
127
+
reg = <0x0a08>;
128
+
ti,bit-shift = <1>;
129
+
};
130
+
131
+
usbtll_fck: usbtll_fck {
132
+
#clock-cells = <0>;
133
+
compatible = "ti,wait-gate-clock";
134
+
clocks = <&dpll5_m2_ck>;
135
+
reg = <0x0a08>;
136
+
ti,bit-shift = <2>;
137
+
};
138
+
139
+
usbtll_ick: usbtll_ick {
140
+
#clock-cells = <0>;
141
+
compatible = "ti,omap3-interface-clock";
142
+
clocks = <&core_l4_ick>;
143
+
reg = <0x0a18>;
144
+
ti,bit-shift = <2>;
145
+
};
146
+
147
+
mmchs3_ick: mmchs3_ick {
148
+
#clock-cells = <0>;
149
+
compatible = "ti,omap3-interface-clock";
150
+
clocks = <&core_l4_ick>;
151
+
reg = <0x0a10>;
152
+
ti,bit-shift = <30>;
153
+
};
154
+
155
+
mmchs3_fck: mmchs3_fck {
156
+
#clock-cells = <0>;
157
+
compatible = "ti,wait-gate-clock";
158
+
clocks = <&core_96m_fck>;
159
+
reg = <0x0a00>;
160
+
ti,bit-shift = <30>;
161
+
};
162
+
163
+
dss1_alwon_fck_3430es2: dss1_alwon_fck_3430es2 {
164
+
#clock-cells = <0>;
165
+
compatible = "ti,dss-gate-clock";
166
+
clocks = <&dpll4_m4x2_ck>;
167
+
ti,bit-shift = <0>;
168
+
reg = <0x0e00>;
169
+
ti,set-rate-parent;
170
+
};
171
+
172
+
dss_ick_3430es2: dss_ick_3430es2 {
173
+
#clock-cells = <0>;
174
+
compatible = "ti,omap3-dss-interface-clock";
175
+
clocks = <&l4_ick>;
176
+
reg = <0x0e10>;
177
+
ti,bit-shift = <0>;
178
+
};
179
+
180
+
usbhost_120m_fck: usbhost_120m_fck {
181
+
#clock-cells = <0>;
182
+
compatible = "ti,gate-clock";
183
+
clocks = <&dpll5_m2_ck>;
184
+
reg = <0x1400>;
185
+
ti,bit-shift = <1>;
186
+
};
187
+
188
+
usbhost_48m_fck: usbhost_48m_fck {
189
+
#clock-cells = <0>;
190
+
compatible = "ti,dss-gate-clock";
191
+
clocks = <&omap_48m_fck>;
192
+
reg = <0x1400>;
193
+
ti,bit-shift = <0>;
194
+
};
195
+
196
+
usbhost_ick: usbhost_ick {
197
+
#clock-cells = <0>;
198
+
compatible = "ti,omap3-dss-interface-clock";
199
+
clocks = <&l4_ick>;
200
+
reg = <0x1410>;
201
+
ti,bit-shift = <0>;
202
+
};
203
+
};
204
+
205
+
&cm_clockdomains {
206
+
dpll5_clkdm: dpll5_clkdm {
207
+
compatible = "ti,clockdomain";
208
+
clocks = <&dpll5_ck>;
209
+
};
210
+
211
+
sgx_clkdm: sgx_clkdm {
212
+
compatible = "ti,clockdomain";
213
+
clocks = <&sgx_ick>;
214
+
};
215
+
216
+
dss_clkdm: dss_clkdm {
217
+
compatible = "ti,clockdomain";
218
+
clocks = <&dss_tv_fck>, <&dss_96m_fck>, <&dss2_alwon_fck>,
219
+
<&dss1_alwon_fck_3430es2>, <&dss_ick_3430es2>;
220
+
};
221
+
222
+
core_l4_clkdm: core_l4_clkdm {
223
+
compatible = "ti,clockdomain";
224
+
clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
225
+
<&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
226
+
<&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
227
+
<&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
228
+
<&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
229
+
<&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
230
+
<&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
231
+
<&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
232
+
<&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>,
233
+
<&cpefuse_fck>, <&ts_fck>, <&usbtll_fck>,
234
+
<&usbtll_ick>, <&mmchs3_ick>, <&mmchs3_fck>;
235
+
};
236
+
237
+
usbhost_clkdm: usbhost_clkdm {
238
+
compatible = "ti,clockdomain";
239
+
clocks = <&usbhost_120m_fck>, <&usbhost_48m_fck>,
240
+
<&usbhost_ick>;
241
+
};
242
+
};
+90
arch/arm/boot/dts/omap36xx-clocks.dtsi
+90
arch/arm/boot/dts/omap36xx-clocks.dtsi
···
1
+
/*
2
+
* Device Tree Source for OMAP36xx clock data
3
+
*
4
+
* Copyright (C) 2013 Texas Instruments, Inc.
5
+
*
6
+
* This program is free software; you can redistribute it and/or modify
7
+
* it under the terms of the GNU General Public License version 2 as
8
+
* published by the Free Software Foundation.
9
+
*/
10
+
&cm_clocks {
11
+
dpll4_ck: dpll4_ck {
12
+
#clock-cells = <0>;
13
+
compatible = "ti,omap3-dpll-per-j-type-clock";
14
+
clocks = <&sys_ck>, <&sys_ck>;
15
+
reg = <0x0d00>, <0x0d20>, <0x0d44>, <0x0d30>;
16
+
};
17
+
18
+
dpll4_m5x2_ck: dpll4_m5x2_ck {
19
+
#clock-cells = <0>;
20
+
compatible = "ti,hsdiv-gate-clock";
21
+
clocks = <&dpll4_m5x2_mul_ck>;
22
+
ti,bit-shift = <0x1e>;
23
+
reg = <0x0d00>;
24
+
ti,set-rate-parent;
25
+
ti,set-bit-to-disable;
26
+
};
27
+
28
+
dpll4_m2x2_ck: dpll4_m2x2_ck {
29
+
#clock-cells = <0>;
30
+
compatible = "ti,hsdiv-gate-clock";
31
+
clocks = <&dpll4_m2x2_mul_ck>;
32
+
ti,bit-shift = <0x1b>;
33
+
reg = <0x0d00>;
34
+
ti,set-bit-to-disable;
35
+
};
36
+
37
+
dpll3_m3x2_ck: dpll3_m3x2_ck {
38
+
#clock-cells = <0>;
39
+
compatible = "ti,hsdiv-gate-clock";
40
+
clocks = <&dpll3_m3x2_mul_ck>;
41
+
ti,bit-shift = <0xc>;
42
+
reg = <0x0d00>;
43
+
ti,set-bit-to-disable;
44
+
};
45
+
46
+
dpll4_m3x2_ck: dpll4_m3x2_ck {
47
+
#clock-cells = <0>;
48
+
compatible = "ti,hsdiv-gate-clock";
49
+
clocks = <&dpll4_m3x2_mul_ck>;
50
+
ti,bit-shift = <0x1c>;
51
+
reg = <0x0d00>;
52
+
ti,set-bit-to-disable;
53
+
};
54
+
55
+
dpll4_m6x2_ck: dpll4_m6x2_ck {
56
+
#clock-cells = <0>;
57
+
compatible = "ti,hsdiv-gate-clock";
58
+
clocks = <&dpll4_m6x2_mul_ck>;
59
+
ti,bit-shift = <0x1f>;
60
+
reg = <0x0d00>;
61
+
ti,set-bit-to-disable;
62
+
};
63
+
64
+
uart4_fck: uart4_fck {
65
+
#clock-cells = <0>;
66
+
compatible = "ti,wait-gate-clock";
67
+
clocks = <&per_48m_fck>;
68
+
reg = <0x1000>;
69
+
ti,bit-shift = <18>;
70
+
};
71
+
};
72
+
73
+
&cm_clockdomains {
74
+
dpll4_clkdm: dpll4_clkdm {
75
+
compatible = "ti,clockdomain";
76
+
clocks = <&dpll4_ck>;
77
+
};
78
+
79
+
per_clkdm: per_clkdm {
80
+
compatible = "ti,clockdomain";
81
+
clocks = <&uart3_fck>, <&gpio6_dbck>, <&gpio5_dbck>,
82
+
<&gpio4_dbck>, <&gpio3_dbck>, <&gpio2_dbck>,
83
+
<&wdt3_fck>, <&gpio6_ick>, <&gpio5_ick>, <&gpio4_ick>,
84
+
<&gpio3_ick>, <&gpio2_ick>, <&wdt3_ick>, <&uart3_ick>,
85
+
<&uart4_ick>, <&gpt9_ick>, <&gpt8_ick>, <&gpt7_ick>,
86
+
<&gpt6_ick>, <&gpt5_ick>, <&gpt4_ick>, <&gpt3_ick>,
87
+
<&gpt2_ick>, <&mcbsp2_ick>, <&mcbsp3_ick>,
88
+
<&mcbsp4_ick>, <&uart4_fck>;
89
+
};
90
+
};
+198
arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi
+198
arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi
···
1
+
/*
2
+
* Device Tree Source for OMAP34xx/OMAP36xx clock data
3
+
*
4
+
* Copyright (C) 2013 Texas Instruments, Inc.
5
+
*
6
+
* This program is free software; you can redistribute it and/or modify
7
+
* it under the terms of the GNU General Public License version 2 as
8
+
* published by the Free Software Foundation.
9
+
*/
10
+
&cm_clocks {
11
+
ssi_ssr_gate_fck_3430es2: ssi_ssr_gate_fck_3430es2 {
12
+
#clock-cells = <0>;
13
+
compatible = "ti,composite-no-wait-gate-clock";
14
+
clocks = <&corex2_fck>;
15
+
ti,bit-shift = <0>;
16
+
reg = <0x0a00>;
17
+
};
18
+
19
+
ssi_ssr_div_fck_3430es2: ssi_ssr_div_fck_3430es2 {
20
+
#clock-cells = <0>;
21
+
compatible = "ti,composite-divider-clock";
22
+
clocks = <&corex2_fck>;
23
+
ti,bit-shift = <8>;
24
+
reg = <0x0a40>;
25
+
ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
26
+
};
27
+
28
+
ssi_ssr_fck_3430es2: ssi_ssr_fck_3430es2 {
29
+
#clock-cells = <0>;
30
+
compatible = "ti,composite-clock";
31
+
clocks = <&ssi_ssr_gate_fck_3430es2>, <&ssi_ssr_div_fck_3430es2>;
32
+
};
33
+
34
+
ssi_sst_fck_3430es2: ssi_sst_fck_3430es2 {
35
+
#clock-cells = <0>;
36
+
compatible = "fixed-factor-clock";
37
+
clocks = <&ssi_ssr_fck_3430es2>;
38
+
clock-mult = <1>;
39
+
clock-div = <2>;
40
+
};
41
+
42
+
hsotgusb_ick_3430es2: hsotgusb_ick_3430es2 {
43
+
#clock-cells = <0>;
44
+
compatible = "ti,omap3-hsotgusb-interface-clock";
45
+
clocks = <&core_l3_ick>;
46
+
reg = <0x0a10>;
47
+
ti,bit-shift = <4>;
48
+
};
49
+
50
+
ssi_l4_ick: ssi_l4_ick {
51
+
#clock-cells = <0>;
52
+
compatible = "fixed-factor-clock";
53
+
clocks = <&l4_ick>;
54
+
clock-mult = <1>;
55
+
clock-div = <1>;
56
+
};
57
+
58
+
ssi_ick_3430es2: ssi_ick_3430es2 {
59
+
#clock-cells = <0>;
60
+
compatible = "ti,omap3-ssi-interface-clock";
61
+
clocks = <&ssi_l4_ick>;
62
+
reg = <0x0a10>;
63
+
ti,bit-shift = <0>;
64
+
};
65
+
66
+
usim_gate_fck: usim_gate_fck {
67
+
#clock-cells = <0>;
68
+
compatible = "ti,composite-gate-clock";
69
+
clocks = <&omap_96m_fck>;
70
+
ti,bit-shift = <9>;
71
+
reg = <0x0c00>;
72
+
};
73
+
74
+
sys_d2_ck: sys_d2_ck {
75
+
#clock-cells = <0>;
76
+
compatible = "fixed-factor-clock";
77
+
clocks = <&sys_ck>;
78
+
clock-mult = <1>;
79
+
clock-div = <2>;
80
+
};
81
+
82
+
omap_96m_d2_fck: omap_96m_d2_fck {
83
+
#clock-cells = <0>;
84
+
compatible = "fixed-factor-clock";
85
+
clocks = <&omap_96m_fck>;
86
+
clock-mult = <1>;
87
+
clock-div = <2>;
88
+
};
89
+
90
+
omap_96m_d4_fck: omap_96m_d4_fck {
91
+
#clock-cells = <0>;
92
+
compatible = "fixed-factor-clock";
93
+
clocks = <&omap_96m_fck>;
94
+
clock-mult = <1>;
95
+
clock-div = <4>;
96
+
};
97
+
98
+
omap_96m_d8_fck: omap_96m_d8_fck {
99
+
#clock-cells = <0>;
100
+
compatible = "fixed-factor-clock";
101
+
clocks = <&omap_96m_fck>;
102
+
clock-mult = <1>;
103
+
clock-div = <8>;
104
+
};
105
+
106
+
omap_96m_d10_fck: omap_96m_d10_fck {
107
+
#clock-cells = <0>;
108
+
compatible = "fixed-factor-clock";
109
+
clocks = <&omap_96m_fck>;
110
+
clock-mult = <1>;
111
+
clock-div = <10>;
112
+
};
113
+
114
+
dpll5_m2_d4_ck: dpll5_m2_d4_ck {
115
+
#clock-cells = <0>;
116
+
compatible = "fixed-factor-clock";
117
+
clocks = <&dpll5_m2_ck>;
118
+
clock-mult = <1>;
119
+
clock-div = <4>;
120
+
};
121
+
122
+
dpll5_m2_d8_ck: dpll5_m2_d8_ck {
123
+
#clock-cells = <0>;
124
+
compatible = "fixed-factor-clock";
125
+
clocks = <&dpll5_m2_ck>;
126
+
clock-mult = <1>;
127
+
clock-div = <8>;
128
+
};
129
+
130
+
dpll5_m2_d16_ck: dpll5_m2_d16_ck {
131
+
#clock-cells = <0>;
132
+
compatible = "fixed-factor-clock";
133
+
clocks = <&dpll5_m2_ck>;
134
+
clock-mult = <1>;
135
+
clock-div = <16>;
136
+
};
137
+
138
+
dpll5_m2_d20_ck: dpll5_m2_d20_ck {
139
+
#clock-cells = <0>;
140
+
compatible = "fixed-factor-clock";
141
+
clocks = <&dpll5_m2_ck>;
142
+
clock-mult = <1>;
143
+
clock-div = <20>;
144
+
};
145
+
146
+
usim_mux_fck: usim_mux_fck {
147
+
#clock-cells = <0>;
148
+
compatible = "ti,composite-mux-clock";
149
+
clocks = <&sys_ck>, <&sys_d2_ck>, <&omap_96m_d2_fck>, <&omap_96m_d4_fck>, <&omap_96m_d8_fck>, <&omap_96m_d10_fck>, <&dpll5_m2_d4_ck>, <&dpll5_m2_d8_ck>, <&dpll5_m2_d16_ck>, <&dpll5_m2_d20_ck>;
150
+
ti,bit-shift = <3>;
151
+
reg = <0x0c40>;
152
+
ti,index-starts-at-one;
153
+
};
154
+
155
+
usim_fck: usim_fck {
156
+
#clock-cells = <0>;
157
+
compatible = "ti,composite-clock";
158
+
clocks = <&usim_gate_fck>, <&usim_mux_fck>;
159
+
};
160
+
161
+
usim_ick: usim_ick {
162
+
#clock-cells = <0>;
163
+
compatible = "ti,omap3-interface-clock";
164
+
clocks = <&wkup_l4_ick>;
165
+
reg = <0x0c10>;
166
+
ti,bit-shift = <9>;
167
+
};
168
+
};
169
+
170
+
&cm_clockdomains {
171
+
core_l3_clkdm: core_l3_clkdm {
172
+
compatible = "ti,clockdomain";
173
+
clocks = <&sdrc_ick>, <&hsotgusb_ick_3430es2>;
174
+
};
175
+
176
+
wkup_clkdm: wkup_clkdm {
177
+
compatible = "ti,clockdomain";
178
+
clocks = <&gpio1_dbck>, <&wdt2_fck>, <&wdt2_ick>, <&wdt1_ick>,
179
+
<&gpio1_ick>, <&omap_32ksync_ick>, <&gpt12_ick>,
180
+
<&gpt1_ick>, <&usim_ick>;
181
+
};
182
+
183
+
core_l4_clkdm: core_l4_clkdm {
184
+
compatible = "ti,clockdomain";
185
+
clocks = <&cpefuse_fck>, <&ts_fck>, <&usbtll_fck>,
186
+
<&usbtll_ick>, <&mmchs3_ick>, <&mmchs3_fck>,
187
+
<&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
188
+
<&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
189
+
<&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
190
+
<&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
191
+
<&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
192
+
<&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
193
+
<&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
194
+
<&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
195
+
<&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>,
196
+
<&ssi_ick_3430es2>;
197
+
};
198
+
};
+5
arch/arm/boot/dts/omap36xx.dtsi
+5
arch/arm/boot/dts/omap36xx.dtsi
+1660
arch/arm/boot/dts/omap3xxx-clocks.dtsi
+1660
arch/arm/boot/dts/omap3xxx-clocks.dtsi
···
1
+
/*
2
+
* Device Tree Source for OMAP3 clock data
3
+
*
4
+
* Copyright (C) 2013 Texas Instruments, Inc.
5
+
*
6
+
* This program is free software; you can redistribute it and/or modify
7
+
* it under the terms of the GNU General Public License version 2 as
8
+
* published by the Free Software Foundation.
9
+
*/
10
+
&prm_clocks {
11
+
virt_16_8m_ck: virt_16_8m_ck {
12
+
#clock-cells = <0>;
13
+
compatible = "fixed-clock";
14
+
clock-frequency = <16800000>;
15
+
};
16
+
17
+
osc_sys_ck: osc_sys_ck {
18
+
#clock-cells = <0>;
19
+
compatible = "ti,mux-clock";
20
+
clocks = <&virt_12m_ck>, <&virt_13m_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_38_4m_ck>, <&virt_16_8m_ck>;
21
+
reg = <0x0d40>;
22
+
};
23
+
24
+
sys_ck: sys_ck {
25
+
#clock-cells = <0>;
26
+
compatible = "ti,divider-clock";
27
+
clocks = <&osc_sys_ck>;
28
+
ti,bit-shift = <6>;
29
+
ti,max-div = <3>;
30
+
reg = <0x1270>;
31
+
ti,index-starts-at-one;
32
+
};
33
+
34
+
sys_clkout1: sys_clkout1 {
35
+
#clock-cells = <0>;
36
+
compatible = "ti,gate-clock";
37
+
clocks = <&osc_sys_ck>;
38
+
reg = <0x0d70>;
39
+
ti,bit-shift = <7>;
40
+
};
41
+
42
+
dpll3_x2_ck: dpll3_x2_ck {
43
+
#clock-cells = <0>;
44
+
compatible = "fixed-factor-clock";
45
+
clocks = <&dpll3_ck>;
46
+
clock-mult = <2>;
47
+
clock-div = <1>;
48
+
};
49
+
50
+
dpll3_m2x2_ck: dpll3_m2x2_ck {
51
+
#clock-cells = <0>;
52
+
compatible = "fixed-factor-clock";
53
+
clocks = <&dpll3_m2_ck>;
54
+
clock-mult = <2>;
55
+
clock-div = <1>;
56
+
};
57
+
58
+
dpll4_x2_ck: dpll4_x2_ck {
59
+
#clock-cells = <0>;
60
+
compatible = "fixed-factor-clock";
61
+
clocks = <&dpll4_ck>;
62
+
clock-mult = <2>;
63
+
clock-div = <1>;
64
+
};
65
+
66
+
corex2_fck: corex2_fck {
67
+
#clock-cells = <0>;
68
+
compatible = "fixed-factor-clock";
69
+
clocks = <&dpll3_m2x2_ck>;
70
+
clock-mult = <1>;
71
+
clock-div = <1>;
72
+
};
73
+
74
+
wkup_l4_ick: wkup_l4_ick {
75
+
#clock-cells = <0>;
76
+
compatible = "fixed-factor-clock";
77
+
clocks = <&sys_ck>;
78
+
clock-mult = <1>;
79
+
clock-div = <1>;
80
+
};
81
+
};
82
+
&scrm_clocks {
83
+
mcbsp5_mux_fck: mcbsp5_mux_fck {
84
+
#clock-cells = <0>;
85
+
compatible = "ti,composite-mux-clock";
86
+
clocks = <&core_96m_fck>, <&mcbsp_clks>;
87
+
ti,bit-shift = <4>;
88
+
reg = <0x02d8>;
89
+
};
90
+
91
+
mcbsp5_fck: mcbsp5_fck {
92
+
#clock-cells = <0>;
93
+
compatible = "ti,composite-clock";
94
+
clocks = <&mcbsp5_gate_fck>, <&mcbsp5_mux_fck>;
95
+
};
96
+
97
+
mcbsp1_mux_fck: mcbsp1_mux_fck {
98
+
#clock-cells = <0>;
99
+
compatible = "ti,composite-mux-clock";
100
+
clocks = <&core_96m_fck>, <&mcbsp_clks>;
101
+
ti,bit-shift = <2>;
102
+
reg = <0x0274>;
103
+
};
104
+
105
+
mcbsp1_fck: mcbsp1_fck {
106
+
#clock-cells = <0>;
107
+
compatible = "ti,composite-clock";
108
+
clocks = <&mcbsp1_gate_fck>, <&mcbsp1_mux_fck>;
109
+
};
110
+
111
+
mcbsp2_mux_fck: mcbsp2_mux_fck {
112
+
#clock-cells = <0>;
113
+
compatible = "ti,composite-mux-clock";
114
+
clocks = <&per_96m_fck>, <&mcbsp_clks>;
115
+
ti,bit-shift = <6>;
116
+
reg = <0x0274>;
117
+
};
118
+
119
+
mcbsp2_fck: mcbsp2_fck {
120
+
#clock-cells = <0>;
121
+
compatible = "ti,composite-clock";
122
+
clocks = <&mcbsp2_gate_fck>, <&mcbsp2_mux_fck>;
123
+
};
124
+
125
+
mcbsp3_mux_fck: mcbsp3_mux_fck {
126
+
#clock-cells = <0>;
127
+
compatible = "ti,composite-mux-clock";
128
+
clocks = <&per_96m_fck>, <&mcbsp_clks>;
129
+
reg = <0x02d8>;
130
+
};
131
+
132
+
mcbsp3_fck: mcbsp3_fck {
133
+
#clock-cells = <0>;
134
+
compatible = "ti,composite-clock";
135
+
clocks = <&mcbsp3_gate_fck>, <&mcbsp3_mux_fck>;
136
+
};
137
+
138
+
mcbsp4_mux_fck: mcbsp4_mux_fck {
139
+
#clock-cells = <0>;
140
+
compatible = "ti,composite-mux-clock";
141
+
clocks = <&per_96m_fck>, <&mcbsp_clks>;
142
+
ti,bit-shift = <2>;
143
+
reg = <0x02d8>;
144
+
};
145
+
146
+
mcbsp4_fck: mcbsp4_fck {
147
+
#clock-cells = <0>;
148
+
compatible = "ti,composite-clock";
149
+
clocks = <&mcbsp4_gate_fck>, <&mcbsp4_mux_fck>;
150
+
};
151
+
};
152
+
&cm_clocks {
153
+
dummy_apb_pclk: dummy_apb_pclk {
154
+
#clock-cells = <0>;
155
+
compatible = "fixed-clock";
156
+
clock-frequency = <0x0>;
157
+
};
158
+
159
+
omap_32k_fck: omap_32k_fck {
160
+
#clock-cells = <0>;
161
+
compatible = "fixed-clock";
162
+
clock-frequency = <32768>;
163
+
};
164
+
165
+
virt_12m_ck: virt_12m_ck {
166
+
#clock-cells = <0>;
167
+
compatible = "fixed-clock";
168
+
clock-frequency = <12000000>;
169
+
};
170
+
171
+
virt_13m_ck: virt_13m_ck {
172
+
#clock-cells = <0>;
173
+
compatible = "fixed-clock";
174
+
clock-frequency = <13000000>;
175
+
};
176
+
177
+
virt_19200000_ck: virt_19200000_ck {
178
+
#clock-cells = <0>;
179
+
compatible = "fixed-clock";
180
+
clock-frequency = <19200000>;
181
+
};
182
+
183
+
virt_26000000_ck: virt_26000000_ck {
184
+
#clock-cells = <0>;
185
+
compatible = "fixed-clock";
186
+
clock-frequency = <26000000>;
187
+
};
188
+
189
+
virt_38_4m_ck: virt_38_4m_ck {
190
+
#clock-cells = <0>;
191
+
compatible = "fixed-clock";
192
+
clock-frequency = <38400000>;
193
+
};
194
+
195
+
dpll4_ck: dpll4_ck {
196
+
#clock-cells = <0>;
197
+
compatible = "ti,omap3-dpll-per-clock";
198
+
clocks = <&sys_ck>, <&sys_ck>;
199
+
reg = <0x0d00>, <0x0d20>, <0x0d44>, <0x0d30>;
200
+
};
201
+
202
+
dpll4_m2_ck: dpll4_m2_ck {
203
+
#clock-cells = <0>;
204
+
compatible = "ti,divider-clock";
205
+
clocks = <&dpll4_ck>;
206
+
ti,max-div = <63>;
207
+
reg = <0x0d48>;
208
+
ti,index-starts-at-one;
209
+
};
210
+
211
+
dpll4_m2x2_mul_ck: dpll4_m2x2_mul_ck {
212
+
#clock-cells = <0>;
213
+
compatible = "fixed-factor-clock";
214
+
clocks = <&dpll4_m2_ck>;
215
+
clock-mult = <2>;
216
+
clock-div = <1>;
217
+
};
218
+
219
+
dpll4_m2x2_ck: dpll4_m2x2_ck {
220
+
#clock-cells = <0>;
221
+
compatible = "ti,gate-clock";
222
+
clocks = <&dpll4_m2x2_mul_ck>;
223
+
ti,bit-shift = <0x1b>;
224
+
reg = <0x0d00>;
225
+
ti,set-bit-to-disable;
226
+
};
227
+
228
+
omap_96m_alwon_fck: omap_96m_alwon_fck {
229
+
#clock-cells = <0>;
230
+
compatible = "fixed-factor-clock";
231
+
clocks = <&dpll4_m2x2_ck>;
232
+
clock-mult = <1>;
233
+
clock-div = <1>;
234
+
};
235
+
236
+
dpll3_ck: dpll3_ck {
237
+
#clock-cells = <0>;
238
+
compatible = "ti,omap3-dpll-core-clock";
239
+
clocks = <&sys_ck>, <&sys_ck>;
240
+
reg = <0x0d00>, <0x0d20>, <0x0d40>, <0x0d30>;
241
+
};
242
+
243
+
dpll3_m3_ck: dpll3_m3_ck {
244
+
#clock-cells = <0>;
245
+
compatible = "ti,divider-clock";
246
+
clocks = <&dpll3_ck>;
247
+
ti,bit-shift = <16>;
248
+
ti,max-div = <31>;
249
+
reg = <0x1140>;
250
+
ti,index-starts-at-one;
251
+
};
252
+
253
+
dpll3_m3x2_mul_ck: dpll3_m3x2_mul_ck {
254
+
#clock-cells = <0>;
255
+
compatible = "fixed-factor-clock";
256
+
clocks = <&dpll3_m3_ck>;
257
+
clock-mult = <2>;
258
+
clock-div = <1>;
259
+
};
260
+
261
+
dpll3_m3x2_ck: dpll3_m3x2_ck {
262
+
#clock-cells = <0>;
263
+
compatible = "ti,gate-clock";
264
+
clocks = <&dpll3_m3x2_mul_ck>;
265
+
ti,bit-shift = <0xc>;
266
+
reg = <0x0d00>;
267
+
ti,set-bit-to-disable;
268
+
};
269
+
270
+
emu_core_alwon_ck: emu_core_alwon_ck {
271
+
#clock-cells = <0>;
272
+
compatible = "fixed-factor-clock";
273
+
clocks = <&dpll3_m3x2_ck>;
274
+
clock-mult = <1>;
275
+
clock-div = <1>;
276
+
};
277
+
278
+
sys_altclk: sys_altclk {
279
+
#clock-cells = <0>;
280
+
compatible = "fixed-clock";
281
+
clock-frequency = <0x0>;
282
+
};
283
+
284
+
mcbsp_clks: mcbsp_clks {
285
+
#clock-cells = <0>;
286
+
compatible = "fixed-clock";
287
+
clock-frequency = <0x0>;
288
+
};
289
+
290
+
dpll3_m2_ck: dpll3_m2_ck {
291
+
#clock-cells = <0>;
292
+
compatible = "ti,divider-clock";
293
+
clocks = <&dpll3_ck>;
294
+
ti,bit-shift = <27>;
295
+
ti,max-div = <31>;
296
+
reg = <0x0d40>;
297
+
ti,index-starts-at-one;
298
+
};
299
+
300
+
core_ck: core_ck {
301
+
#clock-cells = <0>;
302
+
compatible = "fixed-factor-clock";
303
+
clocks = <&dpll3_m2_ck>;
304
+
clock-mult = <1>;
305
+
clock-div = <1>;
306
+
};
307
+
308
+
dpll1_fck: dpll1_fck {
309
+
#clock-cells = <0>;
310
+
compatible = "ti,divider-clock";
311
+
clocks = <&core_ck>;
312
+
ti,bit-shift = <19>;
313
+
ti,max-div = <7>;
314
+
reg = <0x0940>;
315
+
ti,index-starts-at-one;
316
+
};
317
+
318
+
dpll1_ck: dpll1_ck {
319
+
#clock-cells = <0>;
320
+
compatible = "ti,omap3-dpll-clock";
321
+
clocks = <&sys_ck>, <&dpll1_fck>;
322
+
reg = <0x0904>, <0x0924>, <0x0940>, <0x0934>;
323
+
};
324
+
325
+
dpll1_x2_ck: dpll1_x2_ck {
326
+
#clock-cells = <0>;
327
+
compatible = "fixed-factor-clock";
328
+
clocks = <&dpll1_ck>;
329
+
clock-mult = <2>;
330
+
clock-div = <1>;
331
+
};
332
+
333
+
dpll1_x2m2_ck: dpll1_x2m2_ck {
334
+
#clock-cells = <0>;
335
+
compatible = "ti,divider-clock";
336
+
clocks = <&dpll1_x2_ck>;
337
+
ti,max-div = <31>;
338
+
reg = <0x0944>;
339
+
ti,index-starts-at-one;
340
+
};
341
+
342
+
cm_96m_fck: cm_96m_fck {
343
+
#clock-cells = <0>;
344
+
compatible = "fixed-factor-clock";
345
+
clocks = <&omap_96m_alwon_fck>;
346
+
clock-mult = <1>;
347
+
clock-div = <1>;
348
+
};
349
+
350
+
omap_96m_fck: omap_96m_fck {
351
+
#clock-cells = <0>;
352
+
compatible = "ti,mux-clock";
353
+
clocks = <&cm_96m_fck>, <&sys_ck>;
354
+
ti,bit-shift = <6>;
355
+
reg = <0x0d40>;
356
+
};
357
+
358
+
dpll4_m3_ck: dpll4_m3_ck {
359
+
#clock-cells = <0>;
360
+
compatible = "ti,divider-clock";
361
+
clocks = <&dpll4_ck>;
362
+
ti,bit-shift = <8>;
363
+
ti,max-div = <32>;
364
+
reg = <0x0e40>;
365
+
ti,index-starts-at-one;
366
+
};
367
+
368
+
dpll4_m3x2_mul_ck: dpll4_m3x2_mul_ck {
369
+
#clock-cells = <0>;
370
+
compatible = "fixed-factor-clock";
371
+
clocks = <&dpll4_m3_ck>;
372
+
clock-mult = <2>;
373
+
clock-div = <1>;
374
+
};
375
+
376
+
dpll4_m3x2_ck: dpll4_m3x2_ck {
377
+
#clock-cells = <0>;
378
+
compatible = "ti,gate-clock";
379
+
clocks = <&dpll4_m3x2_mul_ck>;
380
+
ti,bit-shift = <0x1c>;
381
+
reg = <0x0d00>;
382
+
ti,set-bit-to-disable;
383
+
};
384
+
385
+
omap_54m_fck: omap_54m_fck {
386
+
#clock-cells = <0>;
387
+
compatible = "ti,mux-clock";
388
+
clocks = <&dpll4_m3x2_ck>, <&sys_altclk>;
389
+
ti,bit-shift = <5>;
390
+
reg = <0x0d40>;
391
+
};
392
+
393
+
cm_96m_d2_fck: cm_96m_d2_fck {
394
+
#clock-cells = <0>;
395
+
compatible = "fixed-factor-clock";
396
+
clocks = <&cm_96m_fck>;
397
+
clock-mult = <1>;
398
+
clock-div = <2>;
399
+
};
400
+
401
+
omap_48m_fck: omap_48m_fck {
402
+
#clock-cells = <0>;
403
+
compatible = "ti,mux-clock";
404
+
clocks = <&cm_96m_d2_fck>, <&sys_altclk>;
405
+
ti,bit-shift = <3>;
406
+
reg = <0x0d40>;
407
+
};
408
+
409
+
omap_12m_fck: omap_12m_fck {
410
+
#clock-cells = <0>;
411
+
compatible = "fixed-factor-clock";
412
+
clocks = <&omap_48m_fck>;
413
+
clock-mult = <1>;
414
+
clock-div = <4>;
415
+
};
416
+
417
+
dpll4_m4_ck: dpll4_m4_ck {
418
+
#clock-cells = <0>;
419
+
compatible = "ti,divider-clock";
420
+
clocks = <&dpll4_ck>;
421
+
ti,max-div = <32>;
422
+
reg = <0x0e40>;
423
+
ti,index-starts-at-one;
424
+
};
425
+
426
+
dpll4_m4x2_mul_ck: dpll4_m4x2_mul_ck {
427
+
#clock-cells = <0>;
428
+
compatible = "fixed-factor-clock";
429
+
clocks = <&dpll4_m4_ck>;
430
+
clock-mult = <2>;
431
+
clock-div = <1>;
432
+
};
433
+
434
+
dpll4_m4x2_ck: dpll4_m4x2_ck {
435
+
#clock-cells = <0>;
436
+
compatible = "ti,gate-clock";
437
+
clocks = <&dpll4_m4x2_mul_ck>;
438
+
ti,bit-shift = <0x1d>;
439
+
reg = <0x0d00>;
440
+
ti,set-bit-to-disable;
441
+
};
442
+
443
+
dpll4_m5_ck: dpll4_m5_ck {
444
+
#clock-cells = <0>;
445
+
compatible = "ti,divider-clock";
446
+
clocks = <&dpll4_ck>;
447
+
ti,max-div = <63>;
448
+
reg = <0x0f40>;
449
+
ti,index-starts-at-one;
450
+
};
451
+
452
+
dpll4_m5x2_mul_ck: dpll4_m5x2_mul_ck {
453
+
#clock-cells = <0>;
454
+
compatible = "fixed-factor-clock";
455
+
clocks = <&dpll4_m5_ck>;
456
+
clock-mult = <2>;
457
+
clock-div = <1>;
458
+
};
459
+
460
+
dpll4_m5x2_ck: dpll4_m5x2_ck {
461
+
#clock-cells = <0>;
462
+
compatible = "ti,gate-clock";
463
+
clocks = <&dpll4_m5x2_mul_ck>;
464
+
ti,bit-shift = <0x1e>;
465
+
reg = <0x0d00>;
466
+
ti,set-bit-to-disable;
467
+
};
468
+
469
+
dpll4_m6_ck: dpll4_m6_ck {
470
+
#clock-cells = <0>;
471
+
compatible = "ti,divider-clock";
472
+
clocks = <&dpll4_ck>;
473
+
ti,bit-shift = <24>;
474
+
ti,max-div = <63>;
475
+
reg = <0x1140>;
476
+
ti,index-starts-at-one;
477
+
};
478
+
479
+
dpll4_m6x2_mul_ck: dpll4_m6x2_mul_ck {
480
+
#clock-cells = <0>;
481
+
compatible = "fixed-factor-clock";
482
+
clocks = <&dpll4_m6_ck>;
483
+
clock-mult = <2>;
484
+
clock-div = <1>;
485
+
};
486
+
487
+
dpll4_m6x2_ck: dpll4_m6x2_ck {
488
+
#clock-cells = <0>;
489
+
compatible = "ti,gate-clock";
490
+
clocks = <&dpll4_m6x2_mul_ck>;
491
+
ti,bit-shift = <0x1f>;
492
+
reg = <0x0d00>;
493
+
ti,set-bit-to-disable;
494
+
};
495
+
496
+
emu_per_alwon_ck: emu_per_alwon_ck {
497
+
#clock-cells = <0>;
498
+
compatible = "fixed-factor-clock";
499
+
clocks = <&dpll4_m6x2_ck>;
500
+
clock-mult = <1>;
501
+
clock-div = <1>;
502
+
};
503
+
504
+
clkout2_src_gate_ck: clkout2_src_gate_ck {
505
+
#clock-cells = <0>;
506
+
compatible = "ti,composite-no-wait-gate-clock";
507
+
clocks = <&core_ck>;
508
+
ti,bit-shift = <7>;
509
+
reg = <0x0d70>;
510
+
};
511
+
512
+
clkout2_src_mux_ck: clkout2_src_mux_ck {
513
+
#clock-cells = <0>;
514
+
compatible = "ti,composite-mux-clock";
515
+
clocks = <&core_ck>, <&sys_ck>, <&cm_96m_fck>, <&omap_54m_fck>;
516
+
reg = <0x0d70>;
517
+
};
518
+
519
+
clkout2_src_ck: clkout2_src_ck {
520
+
#clock-cells = <0>;
521
+
compatible = "ti,composite-clock";
522
+
clocks = <&clkout2_src_gate_ck>, <&clkout2_src_mux_ck>;
523
+
};
524
+
525
+
sys_clkout2: sys_clkout2 {
526
+
#clock-cells = <0>;
527
+
compatible = "ti,divider-clock";
528
+
clocks = <&clkout2_src_ck>;
529
+
ti,bit-shift = <3>;
530
+
ti,max-div = <64>;
531
+
reg = <0x0d70>;
532
+
ti,index-power-of-two;
533
+
};
534
+
535
+
mpu_ck: mpu_ck {
536
+
#clock-cells = <0>;
537
+
compatible = "fixed-factor-clock";
538
+
clocks = <&dpll1_x2m2_ck>;
539
+
clock-mult = <1>;
540
+
clock-div = <1>;
541
+
};
542
+
543
+
arm_fck: arm_fck {
544
+
#clock-cells = <0>;
545
+
compatible = "ti,divider-clock";
546
+
clocks = <&mpu_ck>;
547
+
reg = <0x0924>;
548
+
ti,max-div = <2>;
549
+
};
550
+
551
+
emu_mpu_alwon_ck: emu_mpu_alwon_ck {
552
+
#clock-cells = <0>;
553
+
compatible = "fixed-factor-clock";
554
+
clocks = <&mpu_ck>;
555
+
clock-mult = <1>;
556
+
clock-div = <1>;
557
+
};
558
+
559
+
l3_ick: l3_ick {
560
+
#clock-cells = <0>;
561
+
compatible = "ti,divider-clock";
562
+
clocks = <&core_ck>;
563
+
ti,max-div = <3>;
564
+
reg = <0x0a40>;
565
+
ti,index-starts-at-one;
566
+
};
567
+
568
+
l4_ick: l4_ick {
569
+
#clock-cells = <0>;
570
+
compatible = "ti,divider-clock";
571
+
clocks = <&l3_ick>;
572
+
ti,bit-shift = <2>;
573
+
ti,max-div = <3>;
574
+
reg = <0x0a40>;
575
+
ti,index-starts-at-one;
576
+
};
577
+
578
+
rm_ick: rm_ick {
579
+
#clock-cells = <0>;
580
+
compatible = "ti,divider-clock";
581
+
clocks = <&l4_ick>;
582
+
ti,bit-shift = <1>;
583
+
ti,max-div = <3>;
584
+
reg = <0x0c40>;
585
+
ti,index-starts-at-one;
586
+
};
587
+
588
+
gpt10_gate_fck: gpt10_gate_fck {
589
+
#clock-cells = <0>;
590
+
compatible = "ti,composite-gate-clock";
591
+
clocks = <&sys_ck>;
592
+
ti,bit-shift = <11>;
593
+
reg = <0x0a00>;
594
+
};
595
+
596
+
gpt10_mux_fck: gpt10_mux_fck {
597
+
#clock-cells = <0>;
598
+
compatible = "ti,composite-mux-clock";
599
+
clocks = <&omap_32k_fck>, <&sys_ck>;
600
+
ti,bit-shift = <6>;
601
+
reg = <0x0a40>;
602
+
};
603
+
604
+
gpt10_fck: gpt10_fck {
605
+
#clock-cells = <0>;
606
+
compatible = "ti,composite-clock";
607
+
clocks = <&gpt10_gate_fck>, <&gpt10_mux_fck>;
608
+
};
609
+
610
+
gpt11_gate_fck: gpt11_gate_fck {
611
+
#clock-cells = <0>;
612
+
compatible = "ti,composite-gate-clock";
613
+
clocks = <&sys_ck>;
614
+
ti,bit-shift = <12>;
615
+
reg = <0x0a00>;
616
+
};
617
+
618
+
gpt11_mux_fck: gpt11_mux_fck {
619
+
#clock-cells = <0>;
620
+
compatible = "ti,composite-mux-clock";
621
+
clocks = <&omap_32k_fck>, <&sys_ck>;
622
+
ti,bit-shift = <7>;
623
+
reg = <0x0a40>;
624
+
};
625
+
626
+
gpt11_fck: gpt11_fck {
627
+
#clock-cells = <0>;
628
+
compatible = "ti,composite-clock";
629
+
clocks = <&gpt11_gate_fck>, <&gpt11_mux_fck>;
630
+
};
631
+
632
+
core_96m_fck: core_96m_fck {
633
+
#clock-cells = <0>;
634
+
compatible = "fixed-factor-clock";
635
+
clocks = <&omap_96m_fck>;
636
+
clock-mult = <1>;
637
+
clock-div = <1>;
638
+
};
639
+
640
+
mmchs2_fck: mmchs2_fck {
641
+
#clock-cells = <0>;
642
+
compatible = "ti,wait-gate-clock";
643
+
clocks = <&core_96m_fck>;
644
+
reg = <0x0a00>;
645
+
ti,bit-shift = <25>;
646
+
};
647
+
648
+
mmchs1_fck: mmchs1_fck {
649
+
#clock-cells = <0>;
650
+
compatible = "ti,wait-gate-clock";
651
+
clocks = <&core_96m_fck>;
652
+
reg = <0x0a00>;
653
+
ti,bit-shift = <24>;
654
+
};
655
+
656
+
i2c3_fck: i2c3_fck {
657
+
#clock-cells = <0>;
658
+
compatible = "ti,wait-gate-clock";
659
+
clocks = <&core_96m_fck>;
660
+
reg = <0x0a00>;
661
+
ti,bit-shift = <17>;
662
+
};
663
+
664
+
i2c2_fck: i2c2_fck {
665
+
#clock-cells = <0>;
666
+
compatible = "ti,wait-gate-clock";
667
+
clocks = <&core_96m_fck>;
668
+
reg = <0x0a00>;
669
+
ti,bit-shift = <16>;
670
+
};
671
+
672
+
i2c1_fck: i2c1_fck {
673
+
#clock-cells = <0>;
674
+
compatible = "ti,wait-gate-clock";
675
+
clocks = <&core_96m_fck>;
676
+
reg = <0x0a00>;
677
+
ti,bit-shift = <15>;
678
+
};
679
+
680
+
mcbsp5_gate_fck: mcbsp5_gate_fck {
681
+
#clock-cells = <0>;
682
+
compatible = "ti,composite-gate-clock";
683
+
clocks = <&mcbsp_clks>;
684
+
ti,bit-shift = <10>;
685
+
reg = <0x0a00>;
686
+
};
687
+
688
+
mcbsp1_gate_fck: mcbsp1_gate_fck {
689
+
#clock-cells = <0>;
690
+
compatible = "ti,composite-gate-clock";
691
+
clocks = <&mcbsp_clks>;
692
+
ti,bit-shift = <9>;
693
+
reg = <0x0a00>;
694
+
};
695
+
696
+
core_48m_fck: core_48m_fck {
697
+
#clock-cells = <0>;
698
+
compatible = "fixed-factor-clock";
699
+
clocks = <&omap_48m_fck>;
700
+
clock-mult = <1>;
701
+
clock-div = <1>;
702
+
};
703
+
704
+
mcspi4_fck: mcspi4_fck {
705
+
#clock-cells = <0>;
706
+
compatible = "ti,wait-gate-clock";
707
+
clocks = <&core_48m_fck>;
708
+
reg = <0x0a00>;
709
+
ti,bit-shift = <21>;
710
+
};
711
+
712
+
mcspi3_fck: mcspi3_fck {
713
+
#clock-cells = <0>;
714
+
compatible = "ti,wait-gate-clock";
715
+
clocks = <&core_48m_fck>;
716
+
reg = <0x0a00>;
717
+
ti,bit-shift = <20>;
718
+
};
719
+
720
+
mcspi2_fck: mcspi2_fck {
721
+
#clock-cells = <0>;
722
+
compatible = "ti,wait-gate-clock";
723
+
clocks = <&core_48m_fck>;
724
+
reg = <0x0a00>;
725
+
ti,bit-shift = <19>;
726
+
};
727
+
728
+
mcspi1_fck: mcspi1_fck {
729
+
#clock-cells = <0>;
730
+
compatible = "ti,wait-gate-clock";
731
+
clocks = <&core_48m_fck>;
732
+
reg = <0x0a00>;
733
+
ti,bit-shift = <18>;
734
+
};
735
+
736
+
uart2_fck: uart2_fck {
737
+
#clock-cells = <0>;
738
+
compatible = "ti,wait-gate-clock";
739
+
clocks = <&core_48m_fck>;
740
+
reg = <0x0a00>;
741
+
ti,bit-shift = <14>;
742
+
};
743
+
744
+
uart1_fck: uart1_fck {
745
+
#clock-cells = <0>;
746
+
compatible = "ti,wait-gate-clock";
747
+
clocks = <&core_48m_fck>;
748
+
reg = <0x0a00>;
749
+
ti,bit-shift = <13>;
750
+
};
751
+
752
+
core_12m_fck: core_12m_fck {
753
+
#clock-cells = <0>;
754
+
compatible = "fixed-factor-clock";
755
+
clocks = <&omap_12m_fck>;
756
+
clock-mult = <1>;
757
+
clock-div = <1>;
758
+
};
759
+
760
+
hdq_fck: hdq_fck {
761
+
#clock-cells = <0>;
762
+
compatible = "ti,wait-gate-clock";
763
+
clocks = <&core_12m_fck>;
764
+
reg = <0x0a00>;
765
+
ti,bit-shift = <22>;
766
+
};
767
+
768
+
core_l3_ick: core_l3_ick {
769
+
#clock-cells = <0>;
770
+
compatible = "fixed-factor-clock";
771
+
clocks = <&l3_ick>;
772
+
clock-mult = <1>;
773
+
clock-div = <1>;
774
+
};
775
+
776
+
sdrc_ick: sdrc_ick {
777
+
#clock-cells = <0>;
778
+
compatible = "ti,wait-gate-clock";
779
+
clocks = <&core_l3_ick>;
780
+
reg = <0x0a10>;
781
+
ti,bit-shift = <1>;
782
+
};
783
+
784
+
gpmc_fck: gpmc_fck {
785
+
#clock-cells = <0>;
786
+
compatible = "fixed-factor-clock";
787
+
clocks = <&core_l3_ick>;
788
+
clock-mult = <1>;
789
+
clock-div = <1>;
790
+
};
791
+
792
+
core_l4_ick: core_l4_ick {
793
+
#clock-cells = <0>;
794
+
compatible = "fixed-factor-clock";
795
+
clocks = <&l4_ick>;
796
+
clock-mult = <1>;
797
+
clock-div = <1>;
798
+
};
799
+
800
+
mmchs2_ick: mmchs2_ick {
801
+
#clock-cells = <0>;
802
+
compatible = "ti,omap3-interface-clock";
803
+
clocks = <&core_l4_ick>;
804
+
reg = <0x0a10>;
805
+
ti,bit-shift = <25>;
806
+
};
807
+
808
+
mmchs1_ick: mmchs1_ick {
809
+
#clock-cells = <0>;
810
+
compatible = "ti,omap3-interface-clock";
811
+
clocks = <&core_l4_ick>;
812
+
reg = <0x0a10>;
813
+
ti,bit-shift = <24>;
814
+
};
815
+
816
+
hdq_ick: hdq_ick {
817
+
#clock-cells = <0>;
818
+
compatible = "ti,omap3-interface-clock";
819
+
clocks = <&core_l4_ick>;
820
+
reg = <0x0a10>;
821
+
ti,bit-shift = <22>;
822
+
};
823
+
824
+
mcspi4_ick: mcspi4_ick {
825
+
#clock-cells = <0>;
826
+
compatible = "ti,omap3-interface-clock";
827
+
clocks = <&core_l4_ick>;
828
+
reg = <0x0a10>;
829
+
ti,bit-shift = <21>;
830
+
};
831
+
832
+
mcspi3_ick: mcspi3_ick {
833
+
#clock-cells = <0>;
834
+
compatible = "ti,omap3-interface-clock";
835
+
clocks = <&core_l4_ick>;
836
+
reg = <0x0a10>;
837
+
ti,bit-shift = <20>;
838
+
};
839
+
840
+
mcspi2_ick: mcspi2_ick {
841
+
#clock-cells = <0>;
842
+
compatible = "ti,omap3-interface-clock";
843
+
clocks = <&core_l4_ick>;
844
+
reg = <0x0a10>;
845
+
ti,bit-shift = <19>;
846
+
};
847
+
848
+
mcspi1_ick: mcspi1_ick {
849
+
#clock-cells = <0>;
850
+
compatible = "ti,omap3-interface-clock";
851
+
clocks = <&core_l4_ick>;
852
+
reg = <0x0a10>;
853
+
ti,bit-shift = <18>;
854
+
};
855
+
856
+
i2c3_ick: i2c3_ick {
857
+
#clock-cells = <0>;
858
+
compatible = "ti,omap3-interface-clock";
859
+
clocks = <&core_l4_ick>;
860
+
reg = <0x0a10>;
861
+
ti,bit-shift = <17>;
862
+
};
863
+
864
+
i2c2_ick: i2c2_ick {
865
+
#clock-cells = <0>;
866
+
compatible = "ti,omap3-interface-clock";
867
+
clocks = <&core_l4_ick>;
868
+
reg = <0x0a10>;
869
+
ti,bit-shift = <16>;
870
+
};
871
+
872
+
i2c1_ick: i2c1_ick {
873
+
#clock-cells = <0>;
874
+
compatible = "ti,omap3-interface-clock";
875
+
clocks = <&core_l4_ick>;
876
+
reg = <0x0a10>;
877
+
ti,bit-shift = <15>;
878
+
};
879
+
880
+
uart2_ick: uart2_ick {
881
+
#clock-cells = <0>;
882
+
compatible = "ti,omap3-interface-clock";
883
+
clocks = <&core_l4_ick>;
884
+
reg = <0x0a10>;
885
+
ti,bit-shift = <14>;
886
+
};
887
+
888
+
uart1_ick: uart1_ick {
889
+
#clock-cells = <0>;
890
+
compatible = "ti,omap3-interface-clock";
891
+
clocks = <&core_l4_ick>;
892
+
reg = <0x0a10>;
893
+
ti,bit-shift = <13>;
894
+
};
895
+
896
+
gpt11_ick: gpt11_ick {
897
+
#clock-cells = <0>;
898
+
compatible = "ti,omap3-interface-clock";
899
+
clocks = <&core_l4_ick>;
900
+
reg = <0x0a10>;
901
+
ti,bit-shift = <12>;
902
+
};
903
+
904
+
gpt10_ick: gpt10_ick {
905
+
#clock-cells = <0>;
906
+
compatible = "ti,omap3-interface-clock";
907
+
clocks = <&core_l4_ick>;
908
+
reg = <0x0a10>;
909
+
ti,bit-shift = <11>;
910
+
};
911
+
912
+
mcbsp5_ick: mcbsp5_ick {
913
+
#clock-cells = <0>;
914
+
compatible = "ti,omap3-interface-clock";
915
+
clocks = <&core_l4_ick>;
916
+
reg = <0x0a10>;
917
+
ti,bit-shift = <10>;
918
+
};
919
+
920
+
mcbsp1_ick: mcbsp1_ick {
921
+
#clock-cells = <0>;
922
+
compatible = "ti,omap3-interface-clock";
923
+
clocks = <&core_l4_ick>;
924
+
reg = <0x0a10>;
925
+
ti,bit-shift = <9>;
926
+
};
927
+
928
+
omapctrl_ick: omapctrl_ick {
929
+
#clock-cells = <0>;
930
+
compatible = "ti,omap3-interface-clock";
931
+
clocks = <&core_l4_ick>;
932
+
reg = <0x0a10>;
933
+
ti,bit-shift = <6>;
934
+
};
935
+
936
+
dss_tv_fck: dss_tv_fck {
937
+
#clock-cells = <0>;
938
+
compatible = "ti,gate-clock";
939
+
clocks = <&omap_54m_fck>;
940
+
reg = <0x0e00>;
941
+
ti,bit-shift = <2>;
942
+
};
943
+
944
+
dss_96m_fck: dss_96m_fck {
945
+
#clock-cells = <0>;
946
+
compatible = "ti,gate-clock";
947
+
clocks = <&omap_96m_fck>;
948
+
reg = <0x0e00>;
949
+
ti,bit-shift = <2>;
950
+
};
951
+
952
+
dss2_alwon_fck: dss2_alwon_fck {
953
+
#clock-cells = <0>;
954
+
compatible = "ti,gate-clock";
955
+
clocks = <&sys_ck>;
956
+
reg = <0x0e00>;
957
+
ti,bit-shift = <1>;
958
+
};
959
+
960
+
dummy_ck: dummy_ck {
961
+
#clock-cells = <0>;
962
+
compatible = "fixed-clock";
963
+
clock-frequency = <0>;
964
+
};
965
+
966
+
gpt1_gate_fck: gpt1_gate_fck {
967
+
#clock-cells = <0>;
968
+
compatible = "ti,composite-gate-clock";
969
+
clocks = <&sys_ck>;
970
+
ti,bit-shift = <0>;
971
+
reg = <0x0c00>;
972
+
};
973
+
974
+
gpt1_mux_fck: gpt1_mux_fck {
975
+
#clock-cells = <0>;
976
+
compatible = "ti,composite-mux-clock";
977
+
clocks = <&omap_32k_fck>, <&sys_ck>;
978
+
reg = <0x0c40>;
979
+
};
980
+
981
+
gpt1_fck: gpt1_fck {
982
+
#clock-cells = <0>;
983
+
compatible = "ti,composite-clock";
984
+
clocks = <&gpt1_gate_fck>, <&gpt1_mux_fck>;
985
+
};
986
+
987
+
aes2_ick: aes2_ick {
988
+
#clock-cells = <0>;
989
+
compatible = "ti,omap3-interface-clock";
990
+
clocks = <&core_l4_ick>;
991
+
ti,bit-shift = <28>;
992
+
reg = <0x0a10>;
993
+
};
994
+
995
+
wkup_32k_fck: wkup_32k_fck {
996
+
#clock-cells = <0>;
997
+
compatible = "fixed-factor-clock";
998
+
clocks = <&omap_32k_fck>;
999
+
clock-mult = <1>;
1000
+
clock-div = <1>;
1001
+
};
1002
+
1003
+
gpio1_dbck: gpio1_dbck {
1004
+
#clock-cells = <0>;
1005
+
compatible = "ti,gate-clock";
1006
+
clocks = <&wkup_32k_fck>;
1007
+
reg = <0x0c00>;
1008
+
ti,bit-shift = <3>;
1009
+
};
1010
+
1011
+
sha12_ick: sha12_ick {
1012
+
#clock-cells = <0>;
1013
+
compatible = "ti,omap3-interface-clock";
1014
+
clocks = <&core_l4_ick>;
1015
+
reg = <0x0a10>;
1016
+
ti,bit-shift = <27>;
1017
+
};
1018
+
1019
+
wdt2_fck: wdt2_fck {
1020
+
#clock-cells = <0>;
1021
+
compatible = "ti,wait-gate-clock";
1022
+
clocks = <&wkup_32k_fck>;
1023
+
reg = <0x0c00>;
1024
+
ti,bit-shift = <5>;
1025
+
};
1026
+
1027
+
wdt2_ick: wdt2_ick {
1028
+
#clock-cells = <0>;
1029
+
compatible = "ti,omap3-interface-clock";
1030
+
clocks = <&wkup_l4_ick>;
1031
+
reg = <0x0c10>;
1032
+
ti,bit-shift = <5>;
1033
+
};
1034
+
1035
+
wdt1_ick: wdt1_ick {
1036
+
#clock-cells = <0>;
1037
+
compatible = "ti,omap3-interface-clock";
1038
+
clocks = <&wkup_l4_ick>;
1039
+
reg = <0x0c10>;
1040
+
ti,bit-shift = <4>;
1041
+
};
1042
+
1043
+
gpio1_ick: gpio1_ick {
1044
+
#clock-cells = <0>;
1045
+
compatible = "ti,omap3-interface-clock";
1046
+
clocks = <&wkup_l4_ick>;
1047
+
reg = <0x0c10>;
1048
+
ti,bit-shift = <3>;
1049
+
};
1050
+
1051
+
omap_32ksync_ick: omap_32ksync_ick {
1052
+
#clock-cells = <0>;
1053
+
compatible = "ti,omap3-interface-clock";
1054
+
clocks = <&wkup_l4_ick>;
1055
+
reg = <0x0c10>;
1056
+
ti,bit-shift = <2>;
1057
+
};
1058
+
1059
+
gpt12_ick: gpt12_ick {
1060
+
#clock-cells = <0>;
1061
+
compatible = "ti,omap3-interface-clock";
1062
+
clocks = <&wkup_l4_ick>;
1063
+
reg = <0x0c10>;
1064
+
ti,bit-shift = <1>;
1065
+
};
1066
+
1067
+
gpt1_ick: gpt1_ick {
1068
+
#clock-cells = <0>;
1069
+
compatible = "ti,omap3-interface-clock";
1070
+
clocks = <&wkup_l4_ick>;
1071
+
reg = <0x0c10>;
1072
+
ti,bit-shift = <0>;
1073
+
};
1074
+
1075
+
per_96m_fck: per_96m_fck {
1076
+
#clock-cells = <0>;
1077
+
compatible = "fixed-factor-clock";
1078
+
clocks = <&omap_96m_alwon_fck>;
1079
+
clock-mult = <1>;
1080
+
clock-div = <1>;
1081
+
};
1082
+
1083
+
per_48m_fck: per_48m_fck {
1084
+
#clock-cells = <0>;
1085
+
compatible = "fixed-factor-clock";
1086
+
clocks = <&omap_48m_fck>;
1087
+
clock-mult = <1>;
1088
+
clock-div = <1>;
1089
+
};
1090
+
1091
+
uart3_fck: uart3_fck {
1092
+
#clock-cells = <0>;
1093
+
compatible = "ti,wait-gate-clock";
1094
+
clocks = <&per_48m_fck>;
1095
+
reg = <0x1000>;
1096
+
ti,bit-shift = <11>;
1097
+
};
1098
+
1099
+
gpt2_gate_fck: gpt2_gate_fck {
1100
+
#clock-cells = <0>;
1101
+
compatible = "ti,composite-gate-clock";
1102
+
clocks = <&sys_ck>;
1103
+
ti,bit-shift = <3>;
1104
+
reg = <0x1000>;
1105
+
};
1106
+
1107
+
gpt2_mux_fck: gpt2_mux_fck {
1108
+
#clock-cells = <0>;
1109
+
compatible = "ti,composite-mux-clock";
1110
+
clocks = <&omap_32k_fck>, <&sys_ck>;
1111
+
reg = <0x1040>;
1112
+
};
1113
+
1114
+
gpt2_fck: gpt2_fck {
1115
+
#clock-cells = <0>;
1116
+
compatible = "ti,composite-clock";
1117
+
clocks = <&gpt2_gate_fck>, <&gpt2_mux_fck>;
1118
+
};
1119
+
1120
+
gpt3_gate_fck: gpt3_gate_fck {
1121
+
#clock-cells = <0>;
1122
+
compatible = "ti,composite-gate-clock";
1123
+
clocks = <&sys_ck>;
1124
+
ti,bit-shift = <4>;
1125
+
reg = <0x1000>;
1126
+
};
1127
+
1128
+
gpt3_mux_fck: gpt3_mux_fck {
1129
+
#clock-cells = <0>;
1130
+
compatible = "ti,composite-mux-clock";
1131
+
clocks = <&omap_32k_fck>, <&sys_ck>;
1132
+
ti,bit-shift = <1>;
1133
+
reg = <0x1040>;
1134
+
};
1135
+
1136
+
gpt3_fck: gpt3_fck {
1137
+
#clock-cells = <0>;
1138
+
compatible = "ti,composite-clock";
1139
+
clocks = <&gpt3_gate_fck>, <&gpt3_mux_fck>;
1140
+
};
1141
+
1142
+
gpt4_gate_fck: gpt4_gate_fck {
1143
+
#clock-cells = <0>;
1144
+
compatible = "ti,composite-gate-clock";
1145
+
clocks = <&sys_ck>;
1146
+
ti,bit-shift = <5>;
1147
+
reg = <0x1000>;
1148
+
};
1149
+
1150
+
gpt4_mux_fck: gpt4_mux_fck {
1151
+
#clock-cells = <0>;
1152
+
compatible = "ti,composite-mux-clock";
1153
+
clocks = <&omap_32k_fck>, <&sys_ck>;
1154
+
ti,bit-shift = <2>;
1155
+
reg = <0x1040>;
1156
+
};
1157
+
1158
+
gpt4_fck: gpt4_fck {
1159
+
#clock-cells = <0>;
1160
+
compatible = "ti,composite-clock";
1161
+
clocks = <&gpt4_gate_fck>, <&gpt4_mux_fck>;
1162
+
};
1163
+
1164
+
gpt5_gate_fck: gpt5_gate_fck {
1165
+
#clock-cells = <0>;
1166
+
compatible = "ti,composite-gate-clock";
1167
+
clocks = <&sys_ck>;
1168
+
ti,bit-shift = <6>;
1169
+
reg = <0x1000>;
1170
+
};
1171
+
1172
+
gpt5_mux_fck: gpt5_mux_fck {
1173
+
#clock-cells = <0>;
1174
+
compatible = "ti,composite-mux-clock";
1175
+
clocks = <&omap_32k_fck>, <&sys_ck>;
1176
+
ti,bit-shift = <3>;
1177
+
reg = <0x1040>;
1178
+
};
1179
+
1180
+
gpt5_fck: gpt5_fck {
1181
+
#clock-cells = <0>;
1182
+
compatible = "ti,composite-clock";
1183
+
clocks = <&gpt5_gate_fck>, <&gpt5_mux_fck>;
1184
+
};
1185
+
1186
+
gpt6_gate_fck: gpt6_gate_fck {
1187
+
#clock-cells = <0>;
1188
+
compatible = "ti,composite-gate-clock";
1189
+
clocks = <&sys_ck>;
1190
+
ti,bit-shift = <7>;
1191
+
reg = <0x1000>;
1192
+
};
1193
+
1194
+
gpt6_mux_fck: gpt6_mux_fck {
1195
+
#clock-cells = <0>;
1196
+
compatible = "ti,composite-mux-clock";
1197
+
clocks = <&omap_32k_fck>, <&sys_ck>;
1198
+
ti,bit-shift = <4>;
1199
+
reg = <0x1040>;
1200
+
};
1201
+
1202
+
gpt6_fck: gpt6_fck {
1203
+
#clock-cells = <0>;
1204
+
compatible = "ti,composite-clock";
1205
+
clocks = <&gpt6_gate_fck>, <&gpt6_mux_fck>;
1206
+
};
1207
+
1208
+
gpt7_gate_fck: gpt7_gate_fck {
1209
+
#clock-cells = <0>;
1210
+
compatible = "ti,composite-gate-clock";
1211
+
clocks = <&sys_ck>;
1212
+
ti,bit-shift = <8>;
1213
+
reg = <0x1000>;
1214
+
};
1215
+
1216
+
gpt7_mux_fck: gpt7_mux_fck {
1217
+
#clock-cells = <0>;
1218
+
compatible = "ti,composite-mux-clock";
1219
+
clocks = <&omap_32k_fck>, <&sys_ck>;
1220
+
ti,bit-shift = <5>;
1221
+
reg = <0x1040>;
1222
+
};
1223
+
1224
+
gpt7_fck: gpt7_fck {
1225
+
#clock-cells = <0>;
1226
+
compatible = "ti,composite-clock";
1227
+
clocks = <&gpt7_gate_fck>, <&gpt7_mux_fck>;
1228
+
};
1229
+
1230
+
gpt8_gate_fck: gpt8_gate_fck {
1231
+
#clock-cells = <0>;
1232
+
compatible = "ti,composite-gate-clock";
1233
+
clocks = <&sys_ck>;
1234
+
ti,bit-shift = <9>;
1235
+
reg = <0x1000>;
1236
+
};
1237
+
1238
+
gpt8_mux_fck: gpt8_mux_fck {
1239
+
#clock-cells = <0>;
1240
+
compatible = "ti,composite-mux-clock";
1241
+
clocks = <&omap_32k_fck>, <&sys_ck>;
1242
+
ti,bit-shift = <6>;
1243
+
reg = <0x1040>;
1244
+
};
1245
+
1246
+
gpt8_fck: gpt8_fck {
1247
+
#clock-cells = <0>;
1248
+
compatible = "ti,composite-clock";
1249
+
clocks = <&gpt8_gate_fck>, <&gpt8_mux_fck>;
1250
+
};
1251
+
1252
+
gpt9_gate_fck: gpt9_gate_fck {
1253
+
#clock-cells = <0>;
1254
+
compatible = "ti,composite-gate-clock";
1255
+
clocks = <&sys_ck>;
1256
+
ti,bit-shift = <10>;
1257
+
reg = <0x1000>;
1258
+
};
1259
+
1260
+
gpt9_mux_fck: gpt9_mux_fck {
1261
+
#clock-cells = <0>;
1262
+
compatible = "ti,composite-mux-clock";
1263
+
clocks = <&omap_32k_fck>, <&sys_ck>;
1264
+
ti,bit-shift = <7>;
1265
+
reg = <0x1040>;
1266
+
};
1267
+
1268
+
gpt9_fck: gpt9_fck {
1269
+
#clock-cells = <0>;
1270
+
compatible = "ti,composite-clock";
1271
+
clocks = <&gpt9_gate_fck>, <&gpt9_mux_fck>;
1272
+
};
1273
+
1274
+
per_32k_alwon_fck: per_32k_alwon_fck {
1275
+
#clock-cells = <0>;
1276
+
compatible = "fixed-factor-clock";
1277
+
clocks = <&omap_32k_fck>;
1278
+
clock-mult = <1>;
1279
+
clock-div = <1>;
1280
+
};
1281
+
1282
+
gpio6_dbck: gpio6_dbck {
1283
+
#clock-cells = <0>;
1284
+
compatible = "ti,gate-clock";
1285
+
clocks = <&per_32k_alwon_fck>;
1286
+
reg = <0x1000>;
1287
+
ti,bit-shift = <17>;
1288
+
};
1289
+
1290
+
gpio5_dbck: gpio5_dbck {
1291
+
#clock-cells = <0>;
1292
+
compatible = "ti,gate-clock";
1293
+
clocks = <&per_32k_alwon_fck>;
1294
+
reg = <0x1000>;
1295
+
ti,bit-shift = <16>;
1296
+
};
1297
+
1298
+
gpio4_dbck: gpio4_dbck {
1299
+
#clock-cells = <0>;
1300
+
compatible = "ti,gate-clock";
1301
+
clocks = <&per_32k_alwon_fck>;
1302
+
reg = <0x1000>;
1303
+
ti,bit-shift = <15>;
1304
+
};
1305
+
1306
+
gpio3_dbck: gpio3_dbck {
1307
+
#clock-cells = <0>;
1308
+
compatible = "ti,gate-clock";
1309
+
clocks = <&per_32k_alwon_fck>;
1310
+
reg = <0x1000>;
1311
+
ti,bit-shift = <14>;
1312
+
};
1313
+
1314
+
gpio2_dbck: gpio2_dbck {
1315
+
#clock-cells = <0>;
1316
+
compatible = "ti,gate-clock";
1317
+
clocks = <&per_32k_alwon_fck>;
1318
+
reg = <0x1000>;
1319
+
ti,bit-shift = <13>;
1320
+
};
1321
+
1322
+
wdt3_fck: wdt3_fck {
1323
+
#clock-cells = <0>;
1324
+
compatible = "ti,wait-gate-clock";
1325
+
clocks = <&per_32k_alwon_fck>;
1326
+
reg = <0x1000>;
1327
+
ti,bit-shift = <12>;
1328
+
};
1329
+
1330
+
per_l4_ick: per_l4_ick {
1331
+
#clock-cells = <0>;
1332
+
compatible = "fixed-factor-clock";
1333
+
clocks = <&l4_ick>;
1334
+
clock-mult = <1>;
1335
+
clock-div = <1>;
1336
+
};
1337
+
1338
+
gpio6_ick: gpio6_ick {
1339
+
#clock-cells = <0>;
1340
+
compatible = "ti,omap3-interface-clock";
1341
+
clocks = <&per_l4_ick>;
1342
+
reg = <0x1010>;
1343
+
ti,bit-shift = <17>;
1344
+
};
1345
+
1346
+
gpio5_ick: gpio5_ick {
1347
+
#clock-cells = <0>;
1348
+
compatible = "ti,omap3-interface-clock";
1349
+
clocks = <&per_l4_ick>;
1350
+
reg = <0x1010>;
1351
+
ti,bit-shift = <16>;
1352
+
};
1353
+
1354
+
gpio4_ick: gpio4_ick {
1355
+
#clock-cells = <0>;
1356
+
compatible = "ti,omap3-interface-clock";
1357
+
clocks = <&per_l4_ick>;
1358
+
reg = <0x1010>;
1359
+
ti,bit-shift = <15>;
1360
+
};
1361
+
1362
+
gpio3_ick: gpio3_ick {
1363
+
#clock-cells = <0>;
1364
+
compatible = "ti,omap3-interface-clock";
1365
+
clocks = <&per_l4_ick>;
1366
+
reg = <0x1010>;
1367
+
ti,bit-shift = <14>;
1368
+
};
1369
+
1370
+
gpio2_ick: gpio2_ick {
1371
+
#clock-cells = <0>;
1372
+
compatible = "ti,omap3-interface-clock";
1373
+
clocks = <&per_l4_ick>;
1374
+
reg = <0x1010>;
1375
+
ti,bit-shift = <13>;
1376
+
};
1377
+
1378
+
wdt3_ick: wdt3_ick {
1379
+
#clock-cells = <0>;
1380
+
compatible = "ti,omap3-interface-clock";
1381
+
clocks = <&per_l4_ick>;
1382
+
reg = <0x1010>;
1383
+
ti,bit-shift = <12>;
1384
+
};
1385
+
1386
+
uart3_ick: uart3_ick {
1387
+
#clock-cells = <0>;
1388
+
compatible = "ti,omap3-interface-clock";
1389
+
clocks = <&per_l4_ick>;
1390
+
reg = <0x1010>;
1391
+
ti,bit-shift = <11>;
1392
+
};
1393
+
1394
+
uart4_ick: uart4_ick {
1395
+
#clock-cells = <0>;
1396
+
compatible = "ti,omap3-interface-clock";
1397
+
clocks = <&per_l4_ick>;
1398
+
reg = <0x1010>;
1399
+
ti,bit-shift = <18>;
1400
+
};
1401
+
1402
+
gpt9_ick: gpt9_ick {
1403
+
#clock-cells = <0>;
1404
+
compatible = "ti,omap3-interface-clock";
1405
+
clocks = <&per_l4_ick>;
1406
+
reg = <0x1010>;
1407
+
ti,bit-shift = <10>;
1408
+
};
1409
+
1410
+
gpt8_ick: gpt8_ick {
1411
+
#clock-cells = <0>;
1412
+
compatible = "ti,omap3-interface-clock";
1413
+
clocks = <&per_l4_ick>;
1414
+
reg = <0x1010>;
1415
+
ti,bit-shift = <9>;
1416
+
};
1417
+
1418
+
gpt7_ick: gpt7_ick {
1419
+
#clock-cells = <0>;
1420
+
compatible = "ti,omap3-interface-clock";
1421
+
clocks = <&per_l4_ick>;
1422
+
reg = <0x1010>;
1423
+
ti,bit-shift = <8>;
1424
+
};
1425
+
1426
+
gpt6_ick: gpt6_ick {
1427
+
#clock-cells = <0>;
1428
+
compatible = "ti,omap3-interface-clock";
1429
+
clocks = <&per_l4_ick>;
1430
+
reg = <0x1010>;
1431
+
ti,bit-shift = <7>;
1432
+
};
1433
+
1434
+
gpt5_ick: gpt5_ick {
1435
+
#clock-cells = <0>;
1436
+
compatible = "ti,omap3-interface-clock";
1437
+
clocks = <&per_l4_ick>;
1438
+
reg = <0x1010>;
1439
+
ti,bit-shift = <6>;
1440
+
};
1441
+
1442
+
gpt4_ick: gpt4_ick {
1443
+
#clock-cells = <0>;
1444
+
compatible = "ti,omap3-interface-clock";
1445
+
clocks = <&per_l4_ick>;
1446
+
reg = <0x1010>;
1447
+
ti,bit-shift = <5>;
1448
+
};
1449
+
1450
+
gpt3_ick: gpt3_ick {
1451
+
#clock-cells = <0>;
1452
+
compatible = "ti,omap3-interface-clock";
1453
+
clocks = <&per_l4_ick>;
1454
+
reg = <0x1010>;
1455
+
ti,bit-shift = <4>;
1456
+
};
1457
+
1458
+
gpt2_ick: gpt2_ick {
1459
+
#clock-cells = <0>;
1460
+
compatible = "ti,omap3-interface-clock";
1461
+
clocks = <&per_l4_ick>;
1462
+
reg = <0x1010>;
1463
+
ti,bit-shift = <3>;
1464
+
};
1465
+
1466
+
mcbsp2_ick: mcbsp2_ick {
1467
+
#clock-cells = <0>;
1468
+
compatible = "ti,omap3-interface-clock";
1469
+
clocks = <&per_l4_ick>;
1470
+
reg = <0x1010>;
1471
+
ti,bit-shift = <0>;
1472
+
};
1473
+
1474
+
mcbsp3_ick: mcbsp3_ick {
1475
+
#clock-cells = <0>;
1476
+
compatible = "ti,omap3-interface-clock";
1477
+
clocks = <&per_l4_ick>;
1478
+
reg = <0x1010>;
1479
+
ti,bit-shift = <1>;
1480
+
};
1481
+
1482
+
mcbsp4_ick: mcbsp4_ick {
1483
+
#clock-cells = <0>;
1484
+
compatible = "ti,omap3-interface-clock";
1485
+
clocks = <&per_l4_ick>;
1486
+
reg = <0x1010>;
1487
+
ti,bit-shift = <2>;
1488
+
};
1489
+
1490
+
mcbsp2_gate_fck: mcbsp2_gate_fck {
1491
+
#clock-cells = <0>;
1492
+
compatible = "ti,composite-gate-clock";
1493
+
clocks = <&mcbsp_clks>;
1494
+
ti,bit-shift = <0>;
1495
+
reg = <0x1000>;
1496
+
};
1497
+
1498
+
mcbsp3_gate_fck: mcbsp3_gate_fck {
1499
+
#clock-cells = <0>;
1500
+
compatible = "ti,composite-gate-clock";
1501
+
clocks = <&mcbsp_clks>;
1502
+
ti,bit-shift = <1>;
1503
+
reg = <0x1000>;
1504
+
};
1505
+
1506
+
mcbsp4_gate_fck: mcbsp4_gate_fck {
1507
+
#clock-cells = <0>;
1508
+
compatible = "ti,composite-gate-clock";
1509
+
clocks = <&mcbsp_clks>;
1510
+
ti,bit-shift = <2>;
1511
+
reg = <0x1000>;
1512
+
};
1513
+
1514
+
emu_src_mux_ck: emu_src_mux_ck {
1515
+
#clock-cells = <0>;
1516
+
compatible = "ti,mux-clock";
1517
+
clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>;
1518
+
reg = <0x1140>;
1519
+
};
1520
+
1521
+
emu_src_ck: emu_src_ck {
1522
+
#clock-cells = <0>;
1523
+
compatible = "ti,clkdm-gate-clock";
1524
+
clocks = <&emu_src_mux_ck>;
1525
+
};
1526
+
1527
+
pclk_fck: pclk_fck {
1528
+
#clock-cells = <0>;
1529
+
compatible = "ti,divider-clock";
1530
+
clocks = <&emu_src_ck>;
1531
+
ti,bit-shift = <8>;
1532
+
ti,max-div = <7>;
1533
+
reg = <0x1140>;
1534
+
ti,index-starts-at-one;
1535
+
};
1536
+
1537
+
pclkx2_fck: pclkx2_fck {
1538
+
#clock-cells = <0>;
1539
+
compatible = "ti,divider-clock";
1540
+
clocks = <&emu_src_ck>;
1541
+
ti,bit-shift = <6>;
1542
+
ti,max-div = <3>;
1543
+
reg = <0x1140>;
1544
+
ti,index-starts-at-one;
1545
+
};
1546
+
1547
+
atclk_fck: atclk_fck {
1548
+
#clock-cells = <0>;
1549
+
compatible = "ti,divider-clock";
1550
+
clocks = <&emu_src_ck>;
1551
+
ti,bit-shift = <4>;
1552
+
ti,max-div = <3>;
1553
+
reg = <0x1140>;
1554
+
ti,index-starts-at-one;
1555
+
};
1556
+
1557
+
traceclk_src_fck: traceclk_src_fck {
1558
+
#clock-cells = <0>;
1559
+
compatible = "ti,mux-clock";
1560
+
clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>;
1561
+
ti,bit-shift = <2>;
1562
+
reg = <0x1140>;
1563
+
};
1564
+
1565
+
traceclk_fck: traceclk_fck {
1566
+
#clock-cells = <0>;
1567
+
compatible = "ti,divider-clock";
1568
+
clocks = <&traceclk_src_fck>;
1569
+
ti,bit-shift = <11>;
1570
+
ti,max-div = <7>;
1571
+
reg = <0x1140>;
1572
+
ti,index-starts-at-one;
1573
+
};
1574
+
1575
+
secure_32k_fck: secure_32k_fck {
1576
+
#clock-cells = <0>;
1577
+
compatible = "fixed-clock";
1578
+
clock-frequency = <32768>;
1579
+
};
1580
+
1581
+
gpt12_fck: gpt12_fck {
1582
+
#clock-cells = <0>;
1583
+
compatible = "fixed-factor-clock";
1584
+
clocks = <&secure_32k_fck>;
1585
+
clock-mult = <1>;
1586
+
clock-div = <1>;
1587
+
};
1588
+
1589
+
wdt1_fck: wdt1_fck {
1590
+
#clock-cells = <0>;
1591
+
compatible = "fixed-factor-clock";
1592
+
clocks = <&secure_32k_fck>;
1593
+
clock-mult = <1>;
1594
+
clock-div = <1>;
1595
+
};
1596
+
};
1597
+
1598
+
&cm_clockdomains {
1599
+
core_l3_clkdm: core_l3_clkdm {
1600
+
compatible = "ti,clockdomain";
1601
+
clocks = <&sdrc_ick>;
1602
+
};
1603
+
1604
+
dpll3_clkdm: dpll3_clkdm {
1605
+
compatible = "ti,clockdomain";
1606
+
clocks = <&dpll3_ck>;
1607
+
};
1608
+
1609
+
dpll1_clkdm: dpll1_clkdm {
1610
+
compatible = "ti,clockdomain";
1611
+
clocks = <&dpll1_ck>;
1612
+
};
1613
+
1614
+
per_clkdm: per_clkdm {
1615
+
compatible = "ti,clockdomain";
1616
+
clocks = <&uart3_fck>, <&gpio6_dbck>, <&gpio5_dbck>,
1617
+
<&gpio4_dbck>, <&gpio3_dbck>, <&gpio2_dbck>,
1618
+
<&wdt3_fck>, <&gpio6_ick>, <&gpio5_ick>, <&gpio4_ick>,
1619
+
<&gpio3_ick>, <&gpio2_ick>, <&wdt3_ick>, <&uart3_ick>,
1620
+
<&uart4_ick>, <&gpt9_ick>, <&gpt8_ick>, <&gpt7_ick>,
1621
+
<&gpt6_ick>, <&gpt5_ick>, <&gpt4_ick>, <&gpt3_ick>,
1622
+
<&gpt2_ick>, <&mcbsp2_ick>, <&mcbsp3_ick>,
1623
+
<&mcbsp4_ick>;
1624
+
};
1625
+
1626
+
emu_clkdm: emu_clkdm {
1627
+
compatible = "ti,clockdomain";
1628
+
clocks = <&emu_src_ck>;
1629
+
};
1630
+
1631
+
dpll4_clkdm: dpll4_clkdm {
1632
+
compatible = "ti,clockdomain";
1633
+
clocks = <&dpll4_ck>;
1634
+
};
1635
+
1636
+
wkup_clkdm: wkup_clkdm {
1637
+
compatible = "ti,clockdomain";
1638
+
clocks = <&gpio1_dbck>, <&wdt2_fck>, <&wdt2_ick>, <&wdt1_ick>,
1639
+
<&gpio1_ick>, <&omap_32ksync_ick>, <&gpt12_ick>,
1640
+
<&gpt1_ick>;
1641
+
};
1642
+
1643
+
dss_clkdm: dss_clkdm {
1644
+
compatible = "ti,clockdomain";
1645
+
clocks = <&dss_tv_fck>, <&dss_96m_fck>, <&dss2_alwon_fck>;
1646
+
};
1647
+
1648
+
core_l4_clkdm: core_l4_clkdm {
1649
+
compatible = "ti,clockdomain";
1650
+
clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
1651
+
<&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
1652
+
<&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
1653
+
<&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
1654
+
<&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
1655
+
<&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
1656
+
<&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
1657
+
<&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
1658
+
<&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>;
1659
+
};
1660
+
};