Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

Merge tag 'mips_6.7' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux

Pull MIPS updates from Thomas Bogendoerfer:

- removed AR7 platform support

- cleanups and fixes

* tag 'mips_6.7' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux:
MIPS: AR7: remove platform
watchdog: ar7_wdt: remove driver to prepare for platform removal
vlynq: remove bus driver
mtd: parsers: ar7: remove support
serial: 8250: remove AR7 support
arch: mips: remove ReiserFS from defconfig
MIPS: lantiq: Remove unnecessary include of <linux/of_irq.h>
MIPS: lantiq: Fix pcibios_plat_dev_init() "no previous prototype" warning
MIPS: KVM: Fix a build warning about variable set but not used
MIPS: Remove dead code in relocate_new_kernel
mips: dts: ralink: mt7621: rename to GnuBee GB-PC1 and GnuBee GB-PC2
mips: dts: ralink: mt7621: define each reset as an item
mips: dts: ingenic: Remove unneeded probe-type properties
MIPS: loongson32: Remove dma.h and nand.h

+5 -4033
-7
MAINTAINERS
··· 23198 23198 T: git git://linuxtv.org/media_tree.git 23199 23199 F: drivers/media/test-drivers/vivid/* 23200 23200 23201 - VLYNQ BUS 23202 - M: Florian Fainelli <f.fainelli@gmail.com> 23203 - L: openwrt-devel@lists.openwrt.org (subscribers-only) 23204 - S: Maintained 23205 - F: drivers/vlynq/vlynq.c 23206 - F: include/linux/vlynq.h 23207 - 23208 23201 VM SOCKETS (AF_VSOCK) 23209 23202 M: Stefano Garzarella <sgarzare@redhat.com> 23210 23203 L: virtualization@lists.linux.dev
-1
arch/arm/configs/pxa_defconfig
··· 100 100 CONFIG_DEVTMPFS_MOUNT=y 101 101 CONFIG_CONNECTOR=y 102 102 CONFIG_MTD=y 103 - CONFIG_MTD_AR7_PARTS=m 104 103 CONFIG_MTD_CMDLINE_PARTS=m 105 104 CONFIG_MTD_OF_PARTS=m 106 105 CONFIG_MTD_AFS_PARTS=m
-1
arch/mips/Kbuild.platforms
··· 2 2 # All platforms listed in alphabetic order 3 3 4 4 platform-$(CONFIG_MIPS_ALCHEMY) += alchemy/ 5 - platform-$(CONFIG_AR7) += ar7/ 6 5 platform-$(CONFIG_ATH25) += ath25/ 7 6 platform-$(CONFIG_ATH79) += ath79/ 8 7 platform-$(CONFIG_BCM47XX) += bcm47xx/
-22
arch/mips/Kconfig
··· 202 202 select SYS_SUPPORTS_ZBOOT 203 203 select COMMON_CLK 204 204 205 - config AR7 206 - bool "Texas Instruments AR7" 207 - select BOOT_ELF32 208 - select COMMON_CLK 209 - select DMA_NONCOHERENT 210 - select CEVT_R4K 211 - select CSRC_R4K 212 - select IRQ_MIPS_CPU 213 - select NO_EXCEPT_FILL 214 - select SWAP_IO_SPACE 215 - select SYS_HAS_CPU_MIPS32_R1 216 - select SYS_HAS_EARLY_PRINTK 217 - select SYS_SUPPORTS_32BIT_KERNEL 218 - select SYS_SUPPORTS_LITTLE_ENDIAN 219 - select SYS_SUPPORTS_MIPS16 220 - select SYS_SUPPORTS_ZBOOT_UART16550 221 - select GPIOLIB 222 - select VLYNQ 223 - help 224 - Support for the Texas Instruments AR7 System-on-a-Chip 225 - family: TNETD7100, 7200 and 7300. 226 - 227 205 config ATH25 228 206 bool "Atheros AR231x/AR531x SoC support" 229 207 select CEVT_R4K
-11
arch/mips/ar7/Makefile
··· 1 - # SPDX-License-Identifier: GPL-2.0 2 - 3 - obj-y := \ 4 - prom.o \ 5 - setup.o \ 6 - memory.o \ 7 - irq.o \ 8 - time.o \ 9 - platform.o \ 10 - gpio.o \ 11 - clock.o
-5
arch/mips/ar7/Platform
··· 1 - # 2 - # Texas Instruments AR7 3 - # 4 - cflags-$(CONFIG_AR7) += -I$(srctree)/arch/mips/include/asm/mach-ar7 5 - load-$(CONFIG_AR7) += 0xffffffff94100000
-439
arch/mips/ar7/clock.c
··· 1 - // SPDX-License-Identifier: GPL-2.0-or-later 2 - /* 3 - * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org> 4 - * Copyright (C) 2007 Eugene Konev <ejka@openwrt.org> 5 - * Copyright (C) 2009 Florian Fainelli <florian@openwrt.org> 6 - */ 7 - 8 - #include <linux/kernel.h> 9 - #include <linux/init.h> 10 - #include <linux/types.h> 11 - #include <linux/export.h> 12 - #include <linux/delay.h> 13 - #include <linux/gcd.h> 14 - #include <linux/io.h> 15 - #include <linux/err.h> 16 - #include <linux/clkdev.h> 17 - #include <linux/clk.h> 18 - #include <linux/clk-provider.h> 19 - 20 - #include <asm/addrspace.h> 21 - #include <asm/mach-ar7/ar7.h> 22 - 23 - #define BOOT_PLL_SOURCE_MASK 0x3 24 - #define CPU_PLL_SOURCE_SHIFT 16 25 - #define BUS_PLL_SOURCE_SHIFT 14 26 - #define USB_PLL_SOURCE_SHIFT 18 27 - #define DSP_PLL_SOURCE_SHIFT 22 28 - #define BOOT_PLL_SOURCE_AFE 0 29 - #define BOOT_PLL_SOURCE_BUS 0 30 - #define BOOT_PLL_SOURCE_REF 1 31 - #define BOOT_PLL_SOURCE_XTAL 2 32 - #define BOOT_PLL_SOURCE_CPU 3 33 - #define BOOT_PLL_BYPASS 0x00000020 34 - #define BOOT_PLL_ASYNC_MODE 0x02000000 35 - #define BOOT_PLL_2TO1_MODE 0x00008000 36 - 37 - #define TNETD7200_CLOCK_ID_CPU 0 38 - #define TNETD7200_CLOCK_ID_DSP 1 39 - #define TNETD7200_CLOCK_ID_USB 2 40 - 41 - #define TNETD7200_DEF_CPU_CLK 211000000 42 - #define TNETD7200_DEF_DSP_CLK 125000000 43 - #define TNETD7200_DEF_USB_CLK 48000000 44 - 45 - struct tnetd7300_clock { 46 - u32 ctrl; 47 - #define PREDIV_MASK 0x001f0000 48 - #define PREDIV_SHIFT 16 49 - #define POSTDIV_MASK 0x0000001f 50 - u32 unused1[3]; 51 - u32 pll; 52 - #define MUL_MASK 0x0000f000 53 - #define MUL_SHIFT 12 54 - #define PLL_MODE_MASK 0x00000001 55 - #define PLL_NDIV 0x00000800 56 - #define PLL_DIV 0x00000002 57 - #define PLL_STATUS 0x00000001 58 - u32 unused2[3]; 59 - }; 60 - 61 - struct tnetd7300_clocks { 62 - struct tnetd7300_clock bus; 63 - struct tnetd7300_clock cpu; 64 - struct tnetd7300_clock usb; 65 - struct tnetd7300_clock dsp; 66 - }; 67 - 68 - struct tnetd7200_clock { 69 - u32 ctrl; 70 - u32 unused1[3]; 71 - #define DIVISOR_ENABLE_MASK 0x00008000 72 - u32 mul; 73 - u32 prediv; 74 - u32 postdiv; 75 - u32 postdiv2; 76 - u32 unused2[6]; 77 - u32 cmd; 78 - u32 status; 79 - u32 cmden; 80 - u32 padding[15]; 81 - }; 82 - 83 - struct tnetd7200_clocks { 84 - struct tnetd7200_clock cpu; 85 - struct tnetd7200_clock dsp; 86 - struct tnetd7200_clock usb; 87 - }; 88 - 89 - struct clk_rate { 90 - u32 rate; 91 - }; 92 - static struct clk_rate bus_clk = { 93 - .rate = 125000000, 94 - }; 95 - 96 - static struct clk_rate cpu_clk = { 97 - .rate = 150000000, 98 - }; 99 - 100 - static void approximate(int base, int target, int *prediv, 101 - int *postdiv, int *mul) 102 - { 103 - int i, j, k, freq, res = target; 104 - for (i = 1; i <= 16; i++) 105 - for (j = 1; j <= 32; j++) 106 - for (k = 1; k <= 32; k++) { 107 - freq = abs(base / j * i / k - target); 108 - if (freq < res) { 109 - res = freq; 110 - *mul = i; 111 - *prediv = j; 112 - *postdiv = k; 113 - } 114 - } 115 - } 116 - 117 - static void calculate(int base, int target, int *prediv, int *postdiv, 118 - int *mul) 119 - { 120 - int tmp_gcd, tmp_base, tmp_freq; 121 - 122 - for (*prediv = 1; *prediv <= 32; (*prediv)++) { 123 - tmp_base = base / *prediv; 124 - tmp_gcd = gcd(target, tmp_base); 125 - *mul = target / tmp_gcd; 126 - *postdiv = tmp_base / tmp_gcd; 127 - if ((*mul < 1) || (*mul >= 16)) 128 - continue; 129 - if ((*postdiv > 0) & (*postdiv <= 32)) 130 - break; 131 - } 132 - 133 - if (base / *prediv * *mul / *postdiv != target) { 134 - approximate(base, target, prediv, postdiv, mul); 135 - tmp_freq = base / *prediv * *mul / *postdiv; 136 - printk(KERN_WARNING 137 - "Adjusted requested frequency %d to %d\n", 138 - target, tmp_freq); 139 - } 140 - 141 - printk(KERN_DEBUG "Clocks: prediv: %d, postdiv: %d, mul: %d\n", 142 - *prediv, *postdiv, *mul); 143 - } 144 - 145 - static int tnetd7300_dsp_clock(void) 146 - { 147 - u32 didr1, didr2; 148 - u8 rev = ar7_chip_rev(); 149 - didr1 = readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x18)); 150 - didr2 = readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x1c)); 151 - if (didr2 & (1 << 23)) 152 - return 0; 153 - if ((rev >= 0x23) && (rev != 0x57)) 154 - return 250000000; 155 - if ((((didr2 & 0x1fff) << 10) | ((didr1 & 0xffc00000) >> 22)) 156 - > 4208000) 157 - return 250000000; 158 - return 0; 159 - } 160 - 161 - static int tnetd7300_get_clock(u32 shift, struct tnetd7300_clock *clock, 162 - u32 *bootcr, u32 bus_clock) 163 - { 164 - int product; 165 - int base_clock = AR7_REF_CLOCK; 166 - u32 ctrl = readl(&clock->ctrl); 167 - u32 pll = readl(&clock->pll); 168 - int prediv = ((ctrl & PREDIV_MASK) >> PREDIV_SHIFT) + 1; 169 - int postdiv = (ctrl & POSTDIV_MASK) + 1; 170 - int divisor = prediv * postdiv; 171 - int mul = ((pll & MUL_MASK) >> MUL_SHIFT) + 1; 172 - 173 - switch ((*bootcr & (BOOT_PLL_SOURCE_MASK << shift)) >> shift) { 174 - case BOOT_PLL_SOURCE_BUS: 175 - base_clock = bus_clock; 176 - break; 177 - case BOOT_PLL_SOURCE_REF: 178 - base_clock = AR7_REF_CLOCK; 179 - break; 180 - case BOOT_PLL_SOURCE_XTAL: 181 - base_clock = AR7_XTAL_CLOCK; 182 - break; 183 - case BOOT_PLL_SOURCE_CPU: 184 - base_clock = cpu_clk.rate; 185 - break; 186 - } 187 - 188 - if (*bootcr & BOOT_PLL_BYPASS) 189 - return base_clock / divisor; 190 - 191 - if ((pll & PLL_MODE_MASK) == 0) 192 - return (base_clock >> (mul / 16 + 1)) / divisor; 193 - 194 - if ((pll & (PLL_NDIV | PLL_DIV)) == (PLL_NDIV | PLL_DIV)) { 195 - product = (mul & 1) ? 196 - (base_clock * mul) >> 1 : 197 - (base_clock * (mul - 1)) >> 2; 198 - return product / divisor; 199 - } 200 - 201 - if (mul == 16) 202 - return base_clock / divisor; 203 - 204 - return base_clock * mul / divisor; 205 - } 206 - 207 - static void tnetd7300_set_clock(u32 shift, struct tnetd7300_clock *clock, 208 - u32 *bootcr, u32 frequency) 209 - { 210 - int prediv, postdiv, mul; 211 - int base_clock = bus_clk.rate; 212 - 213 - switch ((*bootcr & (BOOT_PLL_SOURCE_MASK << shift)) >> shift) { 214 - case BOOT_PLL_SOURCE_BUS: 215 - base_clock = bus_clk.rate; 216 - break; 217 - case BOOT_PLL_SOURCE_REF: 218 - base_clock = AR7_REF_CLOCK; 219 - break; 220 - case BOOT_PLL_SOURCE_XTAL: 221 - base_clock = AR7_XTAL_CLOCK; 222 - break; 223 - case BOOT_PLL_SOURCE_CPU: 224 - base_clock = cpu_clk.rate; 225 - break; 226 - } 227 - 228 - calculate(base_clock, frequency, &prediv, &postdiv, &mul); 229 - 230 - writel(((prediv - 1) << PREDIV_SHIFT) | (postdiv - 1), &clock->ctrl); 231 - mdelay(1); 232 - writel(4, &clock->pll); 233 - while (readl(&clock->pll) & PLL_STATUS) 234 - ; 235 - writel(((mul - 1) << MUL_SHIFT) | (0xff << 3) | 0x0e, &clock->pll); 236 - mdelay(75); 237 - } 238 - 239 - static void __init tnetd7300_init_clocks(void) 240 - { 241 - u32 *bootcr = (u32 *)ioremap(AR7_REGS_DCL, 4); 242 - struct tnetd7300_clocks *clocks = 243 - ioremap(UR8_REGS_CLOCKS, 244 - sizeof(struct tnetd7300_clocks)); 245 - u32 dsp_clk; 246 - struct clk *clk; 247 - 248 - bus_clk.rate = tnetd7300_get_clock(BUS_PLL_SOURCE_SHIFT, 249 - &clocks->bus, bootcr, AR7_AFE_CLOCK); 250 - 251 - if (*bootcr & BOOT_PLL_ASYNC_MODE) 252 - cpu_clk.rate = tnetd7300_get_clock(CPU_PLL_SOURCE_SHIFT, 253 - &clocks->cpu, bootcr, AR7_AFE_CLOCK); 254 - else 255 - cpu_clk.rate = bus_clk.rate; 256 - 257 - dsp_clk = tnetd7300_dsp_clock(); 258 - if (dsp_clk == 250000000) 259 - tnetd7300_set_clock(DSP_PLL_SOURCE_SHIFT, &clocks->dsp, 260 - bootcr, dsp_clk); 261 - 262 - iounmap(clocks); 263 - iounmap(bootcr); 264 - 265 - clk = clk_register_fixed_rate(NULL, "cpu", NULL, 0, cpu_clk.rate); 266 - clkdev_create(clk, "cpu", NULL); 267 - clk = clk_register_fixed_rate(NULL, "dsp", NULL, 0, dsp_clk); 268 - clkdev_create(clk, "dsp", NULL); 269 - } 270 - 271 - static void tnetd7200_set_clock(int base, struct tnetd7200_clock *clock, 272 - int prediv, int postdiv, int postdiv2, int mul, u32 frequency) 273 - { 274 - printk(KERN_INFO 275 - "Clocks: base = %d, frequency = %u, prediv = %d, " 276 - "postdiv = %d, postdiv2 = %d, mul = %d\n", 277 - base, frequency, prediv, postdiv, postdiv2, mul); 278 - 279 - writel(0, &clock->ctrl); 280 - writel(DIVISOR_ENABLE_MASK | ((prediv - 1) & 0x1F), &clock->prediv); 281 - writel((mul - 1) & 0xF, &clock->mul); 282 - 283 - while (readl(&clock->status) & 0x1) 284 - ; /* nop */ 285 - 286 - writel(DIVISOR_ENABLE_MASK | ((postdiv - 1) & 0x1F), &clock->postdiv); 287 - 288 - writel(readl(&clock->cmden) | 1, &clock->cmden); 289 - writel(readl(&clock->cmd) | 1, &clock->cmd); 290 - 291 - while (readl(&clock->status) & 0x1) 292 - ; /* nop */ 293 - 294 - writel(DIVISOR_ENABLE_MASK | ((postdiv2 - 1) & 0x1F), &clock->postdiv2); 295 - 296 - writel(readl(&clock->cmden) | 1, &clock->cmden); 297 - writel(readl(&clock->cmd) | 1, &clock->cmd); 298 - 299 - while (readl(&clock->status) & 0x1) 300 - ; /* nop */ 301 - 302 - writel(readl(&clock->ctrl) | 1, &clock->ctrl); 303 - } 304 - 305 - static int tnetd7200_get_clock_base(int clock_id, u32 *bootcr) 306 - { 307 - if (*bootcr & BOOT_PLL_ASYNC_MODE) 308 - /* Async */ 309 - switch (clock_id) { 310 - case TNETD7200_CLOCK_ID_DSP: 311 - return AR7_REF_CLOCK; 312 - default: 313 - return AR7_AFE_CLOCK; 314 - } 315 - else 316 - /* Sync */ 317 - if (*bootcr & BOOT_PLL_2TO1_MODE) 318 - /* 2:1 */ 319 - switch (clock_id) { 320 - case TNETD7200_CLOCK_ID_DSP: 321 - return AR7_REF_CLOCK; 322 - default: 323 - return AR7_AFE_CLOCK; 324 - } 325 - else 326 - /* 1:1 */ 327 - return AR7_REF_CLOCK; 328 - } 329 - 330 - 331 - static void __init tnetd7200_init_clocks(void) 332 - { 333 - u32 *bootcr = (u32 *)ioremap(AR7_REGS_DCL, 4); 334 - struct tnetd7200_clocks *clocks = 335 - ioremap(AR7_REGS_CLOCKS, 336 - sizeof(struct tnetd7200_clocks)); 337 - int cpu_base, cpu_mul, cpu_prediv, cpu_postdiv; 338 - int dsp_base, dsp_mul, dsp_prediv, dsp_postdiv; 339 - int usb_base, usb_mul, usb_prediv, usb_postdiv; 340 - struct clk *clk; 341 - 342 - cpu_base = tnetd7200_get_clock_base(TNETD7200_CLOCK_ID_CPU, bootcr); 343 - dsp_base = tnetd7200_get_clock_base(TNETD7200_CLOCK_ID_DSP, bootcr); 344 - 345 - if (*bootcr & BOOT_PLL_ASYNC_MODE) { 346 - printk(KERN_INFO "Clocks: Async mode\n"); 347 - 348 - printk(KERN_INFO "Clocks: Setting DSP clock\n"); 349 - calculate(dsp_base, TNETD7200_DEF_DSP_CLK, 350 - &dsp_prediv, &dsp_postdiv, &dsp_mul); 351 - bus_clk.rate = 352 - ((dsp_base / dsp_prediv) * dsp_mul) / dsp_postdiv; 353 - tnetd7200_set_clock(dsp_base, &clocks->dsp, 354 - dsp_prediv, dsp_postdiv * 2, dsp_postdiv, dsp_mul * 2, 355 - bus_clk.rate); 356 - 357 - printk(KERN_INFO "Clocks: Setting CPU clock\n"); 358 - calculate(cpu_base, TNETD7200_DEF_CPU_CLK, &cpu_prediv, 359 - &cpu_postdiv, &cpu_mul); 360 - cpu_clk.rate = 361 - ((cpu_base / cpu_prediv) * cpu_mul) / cpu_postdiv; 362 - tnetd7200_set_clock(cpu_base, &clocks->cpu, 363 - cpu_prediv, cpu_postdiv, -1, cpu_mul, 364 - cpu_clk.rate); 365 - 366 - } else 367 - if (*bootcr & BOOT_PLL_2TO1_MODE) { 368 - printk(KERN_INFO "Clocks: Sync 2:1 mode\n"); 369 - 370 - printk(KERN_INFO "Clocks: Setting CPU clock\n"); 371 - calculate(cpu_base, TNETD7200_DEF_CPU_CLK, &cpu_prediv, 372 - &cpu_postdiv, &cpu_mul); 373 - cpu_clk.rate = ((cpu_base / cpu_prediv) * cpu_mul) 374 - / cpu_postdiv; 375 - tnetd7200_set_clock(cpu_base, &clocks->cpu, 376 - cpu_prediv, cpu_postdiv, -1, cpu_mul, 377 - cpu_clk.rate); 378 - 379 - printk(KERN_INFO "Clocks: Setting DSP clock\n"); 380 - calculate(dsp_base, TNETD7200_DEF_DSP_CLK, &dsp_prediv, 381 - &dsp_postdiv, &dsp_mul); 382 - bus_clk.rate = cpu_clk.rate / 2; 383 - tnetd7200_set_clock(dsp_base, &clocks->dsp, 384 - dsp_prediv, dsp_postdiv * 2, dsp_postdiv, 385 - dsp_mul * 2, bus_clk.rate); 386 - } else { 387 - printk(KERN_INFO "Clocks: Sync 1:1 mode\n"); 388 - 389 - printk(KERN_INFO "Clocks: Setting DSP clock\n"); 390 - calculate(dsp_base, TNETD7200_DEF_DSP_CLK, &dsp_prediv, 391 - &dsp_postdiv, &dsp_mul); 392 - bus_clk.rate = ((dsp_base / dsp_prediv) * dsp_mul) 393 - / dsp_postdiv; 394 - tnetd7200_set_clock(dsp_base, &clocks->dsp, 395 - dsp_prediv, dsp_postdiv * 2, dsp_postdiv, 396 - dsp_mul * 2, bus_clk.rate); 397 - 398 - cpu_clk.rate = bus_clk.rate; 399 - } 400 - 401 - printk(KERN_INFO "Clocks: Setting USB clock\n"); 402 - usb_base = bus_clk.rate; 403 - calculate(usb_base, TNETD7200_DEF_USB_CLK, &usb_prediv, 404 - &usb_postdiv, &usb_mul); 405 - tnetd7200_set_clock(usb_base, &clocks->usb, 406 - usb_prediv, usb_postdiv, -1, usb_mul, 407 - TNETD7200_DEF_USB_CLK); 408 - 409 - iounmap(clocks); 410 - iounmap(bootcr); 411 - 412 - clk = clk_register_fixed_rate(NULL, "cpu", NULL, 0, cpu_clk.rate); 413 - clkdev_create(clk, "cpu", NULL); 414 - clkdev_create(clk, "dsp", NULL); 415 - } 416 - 417 - void __init ar7_init_clocks(void) 418 - { 419 - struct clk *clk; 420 - 421 - switch (ar7_chip_id()) { 422 - case AR7_CHIP_7100: 423 - case AR7_CHIP_7200: 424 - tnetd7200_init_clocks(); 425 - break; 426 - case AR7_CHIP_7300: 427 - tnetd7300_init_clocks(); 428 - break; 429 - default: 430 - break; 431 - } 432 - clk = clk_register_fixed_rate(NULL, "bus", NULL, 0, bus_clk.rate); 433 - clkdev_create(clk, "bus", NULL); 434 - /* adjust vbus clock rate */ 435 - clk = clk_register_fixed_factor(NULL, "vbus", "bus", 0, 1, 2); 436 - clkdev_create(clk, "vbus", NULL); 437 - clkdev_create(clk, "cpmac", "cpmac.1"); 438 - clkdev_create(clk, "cpmac", "cpmac.1"); 439 - }
-332
arch/mips/ar7/gpio.c
··· 1 - // SPDX-License-Identifier: GPL-2.0-or-later 2 - /* 3 - * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org> 4 - * Copyright (C) 2007 Eugene Konev <ejka@openwrt.org> 5 - * Copyright (C) 2009-2010 Florian Fainelli <florian@openwrt.org> 6 - */ 7 - 8 - #include <linux/init.h> 9 - #include <linux/export.h> 10 - #include <linux/gpio/driver.h> 11 - 12 - #include <asm/mach-ar7/ar7.h> 13 - 14 - #define AR7_GPIO_MAX 32 15 - #define TITAN_GPIO_MAX 51 16 - 17 - struct ar7_gpio_chip { 18 - void __iomem *regs; 19 - struct gpio_chip chip; 20 - }; 21 - 22 - static int ar7_gpio_get_value(struct gpio_chip *chip, unsigned gpio) 23 - { 24 - struct ar7_gpio_chip *gpch = gpiochip_get_data(chip); 25 - void __iomem *gpio_in = gpch->regs + AR7_GPIO_INPUT; 26 - 27 - return !!(readl(gpio_in) & (1 << gpio)); 28 - } 29 - 30 - static int titan_gpio_get_value(struct gpio_chip *chip, unsigned gpio) 31 - { 32 - struct ar7_gpio_chip *gpch = gpiochip_get_data(chip); 33 - void __iomem *gpio_in0 = gpch->regs + TITAN_GPIO_INPUT_0; 34 - void __iomem *gpio_in1 = gpch->regs + TITAN_GPIO_INPUT_1; 35 - 36 - return readl(gpio >> 5 ? gpio_in1 : gpio_in0) & (1 << (gpio & 0x1f)); 37 - } 38 - 39 - static void ar7_gpio_set_value(struct gpio_chip *chip, 40 - unsigned gpio, int value) 41 - { 42 - struct ar7_gpio_chip *gpch = gpiochip_get_data(chip); 43 - void __iomem *gpio_out = gpch->regs + AR7_GPIO_OUTPUT; 44 - unsigned tmp; 45 - 46 - tmp = readl(gpio_out) & ~(1 << gpio); 47 - if (value) 48 - tmp |= 1 << gpio; 49 - writel(tmp, gpio_out); 50 - } 51 - 52 - static void titan_gpio_set_value(struct gpio_chip *chip, 53 - unsigned gpio, int value) 54 - { 55 - struct ar7_gpio_chip *gpch = gpiochip_get_data(chip); 56 - void __iomem *gpio_out0 = gpch->regs + TITAN_GPIO_OUTPUT_0; 57 - void __iomem *gpio_out1 = gpch->regs + TITAN_GPIO_OUTPUT_1; 58 - unsigned tmp; 59 - 60 - tmp = readl(gpio >> 5 ? gpio_out1 : gpio_out0) & ~(1 << (gpio & 0x1f)); 61 - if (value) 62 - tmp |= 1 << (gpio & 0x1f); 63 - writel(tmp, gpio >> 5 ? gpio_out1 : gpio_out0); 64 - } 65 - 66 - static int ar7_gpio_direction_input(struct gpio_chip *chip, unsigned gpio) 67 - { 68 - struct ar7_gpio_chip *gpch = gpiochip_get_data(chip); 69 - void __iomem *gpio_dir = gpch->regs + AR7_GPIO_DIR; 70 - 71 - writel(readl(gpio_dir) | (1 << gpio), gpio_dir); 72 - 73 - return 0; 74 - } 75 - 76 - static int titan_gpio_direction_input(struct gpio_chip *chip, unsigned gpio) 77 - { 78 - struct ar7_gpio_chip *gpch = gpiochip_get_data(chip); 79 - void __iomem *gpio_dir0 = gpch->regs + TITAN_GPIO_DIR_0; 80 - void __iomem *gpio_dir1 = gpch->regs + TITAN_GPIO_DIR_1; 81 - 82 - if (gpio >= TITAN_GPIO_MAX) 83 - return -EINVAL; 84 - 85 - writel(readl(gpio >> 5 ? gpio_dir1 : gpio_dir0) | (1 << (gpio & 0x1f)), 86 - gpio >> 5 ? gpio_dir1 : gpio_dir0); 87 - return 0; 88 - } 89 - 90 - static int ar7_gpio_direction_output(struct gpio_chip *chip, 91 - unsigned gpio, int value) 92 - { 93 - struct ar7_gpio_chip *gpch = gpiochip_get_data(chip); 94 - void __iomem *gpio_dir = gpch->regs + AR7_GPIO_DIR; 95 - 96 - ar7_gpio_set_value(chip, gpio, value); 97 - writel(readl(gpio_dir) & ~(1 << gpio), gpio_dir); 98 - 99 - return 0; 100 - } 101 - 102 - static int titan_gpio_direction_output(struct gpio_chip *chip, 103 - unsigned gpio, int value) 104 - { 105 - struct ar7_gpio_chip *gpch = gpiochip_get_data(chip); 106 - void __iomem *gpio_dir0 = gpch->regs + TITAN_GPIO_DIR_0; 107 - void __iomem *gpio_dir1 = gpch->regs + TITAN_GPIO_DIR_1; 108 - 109 - if (gpio >= TITAN_GPIO_MAX) 110 - return -EINVAL; 111 - 112 - titan_gpio_set_value(chip, gpio, value); 113 - writel(readl(gpio >> 5 ? gpio_dir1 : gpio_dir0) & ~(1 << 114 - (gpio & 0x1f)), gpio >> 5 ? gpio_dir1 : gpio_dir0); 115 - 116 - return 0; 117 - } 118 - 119 - static struct ar7_gpio_chip ar7_gpio_chip = { 120 - .chip = { 121 - .label = "ar7-gpio", 122 - .direction_input = ar7_gpio_direction_input, 123 - .direction_output = ar7_gpio_direction_output, 124 - .set = ar7_gpio_set_value, 125 - .get = ar7_gpio_get_value, 126 - .base = 0, 127 - .ngpio = AR7_GPIO_MAX, 128 - } 129 - }; 130 - 131 - static struct ar7_gpio_chip titan_gpio_chip = { 132 - .chip = { 133 - .label = "titan-gpio", 134 - .direction_input = titan_gpio_direction_input, 135 - .direction_output = titan_gpio_direction_output, 136 - .set = titan_gpio_set_value, 137 - .get = titan_gpio_get_value, 138 - .base = 0, 139 - .ngpio = TITAN_GPIO_MAX, 140 - } 141 - }; 142 - 143 - static inline int ar7_gpio_enable_ar7(unsigned gpio) 144 - { 145 - void __iomem *gpio_en = ar7_gpio_chip.regs + AR7_GPIO_ENABLE; 146 - 147 - writel(readl(gpio_en) | (1 << gpio), gpio_en); 148 - 149 - return 0; 150 - } 151 - 152 - static inline int ar7_gpio_enable_titan(unsigned gpio) 153 - { 154 - void __iomem *gpio_en0 = titan_gpio_chip.regs + TITAN_GPIO_ENBL_0; 155 - void __iomem *gpio_en1 = titan_gpio_chip.regs + TITAN_GPIO_ENBL_1; 156 - 157 - writel(readl(gpio >> 5 ? gpio_en1 : gpio_en0) | (1 << (gpio & 0x1f)), 158 - gpio >> 5 ? gpio_en1 : gpio_en0); 159 - 160 - return 0; 161 - } 162 - 163 - int ar7_gpio_enable(unsigned gpio) 164 - { 165 - return ar7_is_titan() ? ar7_gpio_enable_titan(gpio) : 166 - ar7_gpio_enable_ar7(gpio); 167 - } 168 - EXPORT_SYMBOL(ar7_gpio_enable); 169 - 170 - static inline int ar7_gpio_disable_ar7(unsigned gpio) 171 - { 172 - void __iomem *gpio_en = ar7_gpio_chip.regs + AR7_GPIO_ENABLE; 173 - 174 - writel(readl(gpio_en) & ~(1 << gpio), gpio_en); 175 - 176 - return 0; 177 - } 178 - 179 - static inline int ar7_gpio_disable_titan(unsigned gpio) 180 - { 181 - void __iomem *gpio_en0 = titan_gpio_chip.regs + TITAN_GPIO_ENBL_0; 182 - void __iomem *gpio_en1 = titan_gpio_chip.regs + TITAN_GPIO_ENBL_1; 183 - 184 - writel(readl(gpio >> 5 ? gpio_en1 : gpio_en0) & ~(1 << (gpio & 0x1f)), 185 - gpio >> 5 ? gpio_en1 : gpio_en0); 186 - 187 - return 0; 188 - } 189 - 190 - int ar7_gpio_disable(unsigned gpio) 191 - { 192 - return ar7_is_titan() ? ar7_gpio_disable_titan(gpio) : 193 - ar7_gpio_disable_ar7(gpio); 194 - } 195 - EXPORT_SYMBOL(ar7_gpio_disable); 196 - 197 - struct titan_gpio_cfg { 198 - u32 reg; 199 - u32 shift; 200 - u32 func; 201 - }; 202 - 203 - static const struct titan_gpio_cfg titan_gpio_table[] = { 204 - /* reg, start bit, mux value */ 205 - {4, 24, 1}, 206 - {4, 26, 1}, 207 - {4, 28, 1}, 208 - {4, 30, 1}, 209 - {5, 6, 1}, 210 - {5, 8, 1}, 211 - {5, 10, 1}, 212 - {5, 12, 1}, 213 - {7, 14, 3}, 214 - {7, 16, 3}, 215 - {7, 18, 3}, 216 - {7, 20, 3}, 217 - {7, 22, 3}, 218 - {7, 26, 3}, 219 - {7, 28, 3}, 220 - {7, 30, 3}, 221 - {8, 0, 3}, 222 - {8, 2, 3}, 223 - {8, 4, 3}, 224 - {8, 10, 3}, 225 - {8, 14, 3}, 226 - {8, 16, 3}, 227 - {8, 18, 3}, 228 - {8, 20, 3}, 229 - {9, 8, 3}, 230 - {9, 10, 3}, 231 - {9, 12, 3}, 232 - {9, 14, 3}, 233 - {9, 18, 3}, 234 - {9, 20, 3}, 235 - {9, 24, 3}, 236 - {9, 26, 3}, 237 - {9, 28, 3}, 238 - {9, 30, 3}, 239 - {10, 0, 3}, 240 - {10, 2, 3}, 241 - {10, 8, 3}, 242 - {10, 10, 3}, 243 - {10, 12, 3}, 244 - {10, 14, 3}, 245 - {13, 12, 3}, 246 - {13, 14, 3}, 247 - {13, 16, 3}, 248 - {13, 18, 3}, 249 - {13, 24, 3}, 250 - {13, 26, 3}, 251 - {13, 28, 3}, 252 - {13, 30, 3}, 253 - {14, 2, 3}, 254 - {14, 6, 3}, 255 - {14, 8, 3}, 256 - {14, 12, 3} 257 - }; 258 - 259 - static int titan_gpio_pinsel(unsigned gpio) 260 - { 261 - struct titan_gpio_cfg gpio_cfg; 262 - u32 mux_status, pin_sel_reg, tmp; 263 - void __iomem *pin_sel = (void __iomem *)KSEG1ADDR(AR7_REGS_PINSEL); 264 - 265 - if (gpio >= ARRAY_SIZE(titan_gpio_table)) 266 - return -EINVAL; 267 - 268 - gpio_cfg = titan_gpio_table[gpio]; 269 - pin_sel_reg = gpio_cfg.reg - 1; 270 - 271 - mux_status = (readl(pin_sel + pin_sel_reg) >> gpio_cfg.shift) & 0x3; 272 - 273 - /* Check the mux status */ 274 - if (!((mux_status == 0) || (mux_status == gpio_cfg.func))) 275 - return 0; 276 - 277 - /* Set the pin sel value */ 278 - tmp = readl(pin_sel + pin_sel_reg); 279 - tmp |= ((gpio_cfg.func & 0x3) << gpio_cfg.shift); 280 - writel(tmp, pin_sel + pin_sel_reg); 281 - 282 - return 0; 283 - } 284 - 285 - /* Perform minimal Titan GPIO configuration */ 286 - static void titan_gpio_init(void) 287 - { 288 - unsigned i; 289 - 290 - for (i = 44; i < 48; i++) { 291 - titan_gpio_pinsel(i); 292 - ar7_gpio_enable_titan(i); 293 - titan_gpio_direction_input(&titan_gpio_chip.chip, i); 294 - } 295 - } 296 - 297 - int __init ar7_gpio_init(void) 298 - { 299 - int ret; 300 - struct ar7_gpio_chip *gpch; 301 - unsigned size; 302 - 303 - if (!ar7_is_titan()) { 304 - gpch = &ar7_gpio_chip; 305 - size = 0x10; 306 - } else { 307 - gpch = &titan_gpio_chip; 308 - size = 0x1f; 309 - } 310 - 311 - gpch->regs = ioremap(AR7_REGS_GPIO, size); 312 - if (!gpch->regs) { 313 - printk(KERN_ERR "%s: failed to ioremap regs\n", 314 - gpch->chip.label); 315 - return -ENOMEM; 316 - } 317 - 318 - ret = gpiochip_add_data(&gpch->chip, gpch); 319 - if (ret) { 320 - printk(KERN_ERR "%s: failed to add gpiochip\n", 321 - gpch->chip.label); 322 - iounmap(gpch->regs); 323 - return ret; 324 - } 325 - printk(KERN_INFO "%s: registered %d GPIOs\n", 326 - gpch->chip.label, gpch->chip.ngpio); 327 - 328 - if (ar7_is_titan()) 329 - titan_gpio_init(); 330 - 331 - return ret; 332 - }
-165
arch/mips/ar7/irq.c
··· 1 - // SPDX-License-Identifier: GPL-2.0-or-later 2 - /* 3 - * Copyright (C) 2006,2007 Felix Fietkau <nbd@openwrt.org> 4 - * Copyright (C) 2006,2007 Eugene Konev <ejka@openwrt.org> 5 - */ 6 - 7 - #include <linux/interrupt.h> 8 - #include <linux/io.h> 9 - #include <linux/irq.h> 10 - 11 - #include <asm/irq_cpu.h> 12 - #include <asm/mipsregs.h> 13 - #include <asm/mach-ar7/ar7.h> 14 - 15 - #define EXCEPT_OFFSET 0x80 16 - #define PACE_OFFSET 0xA0 17 - #define CHNLS_OFFSET 0x200 18 - 19 - #define REG_OFFSET(irq, reg) ((irq) / 32 * 0x4 + reg * 0x10) 20 - #define SEC_REG_OFFSET(reg) (EXCEPT_OFFSET + reg * 0x8) 21 - #define SEC_SR_OFFSET (SEC_REG_OFFSET(0)) /* 0x80 */ 22 - #define CR_OFFSET(irq) (REG_OFFSET(irq, 1)) /* 0x10 */ 23 - #define SEC_CR_OFFSET (SEC_REG_OFFSET(1)) /* 0x88 */ 24 - #define ESR_OFFSET(irq) (REG_OFFSET(irq, 2)) /* 0x20 */ 25 - #define SEC_ESR_OFFSET (SEC_REG_OFFSET(2)) /* 0x90 */ 26 - #define ECR_OFFSET(irq) (REG_OFFSET(irq, 3)) /* 0x30 */ 27 - #define SEC_ECR_OFFSET (SEC_REG_OFFSET(3)) /* 0x98 */ 28 - #define PIR_OFFSET (0x40) 29 - #define MSR_OFFSET (0x44) 30 - #define PM_OFFSET(irq) (REG_OFFSET(irq, 5)) /* 0x50 */ 31 - #define TM_OFFSET(irq) (REG_OFFSET(irq, 6)) /* 0x60 */ 32 - 33 - #define REG(addr) ((u32 *)(KSEG1ADDR(AR7_REGS_IRQ) + addr)) 34 - 35 - #define CHNL_OFFSET(chnl) (CHNLS_OFFSET + (chnl * 4)) 36 - 37 - static int ar7_irq_base; 38 - 39 - static void ar7_unmask_irq(struct irq_data *d) 40 - { 41 - writel(1 << ((d->irq - ar7_irq_base) % 32), 42 - REG(ESR_OFFSET(d->irq - ar7_irq_base))); 43 - } 44 - 45 - static void ar7_mask_irq(struct irq_data *d) 46 - { 47 - writel(1 << ((d->irq - ar7_irq_base) % 32), 48 - REG(ECR_OFFSET(d->irq - ar7_irq_base))); 49 - } 50 - 51 - static void ar7_ack_irq(struct irq_data *d) 52 - { 53 - writel(1 << ((d->irq - ar7_irq_base) % 32), 54 - REG(CR_OFFSET(d->irq - ar7_irq_base))); 55 - } 56 - 57 - static void ar7_unmask_sec_irq(struct irq_data *d) 58 - { 59 - writel(1 << (d->irq - ar7_irq_base - 40), REG(SEC_ESR_OFFSET)); 60 - } 61 - 62 - static void ar7_mask_sec_irq(struct irq_data *d) 63 - { 64 - writel(1 << (d->irq - ar7_irq_base - 40), REG(SEC_ECR_OFFSET)); 65 - } 66 - 67 - static void ar7_ack_sec_irq(struct irq_data *d) 68 - { 69 - writel(1 << (d->irq - ar7_irq_base - 40), REG(SEC_CR_OFFSET)); 70 - } 71 - 72 - static struct irq_chip ar7_irq_type = { 73 - .name = "AR7", 74 - .irq_unmask = ar7_unmask_irq, 75 - .irq_mask = ar7_mask_irq, 76 - .irq_ack = ar7_ack_irq 77 - }; 78 - 79 - static struct irq_chip ar7_sec_irq_type = { 80 - .name = "AR7", 81 - .irq_unmask = ar7_unmask_sec_irq, 82 - .irq_mask = ar7_mask_sec_irq, 83 - .irq_ack = ar7_ack_sec_irq, 84 - }; 85 - 86 - static void __init ar7_irq_init(int base) 87 - { 88 - int i; 89 - /* 90 - * Disable interrupts and clear pending 91 - */ 92 - writel(0xffffffff, REG(ECR_OFFSET(0))); 93 - writel(0xff, REG(ECR_OFFSET(32))); 94 - writel(0xffffffff, REG(SEC_ECR_OFFSET)); 95 - writel(0xffffffff, REG(CR_OFFSET(0))); 96 - writel(0xff, REG(CR_OFFSET(32))); 97 - writel(0xffffffff, REG(SEC_CR_OFFSET)); 98 - 99 - ar7_irq_base = base; 100 - 101 - for (i = 0; i < 40; i++) { 102 - writel(i, REG(CHNL_OFFSET(i))); 103 - /* Primary IRQ's */ 104 - irq_set_chip_and_handler(base + i, &ar7_irq_type, 105 - handle_level_irq); 106 - /* Secondary IRQ's */ 107 - if (i < 32) 108 - irq_set_chip_and_handler(base + i + 40, 109 - &ar7_sec_irq_type, 110 - handle_level_irq); 111 - } 112 - 113 - if (request_irq(2, no_action, IRQF_NO_THREAD, "AR7 cascade interrupt", 114 - NULL)) 115 - pr_err("Failed to request irq 2 (AR7 cascade interrupt)\n"); 116 - if (request_irq(ar7_irq_base, no_action, IRQF_NO_THREAD, 117 - "AR7 cascade interrupt", NULL)) { 118 - pr_err("Failed to request irq %d (AR7 cascade interrupt)\n", 119 - ar7_irq_base); 120 - } 121 - set_c0_status(IE_IRQ0); 122 - } 123 - 124 - void __init arch_init_irq(void) 125 - { 126 - mips_cpu_irq_init(); 127 - ar7_irq_init(8); 128 - } 129 - 130 - static void ar7_cascade(void) 131 - { 132 - u32 status; 133 - int i, irq; 134 - 135 - /* Primary IRQ's */ 136 - irq = readl(REG(PIR_OFFSET)) & 0x3f; 137 - if (irq) { 138 - do_IRQ(ar7_irq_base + irq); 139 - return; 140 - } 141 - 142 - /* Secondary IRQ's are cascaded through primary '0' */ 143 - writel(1, REG(CR_OFFSET(irq))); 144 - status = readl(REG(SEC_SR_OFFSET)); 145 - for (i = 0; i < 32; i++) { 146 - if (status & 1) { 147 - do_IRQ(ar7_irq_base + i + 40); 148 - return; 149 - } 150 - status >>= 1; 151 - } 152 - 153 - spurious_interrupt(); 154 - } 155 - 156 - asmlinkage void plat_irq_dispatch(void) 157 - { 158 - unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM; 159 - if (pending & STATUSF_IP7) /* cpu timer */ 160 - do_IRQ(7); 161 - else if (pending & STATUSF_IP2) /* int0 hardware line */ 162 - ar7_cascade(); 163 - else 164 - spurious_interrupt(); 165 - }
-51
arch/mips/ar7/memory.c
··· 1 - // SPDX-License-Identifier: GPL-2.0-or-later 2 - /* 3 - * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org> 4 - * Copyright (C) 2007 Eugene Konev <ejka@openwrt.org> 5 - */ 6 - #include <linux/memblock.h> 7 - #include <linux/init.h> 8 - #include <linux/mm.h> 9 - #include <linux/pfn.h> 10 - #include <linux/proc_fs.h> 11 - #include <linux/string.h> 12 - #include <linux/swap.h> 13 - 14 - #include <asm/bootinfo.h> 15 - #include <asm/page.h> 16 - #include <asm/sections.h> 17 - 18 - #include <asm/mach-ar7/ar7.h> 19 - 20 - static int __init memsize(void) 21 - { 22 - u32 size = (64 << 20); 23 - u32 *addr = (u32 *)KSEG1ADDR(AR7_SDRAM_BASE + size - 4); 24 - u32 *kernel_end = (u32 *)KSEG1ADDR(CPHYSADDR((u32)&_end)); 25 - u32 *tmpaddr = addr; 26 - 27 - while (tmpaddr > kernel_end) { 28 - *tmpaddr = (u32)tmpaddr; 29 - size >>= 1; 30 - tmpaddr -= size >> 2; 31 - } 32 - 33 - do { 34 - tmpaddr += size >> 2; 35 - if (*tmpaddr != (u32)tmpaddr) 36 - break; 37 - size <<= 1; 38 - } while (size < (64 << 20)); 39 - 40 - writel((u32)tmpaddr, &addr); 41 - 42 - return size; 43 - } 44 - 45 - void __init prom_meminit(void) 46 - { 47 - unsigned long pages; 48 - 49 - pages = memsize() >> PAGE_SHIFT; 50 - memblock_add(PHYS_OFFSET, pages << PAGE_SHIFT); 51 - }
-722
arch/mips/ar7/platform.c
··· 1 - // SPDX-License-Identifier: GPL-2.0-or-later 2 - /* 3 - * Copyright (C) 2006,2007 Felix Fietkau <nbd@openwrt.org> 4 - * Copyright (C) 2006,2007 Eugene Konev <ejka@openwrt.org> 5 - */ 6 - 7 - #include <linux/init.h> 8 - #include <linux/types.h> 9 - #include <linux/delay.h> 10 - #include <linux/dma-mapping.h> 11 - #include <linux/platform_device.h> 12 - #include <linux/mtd/physmap.h> 13 - #include <linux/serial.h> 14 - #include <linux/serial_8250.h> 15 - #include <linux/ioport.h> 16 - #include <linux/io.h> 17 - #include <linux/vlynq.h> 18 - #include <linux/leds.h> 19 - #include <linux/string.h> 20 - #include <linux/etherdevice.h> 21 - #include <linux/phy.h> 22 - #include <linux/phy_fixed.h> 23 - #include <linux/gpio.h> 24 - #include <linux/clk.h> 25 - 26 - #include <asm/addrspace.h> 27 - #include <asm/mach-ar7/ar7.h> 28 - #include <asm/mach-ar7/prom.h> 29 - 30 - /***************************************************************************** 31 - * VLYNQ Bus 32 - ****************************************************************************/ 33 - struct plat_vlynq_data { 34 - struct plat_vlynq_ops ops; 35 - int gpio_bit; 36 - int reset_bit; 37 - }; 38 - 39 - static int vlynq_on(struct vlynq_device *dev) 40 - { 41 - int ret; 42 - struct plat_vlynq_data *pdata = dev->dev.platform_data; 43 - 44 - ret = gpio_request(pdata->gpio_bit, "vlynq"); 45 - if (ret) 46 - goto out; 47 - 48 - ar7_device_reset(pdata->reset_bit); 49 - 50 - ret = ar7_gpio_disable(pdata->gpio_bit); 51 - if (ret) 52 - goto out_enabled; 53 - 54 - ret = ar7_gpio_enable(pdata->gpio_bit); 55 - if (ret) 56 - goto out_enabled; 57 - 58 - ret = gpio_direction_output(pdata->gpio_bit, 0); 59 - if (ret) 60 - goto out_gpio_enabled; 61 - 62 - msleep(50); 63 - 64 - gpio_set_value(pdata->gpio_bit, 1); 65 - 66 - msleep(50); 67 - 68 - return 0; 69 - 70 - out_gpio_enabled: 71 - ar7_gpio_disable(pdata->gpio_bit); 72 - out_enabled: 73 - ar7_device_disable(pdata->reset_bit); 74 - gpio_free(pdata->gpio_bit); 75 - out: 76 - return ret; 77 - } 78 - 79 - static void vlynq_off(struct vlynq_device *dev) 80 - { 81 - struct plat_vlynq_data *pdata = dev->dev.platform_data; 82 - 83 - ar7_gpio_disable(pdata->gpio_bit); 84 - gpio_free(pdata->gpio_bit); 85 - ar7_device_disable(pdata->reset_bit); 86 - } 87 - 88 - static struct resource vlynq_low_res[] = { 89 - { 90 - .name = "regs", 91 - .flags = IORESOURCE_MEM, 92 - .start = AR7_REGS_VLYNQ0, 93 - .end = AR7_REGS_VLYNQ0 + 0xff, 94 - }, 95 - { 96 - .name = "irq", 97 - .flags = IORESOURCE_IRQ, 98 - .start = 29, 99 - .end = 29, 100 - }, 101 - { 102 - .name = "mem", 103 - .flags = IORESOURCE_MEM, 104 - .start = 0x04000000, 105 - .end = 0x04ffffff, 106 - }, 107 - { 108 - .name = "devirq", 109 - .flags = IORESOURCE_IRQ, 110 - .start = 80, 111 - .end = 111, 112 - }, 113 - }; 114 - 115 - static struct resource vlynq_high_res[] = { 116 - { 117 - .name = "regs", 118 - .flags = IORESOURCE_MEM, 119 - .start = AR7_REGS_VLYNQ1, 120 - .end = AR7_REGS_VLYNQ1 + 0xff, 121 - }, 122 - { 123 - .name = "irq", 124 - .flags = IORESOURCE_IRQ, 125 - .start = 33, 126 - .end = 33, 127 - }, 128 - { 129 - .name = "mem", 130 - .flags = IORESOURCE_MEM, 131 - .start = 0x0c000000, 132 - .end = 0x0cffffff, 133 - }, 134 - { 135 - .name = "devirq", 136 - .flags = IORESOURCE_IRQ, 137 - .start = 112, 138 - .end = 143, 139 - }, 140 - }; 141 - 142 - static struct plat_vlynq_data vlynq_low_data = { 143 - .ops = { 144 - .on = vlynq_on, 145 - .off = vlynq_off, 146 - }, 147 - .reset_bit = 20, 148 - .gpio_bit = 18, 149 - }; 150 - 151 - static struct plat_vlynq_data vlynq_high_data = { 152 - .ops = { 153 - .on = vlynq_on, 154 - .off = vlynq_off, 155 - }, 156 - .reset_bit = 16, 157 - .gpio_bit = 19, 158 - }; 159 - 160 - static struct platform_device vlynq_low = { 161 - .id = 0, 162 - .name = "vlynq", 163 - .dev = { 164 - .platform_data = &vlynq_low_data, 165 - }, 166 - .resource = vlynq_low_res, 167 - .num_resources = ARRAY_SIZE(vlynq_low_res), 168 - }; 169 - 170 - static struct platform_device vlynq_high = { 171 - .id = 1, 172 - .name = "vlynq", 173 - .dev = { 174 - .platform_data = &vlynq_high_data, 175 - }, 176 - .resource = vlynq_high_res, 177 - .num_resources = ARRAY_SIZE(vlynq_high_res), 178 - }; 179 - 180 - /***************************************************************************** 181 - * Flash 182 - ****************************************************************************/ 183 - static struct resource physmap_flash_resource = { 184 - .name = "mem", 185 - .flags = IORESOURCE_MEM, 186 - .start = 0x10000000, 187 - .end = 0x107fffff, 188 - }; 189 - 190 - static const char *ar7_probe_types[] = { "ar7part", NULL }; 191 - 192 - static struct physmap_flash_data physmap_flash_data = { 193 - .width = 2, 194 - .part_probe_types = ar7_probe_types, 195 - }; 196 - 197 - static struct platform_device physmap_flash = { 198 - .name = "physmap-flash", 199 - .dev = { 200 - .platform_data = &physmap_flash_data, 201 - }, 202 - .resource = &physmap_flash_resource, 203 - .num_resources = 1, 204 - }; 205 - 206 - /***************************************************************************** 207 - * Ethernet 208 - ****************************************************************************/ 209 - static struct resource cpmac_low_res[] = { 210 - { 211 - .name = "regs", 212 - .flags = IORESOURCE_MEM, 213 - .start = AR7_REGS_MAC0, 214 - .end = AR7_REGS_MAC0 + 0x7ff, 215 - }, 216 - { 217 - .name = "irq", 218 - .flags = IORESOURCE_IRQ, 219 - .start = 27, 220 - .end = 27, 221 - }, 222 - }; 223 - 224 - static struct resource cpmac_high_res[] = { 225 - { 226 - .name = "regs", 227 - .flags = IORESOURCE_MEM, 228 - .start = AR7_REGS_MAC1, 229 - .end = AR7_REGS_MAC1 + 0x7ff, 230 - }, 231 - { 232 - .name = "irq", 233 - .flags = IORESOURCE_IRQ, 234 - .start = 41, 235 - .end = 41, 236 - }, 237 - }; 238 - 239 - static struct fixed_phy_status fixed_phy_status __initdata = { 240 - .link = 1, 241 - .speed = 100, 242 - .duplex = 1, 243 - }; 244 - 245 - static struct plat_cpmac_data cpmac_low_data = { 246 - .reset_bit = 17, 247 - .power_bit = 20, 248 - .phy_mask = 0x80000000, 249 - }; 250 - 251 - static struct plat_cpmac_data cpmac_high_data = { 252 - .reset_bit = 21, 253 - .power_bit = 22, 254 - .phy_mask = 0x7fffffff, 255 - }; 256 - 257 - static u64 cpmac_dma_mask = DMA_BIT_MASK(32); 258 - 259 - static struct platform_device cpmac_low = { 260 - .id = 0, 261 - .name = "cpmac", 262 - .dev = { 263 - .dma_mask = &cpmac_dma_mask, 264 - .coherent_dma_mask = DMA_BIT_MASK(32), 265 - .platform_data = &cpmac_low_data, 266 - }, 267 - .resource = cpmac_low_res, 268 - .num_resources = ARRAY_SIZE(cpmac_low_res), 269 - }; 270 - 271 - static struct platform_device cpmac_high = { 272 - .id = 1, 273 - .name = "cpmac", 274 - .dev = { 275 - .dma_mask = &cpmac_dma_mask, 276 - .coherent_dma_mask = DMA_BIT_MASK(32), 277 - .platform_data = &cpmac_high_data, 278 - }, 279 - .resource = cpmac_high_res, 280 - .num_resources = ARRAY_SIZE(cpmac_high_res), 281 - }; 282 - 283 - static void __init cpmac_get_mac(int instance, unsigned char *dev_addr) 284 - { 285 - char name[5], *mac; 286 - 287 - sprintf(name, "mac%c", 'a' + instance); 288 - mac = prom_getenv(name); 289 - if (!mac && instance) { 290 - sprintf(name, "mac%c", 'a'); 291 - mac = prom_getenv(name); 292 - } 293 - 294 - if (mac) { 295 - if (!mac_pton(mac, dev_addr)) { 296 - pr_warn("cannot parse mac address, using random address\n"); 297 - eth_random_addr(dev_addr); 298 - } 299 - } else 300 - eth_random_addr(dev_addr); 301 - } 302 - 303 - /***************************************************************************** 304 - * USB 305 - ****************************************************************************/ 306 - static struct resource usb_res[] = { 307 - { 308 - .name = "regs", 309 - .flags = IORESOURCE_MEM, 310 - .start = AR7_REGS_USB, 311 - .end = AR7_REGS_USB + 0xff, 312 - }, 313 - { 314 - .name = "irq", 315 - .flags = IORESOURCE_IRQ, 316 - .start = 32, 317 - .end = 32, 318 - }, 319 - { 320 - .name = "mem", 321 - .flags = IORESOURCE_MEM, 322 - .start = 0x03400000, 323 - .end = 0x03401fff, 324 - }, 325 - }; 326 - 327 - static struct platform_device ar7_udc = { 328 - .name = "ar7_udc", 329 - .resource = usb_res, 330 - .num_resources = ARRAY_SIZE(usb_res), 331 - }; 332 - 333 - /***************************************************************************** 334 - * LEDs 335 - ****************************************************************************/ 336 - static const struct gpio_led default_leds[] = { 337 - { 338 - .name = "status", 339 - .gpio = 8, 340 - .active_low = 1, 341 - }, 342 - }; 343 - 344 - static const struct gpio_led titan_leds[] = { 345 - { .name = "status", .gpio = 8, .active_low = 1, }, 346 - { .name = "wifi", .gpio = 13, .active_low = 1, }, 347 - }; 348 - 349 - static const struct gpio_led dsl502t_leds[] = { 350 - { 351 - .name = "status", 352 - .gpio = 9, 353 - .active_low = 1, 354 - }, 355 - { 356 - .name = "ethernet", 357 - .gpio = 7, 358 - .active_low = 1, 359 - }, 360 - { 361 - .name = "usb", 362 - .gpio = 12, 363 - .active_low = 1, 364 - }, 365 - }; 366 - 367 - static const struct gpio_led dg834g_leds[] = { 368 - { 369 - .name = "ppp", 370 - .gpio = 6, 371 - .active_low = 1, 372 - }, 373 - { 374 - .name = "status", 375 - .gpio = 7, 376 - .active_low = 1, 377 - }, 378 - { 379 - .name = "adsl", 380 - .gpio = 8, 381 - .active_low = 1, 382 - }, 383 - { 384 - .name = "wifi", 385 - .gpio = 12, 386 - .active_low = 1, 387 - }, 388 - { 389 - .name = "power", 390 - .gpio = 14, 391 - .active_low = 1, 392 - .default_trigger = "default-on", 393 - }, 394 - }; 395 - 396 - static const struct gpio_led fb_sl_leds[] = { 397 - { 398 - .name = "1", 399 - .gpio = 7, 400 - }, 401 - { 402 - .name = "2", 403 - .gpio = 13, 404 - .active_low = 1, 405 - }, 406 - { 407 - .name = "3", 408 - .gpio = 10, 409 - .active_low = 1, 410 - }, 411 - { 412 - .name = "4", 413 - .gpio = 12, 414 - .active_low = 1, 415 - }, 416 - { 417 - .name = "5", 418 - .gpio = 9, 419 - .active_low = 1, 420 - }, 421 - }; 422 - 423 - static const struct gpio_led fb_fon_leds[] = { 424 - { 425 - .name = "1", 426 - .gpio = 8, 427 - }, 428 - { 429 - .name = "2", 430 - .gpio = 3, 431 - .active_low = 1, 432 - }, 433 - { 434 - .name = "3", 435 - .gpio = 5, 436 - }, 437 - { 438 - .name = "4", 439 - .gpio = 4, 440 - .active_low = 1, 441 - }, 442 - { 443 - .name = "5", 444 - .gpio = 11, 445 - .active_low = 1, 446 - }, 447 - }; 448 - 449 - static const struct gpio_led gt701_leds[] = { 450 - { 451 - .name = "inet:green", 452 - .gpio = 13, 453 - .active_low = 1, 454 - }, 455 - { 456 - .name = "usb", 457 - .gpio = 12, 458 - .active_low = 1, 459 - }, 460 - { 461 - .name = "inet:red", 462 - .gpio = 9, 463 - .active_low = 1, 464 - }, 465 - { 466 - .name = "power:red", 467 - .gpio = 7, 468 - .active_low = 1, 469 - }, 470 - { 471 - .name = "power:green", 472 - .gpio = 8, 473 - .active_low = 1, 474 - .default_trigger = "default-on", 475 - }, 476 - { 477 - .name = "ethernet", 478 - .gpio = 10, 479 - .active_low = 1, 480 - }, 481 - }; 482 - 483 - static struct gpio_led_platform_data ar7_led_data; 484 - 485 - static struct platform_device ar7_gpio_leds = { 486 - .name = "leds-gpio", 487 - .dev = { 488 - .platform_data = &ar7_led_data, 489 - } 490 - }; 491 - 492 - static void __init detect_leds(void) 493 - { 494 - char *prid, *usb_prod; 495 - 496 - /* Default LEDs */ 497 - ar7_led_data.num_leds = ARRAY_SIZE(default_leds); 498 - ar7_led_data.leds = default_leds; 499 - 500 - /* FIXME: the whole thing is unreliable */ 501 - prid = prom_getenv("ProductID"); 502 - usb_prod = prom_getenv("usb_prod"); 503 - 504 - /* If we can't get the product id from PROM, use the default LEDs */ 505 - if (!prid) 506 - return; 507 - 508 - if (strstr(prid, "Fritz_Box_FON")) { 509 - ar7_led_data.num_leds = ARRAY_SIZE(fb_fon_leds); 510 - ar7_led_data.leds = fb_fon_leds; 511 - } else if (strstr(prid, "Fritz_Box_")) { 512 - ar7_led_data.num_leds = ARRAY_SIZE(fb_sl_leds); 513 - ar7_led_data.leds = fb_sl_leds; 514 - } else if ((!strcmp(prid, "AR7RD") || !strcmp(prid, "AR7DB")) 515 - && usb_prod != NULL && strstr(usb_prod, "DSL-502T")) { 516 - ar7_led_data.num_leds = ARRAY_SIZE(dsl502t_leds); 517 - ar7_led_data.leds = dsl502t_leds; 518 - } else if (strstr(prid, "DG834")) { 519 - ar7_led_data.num_leds = ARRAY_SIZE(dg834g_leds); 520 - ar7_led_data.leds = dg834g_leds; 521 - } else if (strstr(prid, "CYWM") || strstr(prid, "CYWL")) { 522 - ar7_led_data.num_leds = ARRAY_SIZE(titan_leds); 523 - ar7_led_data.leds = titan_leds; 524 - } else if (strstr(prid, "GT701")) { 525 - ar7_led_data.num_leds = ARRAY_SIZE(gt701_leds); 526 - ar7_led_data.leds = gt701_leds; 527 - } 528 - } 529 - 530 - /***************************************************************************** 531 - * Watchdog 532 - ****************************************************************************/ 533 - static struct resource ar7_wdt_res = { 534 - .name = "regs", 535 - .flags = IORESOURCE_MEM, 536 - .start = -1, /* Filled at runtime */ 537 - .end = -1, /* Filled at runtime */ 538 - }; 539 - 540 - static struct platform_device ar7_wdt = { 541 - .name = "ar7_wdt", 542 - .resource = &ar7_wdt_res, 543 - .num_resources = 1, 544 - }; 545 - 546 - /***************************************************************************** 547 - * Init 548 - ****************************************************************************/ 549 - static int __init ar7_register_uarts(void) 550 - { 551 - #ifdef CONFIG_SERIAL_8250 552 - static struct uart_port uart_port __initdata; 553 - struct clk *bus_clk; 554 - int res; 555 - 556 - memset(&uart_port, 0, sizeof(struct uart_port)); 557 - 558 - bus_clk = clk_get(NULL, "bus"); 559 - if (IS_ERR(bus_clk)) 560 - panic("unable to get bus clk"); 561 - 562 - uart_port.type = PORT_AR7; 563 - uart_port.uartclk = clk_get_rate(bus_clk) / 2; 564 - uart_port.iotype = UPIO_MEM32; 565 - uart_port.flags = UPF_FIXED_TYPE | UPF_BOOT_AUTOCONF; 566 - uart_port.regshift = 2; 567 - 568 - uart_port.line = 0; 569 - uart_port.irq = AR7_IRQ_UART0; 570 - uart_port.mapbase = AR7_REGS_UART0; 571 - uart_port.membase = ioremap(uart_port.mapbase, 256); 572 - 573 - res = early_serial_setup(&uart_port); 574 - if (res) 575 - return res; 576 - 577 - /* Only TNETD73xx have a second serial port */ 578 - if (ar7_has_second_uart()) { 579 - uart_port.line = 1; 580 - uart_port.irq = AR7_IRQ_UART1; 581 - uart_port.mapbase = UR8_REGS_UART1; 582 - uart_port.membase = ioremap(uart_port.mapbase, 256); 583 - 584 - res = early_serial_setup(&uart_port); 585 - if (res) 586 - return res; 587 - } 588 - #endif 589 - 590 - return 0; 591 - } 592 - 593 - static void __init titan_fixup_devices(void) 594 - { 595 - /* Set vlynq0 data */ 596 - vlynq_low_data.reset_bit = 15; 597 - vlynq_low_data.gpio_bit = 14; 598 - 599 - /* Set vlynq1 data */ 600 - vlynq_high_data.reset_bit = 16; 601 - vlynq_high_data.gpio_bit = 7; 602 - 603 - /* Set vlynq0 resources */ 604 - vlynq_low_res[0].start = TITAN_REGS_VLYNQ0; 605 - vlynq_low_res[0].end = TITAN_REGS_VLYNQ0 + 0xff; 606 - vlynq_low_res[1].start = 33; 607 - vlynq_low_res[1].end = 33; 608 - vlynq_low_res[2].start = 0x0c000000; 609 - vlynq_low_res[2].end = 0x0fffffff; 610 - vlynq_low_res[3].start = 80; 611 - vlynq_low_res[3].end = 111; 612 - 613 - /* Set vlynq1 resources */ 614 - vlynq_high_res[0].start = TITAN_REGS_VLYNQ1; 615 - vlynq_high_res[0].end = TITAN_REGS_VLYNQ1 + 0xff; 616 - vlynq_high_res[1].start = 34; 617 - vlynq_high_res[1].end = 34; 618 - vlynq_high_res[2].start = 0x40000000; 619 - vlynq_high_res[2].end = 0x43ffffff; 620 - vlynq_high_res[3].start = 112; 621 - vlynq_high_res[3].end = 143; 622 - 623 - /* Set cpmac0 data */ 624 - cpmac_low_data.phy_mask = 0x40000000; 625 - 626 - /* Set cpmac1 data */ 627 - cpmac_high_data.phy_mask = 0x80000000; 628 - 629 - /* Set cpmac0 resources */ 630 - cpmac_low_res[0].start = TITAN_REGS_MAC0; 631 - cpmac_low_res[0].end = TITAN_REGS_MAC0 + 0x7ff; 632 - 633 - /* Set cpmac1 resources */ 634 - cpmac_high_res[0].start = TITAN_REGS_MAC1; 635 - cpmac_high_res[0].end = TITAN_REGS_MAC1 + 0x7ff; 636 - } 637 - 638 - static int __init ar7_register_devices(void) 639 - { 640 - void __iomem *bootcr; 641 - u32 val; 642 - int res; 643 - 644 - res = ar7_gpio_init(); 645 - if (res) 646 - pr_warn("unable to register gpios: %d\n", res); 647 - 648 - res = ar7_register_uarts(); 649 - if (res) 650 - pr_err("unable to setup uart(s): %d\n", res); 651 - 652 - res = platform_device_register(&physmap_flash); 653 - if (res) 654 - pr_warn("unable to register physmap-flash: %d\n", res); 655 - 656 - if (ar7_is_titan()) 657 - titan_fixup_devices(); 658 - 659 - ar7_device_disable(vlynq_low_data.reset_bit); 660 - res = platform_device_register(&vlynq_low); 661 - if (res) 662 - pr_warn("unable to register vlynq-low: %d\n", res); 663 - 664 - if (ar7_has_high_vlynq()) { 665 - ar7_device_disable(vlynq_high_data.reset_bit); 666 - res = platform_device_register(&vlynq_high); 667 - if (res) 668 - pr_warn("unable to register vlynq-high: %d\n", res); 669 - } 670 - 671 - if (ar7_has_high_cpmac()) { 672 - res = fixed_phy_add(PHY_POLL, cpmac_high.id, 673 - &fixed_phy_status); 674 - if (!res) { 675 - cpmac_get_mac(1, cpmac_high_data.dev_addr); 676 - 677 - res = platform_device_register(&cpmac_high); 678 - if (res) 679 - pr_warn("unable to register cpmac-high: %d\n", 680 - res); 681 - } else 682 - pr_warn("unable to add cpmac-high phy: %d\n", res); 683 - } else 684 - cpmac_low_data.phy_mask = 0xffffffff; 685 - 686 - res = fixed_phy_add(PHY_POLL, cpmac_low.id, &fixed_phy_status); 687 - if (!res) { 688 - cpmac_get_mac(0, cpmac_low_data.dev_addr); 689 - res = platform_device_register(&cpmac_low); 690 - if (res) 691 - pr_warn("unable to register cpmac-low: %d\n", res); 692 - } else 693 - pr_warn("unable to add cpmac-low phy: %d\n", res); 694 - 695 - detect_leds(); 696 - res = platform_device_register(&ar7_gpio_leds); 697 - if (res) 698 - pr_warn("unable to register leds: %d\n", res); 699 - 700 - res = platform_device_register(&ar7_udc); 701 - if (res) 702 - pr_warn("unable to register usb slave: %d\n", res); 703 - 704 - /* Register watchdog only if enabled in hardware */ 705 - bootcr = ioremap(AR7_REGS_DCL, 4); 706 - val = readl(bootcr); 707 - iounmap(bootcr); 708 - if (val & AR7_WDT_HW_ENA) { 709 - if (ar7_has_high_vlynq()) 710 - ar7_wdt_res.start = UR8_REGS_WDT; 711 - else 712 - ar7_wdt_res.start = AR7_REGS_WDT; 713 - 714 - ar7_wdt_res.end = ar7_wdt_res.start + 0x20; 715 - res = platform_device_register(&ar7_wdt); 716 - if (res) 717 - pr_warn("unable to register watchdog: %d\n", res); 718 - } 719 - 720 - return 0; 721 - } 722 - device_initcall(ar7_register_devices);
-256
arch/mips/ar7/prom.c
··· 1 - // SPDX-License-Identifier: GPL-2.0-only 2 - /* 3 - * Carsten Langgaard, carstenl@mips.com 4 - * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. 5 - * 6 - * Putting things on the screen/serial line using YAMONs facilities. 7 - */ 8 - #include <linux/init.h> 9 - #include <linux/kernel.h> 10 - #include <linux/serial_reg.h> 11 - #include <linux/spinlock.h> 12 - #include <linux/export.h> 13 - #include <linux/string.h> 14 - #include <linux/io.h> 15 - #include <asm/bootinfo.h> 16 - #include <asm/setup.h> 17 - 18 - #include <asm/mach-ar7/ar7.h> 19 - #include <asm/mach-ar7/prom.h> 20 - 21 - #define MAX_ENTRY 80 22 - 23 - struct env_var { 24 - char *name; 25 - char *value; 26 - }; 27 - 28 - static struct env_var adam2_env[MAX_ENTRY]; 29 - 30 - char *prom_getenv(const char *name) 31 - { 32 - int i; 33 - 34 - for (i = 0; (i < MAX_ENTRY) && adam2_env[i].name; i++) 35 - if (!strcmp(name, adam2_env[i].name)) 36 - return adam2_env[i].value; 37 - 38 - return NULL; 39 - } 40 - EXPORT_SYMBOL(prom_getenv); 41 - 42 - static void __init ar7_init_cmdline(int argc, char *argv[]) 43 - { 44 - int i; 45 - 46 - for (i = 1; i < argc; i++) { 47 - strlcat(arcs_cmdline, argv[i], COMMAND_LINE_SIZE); 48 - if (i < (argc - 1)) 49 - strlcat(arcs_cmdline, " ", COMMAND_LINE_SIZE); 50 - } 51 - } 52 - 53 - struct psbl_rec { 54 - u32 psbl_size; 55 - u32 env_base; 56 - u32 env_size; 57 - u32 ffs_base; 58 - u32 ffs_size; 59 - }; 60 - 61 - static const char psp_env_version[] __initconst = "TIENV0.8"; 62 - 63 - struct psp_env_chunk { 64 - u8 num; 65 - u8 ctrl; 66 - u16 csum; 67 - u8 len; 68 - char data[11]; 69 - } __packed; 70 - 71 - struct psp_var_map_entry { 72 - u8 num; 73 - char *value; 74 - }; 75 - 76 - static const struct psp_var_map_entry psp_var_map[] = { 77 - { 1, "cpufrequency" }, 78 - { 2, "memsize" }, 79 - { 3, "flashsize" }, 80 - { 4, "modetty0" }, 81 - { 5, "modetty1" }, 82 - { 8, "maca" }, 83 - { 9, "macb" }, 84 - { 28, "sysfrequency" }, 85 - { 38, "mipsfrequency" }, 86 - }; 87 - 88 - /* 89 - 90 - Well-known variable (num is looked up in table above for matching variable name) 91 - Example: cpufrequency=211968000 92 - +----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+--- 93 - | 01 |CTRL|CHECKSUM | 01 | _2 | _1 | _1 | _9 | _6 | _8 | _0 | _0 | _0 | \0 | FF 94 - +----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+--- 95 - 96 - Name=Value pair in a single chunk 97 - Example: NAME=VALUE 98 - +----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+--- 99 - | 00 |CTRL|CHECKSUM | 01 | _N | _A | _M | _E | _0 | _V | _A | _L | _U | _E | \0 100 - +----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+--- 101 - 102 - Name=Value pair in 2 chunks (len is the number of chunks) 103 - Example: bootloaderVersion=1.3.7.15 104 - +----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+--- 105 - | 00 |CTRL|CHECKSUM | 02 | _b | _o | _o | _t | _l | _o | _a | _d | _e | _r | _V 106 - +----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+--- 107 - | _e | _r | _s | _i | _o | _n | \0 | _1 | _. | _3 | _. | _7 | _. | _1 | _5 | \0 108 - +----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+--- 109 - 110 - Data is padded with 0xFF 111 - 112 - */ 113 - 114 - #define PSP_ENV_SIZE 4096 115 - 116 - static char psp_env_data[PSP_ENV_SIZE] = { 0, }; 117 - 118 - static char * __init lookup_psp_var_map(u8 num) 119 - { 120 - int i; 121 - 122 - for (i = 0; i < ARRAY_SIZE(psp_var_map); i++) 123 - if (psp_var_map[i].num == num) 124 - return psp_var_map[i].value; 125 - 126 - return NULL; 127 - } 128 - 129 - static void __init add_adam2_var(char *name, char *value) 130 - { 131 - int i; 132 - 133 - for (i = 0; i < MAX_ENTRY; i++) { 134 - if (!adam2_env[i].name) { 135 - adam2_env[i].name = name; 136 - adam2_env[i].value = value; 137 - return; 138 - } else if (!strcmp(adam2_env[i].name, name)) { 139 - adam2_env[i].value = value; 140 - return; 141 - } 142 - } 143 - } 144 - 145 - static int __init parse_psp_env(void *psp_env_base) 146 - { 147 - int i, n; 148 - char *name, *value; 149 - struct psp_env_chunk *chunks = (struct psp_env_chunk *)psp_env_data; 150 - 151 - memcpy_fromio(chunks, psp_env_base, PSP_ENV_SIZE); 152 - 153 - i = 1; 154 - n = PSP_ENV_SIZE / sizeof(struct psp_env_chunk); 155 - while (i < n) { 156 - if ((chunks[i].num == 0xff) || ((i + chunks[i].len) > n)) 157 - break; 158 - value = chunks[i].data; 159 - if (chunks[i].num) { 160 - name = lookup_psp_var_map(chunks[i].num); 161 - } else { 162 - name = value; 163 - value += strlen(name) + 1; 164 - } 165 - if (name) 166 - add_adam2_var(name, value); 167 - i += chunks[i].len; 168 - } 169 - return 0; 170 - } 171 - 172 - static void __init ar7_init_env(struct env_var *env) 173 - { 174 - int i; 175 - struct psbl_rec *psbl = (struct psbl_rec *)(KSEG1ADDR(0x14000300)); 176 - void *psp_env = (void *)KSEG1ADDR(psbl->env_base); 177 - 178 - if (strcmp(psp_env, psp_env_version) == 0) { 179 - parse_psp_env(psp_env); 180 - } else { 181 - for (i = 0; i < MAX_ENTRY; i++, env++) 182 - if (env->name) 183 - add_adam2_var(env->name, env->value); 184 - } 185 - } 186 - 187 - static void __init console_config(void) 188 - { 189 - #ifdef CONFIG_SERIAL_8250_CONSOLE 190 - char console_string[40]; 191 - int baud = 0; 192 - char parity = '\0', bits = '\0', flow = '\0'; 193 - char *s, *p; 194 - 195 - if (strstr(arcs_cmdline, "console=")) 196 - return; 197 - 198 - s = prom_getenv("modetty0"); 199 - if (s) { 200 - baud = simple_strtoul(s, &p, 10); 201 - s = p; 202 - if (*s == ',') 203 - s++; 204 - if (*s) 205 - parity = *s++; 206 - if (*s == ',') 207 - s++; 208 - if (*s) 209 - bits = *s++; 210 - if (*s == ',') 211 - s++; 212 - if (*s == 'h') 213 - flow = 'r'; 214 - } 215 - 216 - if (baud == 0) 217 - baud = 38400; 218 - if (parity != 'n' && parity != 'o' && parity != 'e') 219 - parity = 'n'; 220 - if (bits != '7' && bits != '8') 221 - bits = '8'; 222 - 223 - if (flow == 'r') 224 - sprintf(console_string, " console=ttyS0,%d%c%c%c", baud, 225 - parity, bits, flow); 226 - else 227 - sprintf(console_string, " console=ttyS0,%d%c%c", baud, parity, 228 - bits); 229 - strlcat(arcs_cmdline, console_string, COMMAND_LINE_SIZE); 230 - #endif 231 - } 232 - 233 - void __init prom_init(void) 234 - { 235 - ar7_init_cmdline(fw_arg0, (char **)fw_arg1); 236 - ar7_init_env((struct env_var *)fw_arg2); 237 - console_config(); 238 - } 239 - 240 - #define PORT(offset) (KSEG1ADDR(AR7_REGS_UART0 + (offset * 4))) 241 - static inline unsigned int serial_in(int offset) 242 - { 243 - return readl((void *)PORT(offset)); 244 - } 245 - 246 - static inline void serial_out(int offset, int value) 247 - { 248 - writel(value, (void *)PORT(offset)); 249 - } 250 - 251 - void prom_putchar(char c) 252 - { 253 - while ((serial_in(UART_LSR) & UART_LSR_TEMT) == 0) 254 - ; 255 - serial_out(UART_TX, c); 256 - }
-93
arch/mips/ar7/setup.c
··· 1 - // SPDX-License-Identifier: GPL-2.0-only 2 - /* 3 - * Carsten Langgaard, carstenl@mips.com 4 - * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. 5 - */ 6 - #include <linux/init.h> 7 - #include <linux/ioport.h> 8 - #include <linux/pm.h> 9 - #include <linux/time.h> 10 - 11 - #include <asm/reboot.h> 12 - #include <asm/mach-ar7/ar7.h> 13 - #include <asm/mach-ar7/prom.h> 14 - 15 - static void ar7_machine_restart(char *command) 16 - { 17 - u32 *softres_reg = ioremap(AR7_REGS_RESET + AR7_RESET_SOFTWARE, 1); 18 - 19 - writel(1, softres_reg); 20 - } 21 - 22 - static void ar7_machine_halt(void) 23 - { 24 - while (1) 25 - ; 26 - } 27 - 28 - static void ar7_machine_power_off(void) 29 - { 30 - u32 *power_reg = (u32 *)ioremap(AR7_REGS_POWER, 1); 31 - u32 power_state = readl(power_reg) | (3 << 30); 32 - 33 - writel(power_state, power_reg); 34 - ar7_machine_halt(); 35 - } 36 - 37 - const char *get_system_type(void) 38 - { 39 - u16 chip_id = ar7_chip_id(); 40 - u16 titan_variant_id = titan_chip_id(); 41 - 42 - switch (chip_id) { 43 - case AR7_CHIP_7100: 44 - return "TI AR7 (TNETD7100)"; 45 - case AR7_CHIP_7200: 46 - return "TI AR7 (TNETD7200)"; 47 - case AR7_CHIP_7300: 48 - return "TI AR7 (TNETD7300)"; 49 - case AR7_CHIP_TITAN: 50 - switch (titan_variant_id) { 51 - case TITAN_CHIP_1050: 52 - return "TI AR7 (TNETV1050)"; 53 - case TITAN_CHIP_1055: 54 - return "TI AR7 (TNETV1055)"; 55 - case TITAN_CHIP_1056: 56 - return "TI AR7 (TNETV1056)"; 57 - case TITAN_CHIP_1060: 58 - return "TI AR7 (TNETV1060)"; 59 - } 60 - fallthrough; 61 - default: 62 - return "TI AR7 (unknown)"; 63 - } 64 - } 65 - 66 - static int __init ar7_init_console(void) 67 - { 68 - return 0; 69 - } 70 - console_initcall(ar7_init_console); 71 - 72 - /* 73 - * Initializes basic routines and structures pointers, memory size (as 74 - * given by the bios and saves the command line. 75 - */ 76 - void __init plat_mem_setup(void) 77 - { 78 - unsigned long io_base; 79 - 80 - _machine_restart = ar7_machine_restart; 81 - _machine_halt = ar7_machine_halt; 82 - pm_power_off = ar7_machine_power_off; 83 - 84 - io_base = (unsigned long)ioremap(AR7_REGS_BASE, 0x10000); 85 - if (!io_base) 86 - panic("Can't remap IO base!"); 87 - set_io_port_base(io_base); 88 - 89 - prom_meminit(); 90 - 91 - printk(KERN_INFO "%s, ID: 0x%04x, Revision: 0x%02x\n", 92 - get_system_type(), ar7_chip_id(), ar7_chip_rev()); 93 - }
-31
arch/mips/ar7/time.c
··· 1 - // SPDX-License-Identifier: GPL-2.0-only 2 - /* 3 - * Carsten Langgaard, carstenl@mips.com 4 - * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. 5 - * 6 - * Setting up the clock on the MIPS boards. 7 - */ 8 - 9 - #include <linux/init.h> 10 - #include <linux/time.h> 11 - #include <linux/err.h> 12 - #include <linux/clk.h> 13 - 14 - #include <asm/time.h> 15 - #include <asm/mach-ar7/ar7.h> 16 - 17 - void __init plat_time_init(void) 18 - { 19 - struct clk *cpu_clk; 20 - 21 - /* Initialize ar7 clocks so the CPU clock frequency is correct */ 22 - ar7_init_clocks(); 23 - 24 - cpu_clk = clk_get(NULL, "cpu"); 25 - if (IS_ERR(cpu_clk)) { 26 - printk(KERN_ERR "unable to get cpu clock\n"); 27 - return; 28 - } 29 - 30 - mips_hpt_frequency = clk_get_rate(cpu_clk) / 2; 31 - }
-5
arch/mips/boot/compressed/uart-16550.c
··· 13 13 #define PORT(offset) (CKSEG1ADDR(UART_BASE) + (offset)) 14 14 #endif 15 15 16 - #ifdef CONFIG_AR7 17 - #include <ar7.h> 18 - #define PORT(offset) (CKSEG1ADDR(AR7_REGS_UART0) + (4 * offset)) 19 - #endif 20 - 21 16 #ifdef CONFIG_MACH_INGENIC 22 17 #define INGENIC_UART_BASE_ADDR (0x10030000 + 0x1000 * CONFIG_ZBOOT_INGENIC_UART) 23 18 #define PORT(offset) (CKSEG1ADDR(INGENIC_UART_BASE_ADDR) + (4 * offset))
-1
arch/mips/boot/dts/ingenic/jz4725b.dtsi
··· 366 366 367 367 rom: memory@1fc00000 { 368 368 compatible = "mtd-rom"; 369 - probe-type = "map_rom"; 370 369 reg = <0x1fc00000 0x2000>; 371 370 372 371 bank-width = <4>;
-1
arch/mips/boot/dts/ingenic/jz4770.dtsi
··· 461 461 462 462 rom: memory@1fc00000 { 463 463 compatible = "mtd-rom"; 464 - probe-type = "map_rom"; 465 464 reg = <0x1fc00000 0x2000>; 466 465 467 466 bank-width = <4>;
+1 -1
arch/mips/boot/dts/ralink/mt7621-gnubee-gb-pc1.dts
··· 8 8 9 9 / { 10 10 compatible = "gnubee,gb-pc1", "mediatek,mt7621-soc"; 11 - model = "GB-PC1"; 11 + model = "GnuBee GB-PC1"; 12 12 13 13 memory@0 { 14 14 device_type = "memory";
+1 -1
arch/mips/boot/dts/ralink/mt7621-gnubee-gb-pc2.dts
··· 8 8 9 9 / { 10 10 compatible = "gnubee,gb-pc2", "mediatek,mt7621-soc"; 11 - model = "GB-PC2"; 11 + model = "GnuBee GB-PC2"; 12 12 13 13 memory@0 { 14 14 device_type = "memory";
+2 -3
arch/mips/boot/dts/ralink/mt7621.dtsi
··· 300 300 compatible = "mediatek,mt7621-eth"; 301 301 reg = <0x1e100000 0x10000>; 302 302 303 - clocks = <&sysc MT7621_CLK_FE>, 304 - <&sysc MT7621_CLK_ETH>; 303 + clocks = <&sysc MT7621_CLK_FE>, <&sysc MT7621_CLK_ETH>; 305 304 clock-names = "fe", "ethif"; 306 305 307 306 #address-cells = <1>; 308 307 #size-cells = <0>; 309 308 310 - resets = <&sysc MT7621_RST_FE &sysc MT7621_RST_ETH>; 309 + resets = <&sysc MT7621_RST_FE>, <&sysc MT7621_RST_ETH>; 311 310 reset-names = "fe", "eth"; 312 311 313 312 interrupt-parent = <&gic>;
-119
arch/mips/configs/ar7_defconfig
··· 1 - # CONFIG_LOCALVERSION_AUTO is not set 2 - CONFIG_KERNEL_LZMA=y 3 - CONFIG_SYSVIPC=y 4 - CONFIG_HIGH_RES_TIMERS=y 5 - CONFIG_BSD_PROCESS_ACCT=y 6 - CONFIG_LOG_BUF_SHIFT=14 7 - CONFIG_RELAY=y 8 - CONFIG_BLK_DEV_INITRD=y 9 - CONFIG_EXPERT=y 10 - # CONFIG_ELF_CORE is not set 11 - # CONFIG_KALLSYMS is not set 12 - # CONFIG_VM_EVENT_COUNTERS is not set 13 - # CONFIG_COMPAT_BRK is not set 14 - CONFIG_AR7=y 15 - CONFIG_HZ_100=y 16 - CONFIG_KEXEC=y 17 - # CONFIG_SECCOMP is not set 18 - CONFIG_MODULES=y 19 - CONFIG_MODULE_UNLOAD=y 20 - # CONFIG_BLK_DEV_BSG is not set 21 - CONFIG_PARTITION_ADVANCED=y 22 - CONFIG_BSD_DISKLABEL=y 23 - CONFIG_NET=y 24 - CONFIG_PACKET=y 25 - CONFIG_UNIX=y 26 - CONFIG_INET=y 27 - CONFIG_IP_MULTICAST=y 28 - CONFIG_IP_ADVANCED_ROUTER=y 29 - CONFIG_IP_MULTIPLE_TABLES=y 30 - CONFIG_IP_ROUTE_MULTIPATH=y 31 - CONFIG_IP_ROUTE_VERBOSE=y 32 - CONFIG_IP_MROUTE=y 33 - CONFIG_SYN_COOKIES=y 34 - # CONFIG_INET_DIAG is not set 35 - CONFIG_TCP_CONG_ADVANCED=y 36 - # CONFIG_TCP_CONG_BIC is not set 37 - # CONFIG_TCP_CONG_CUBIC is not set 38 - CONFIG_TCP_CONG_WESTWOOD=y 39 - # CONFIG_TCP_CONG_HTCP is not set 40 - # CONFIG_IPV6 is not set 41 - CONFIG_NETFILTER=y 42 - # CONFIG_BRIDGE_NETFILTER is not set 43 - CONFIG_NF_CONNTRACK=m 44 - CONFIG_NF_CONNTRACK_MARK=y 45 - CONFIG_NF_CONNTRACK_FTP=m 46 - CONFIG_NF_CONNTRACK_IRC=m 47 - CONFIG_NF_CONNTRACK_TFTP=m 48 - CONFIG_NETFILTER_XT_TARGET_TCPMSS=m 49 - CONFIG_NETFILTER_XT_MATCH_LIMIT=m 50 - CONFIG_NETFILTER_XT_MATCH_MAC=m 51 - CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m 52 - CONFIG_NETFILTER_XT_MATCH_STATE=m 53 - CONFIG_IP_NF_IPTABLES=m 54 - CONFIG_IP_NF_FILTER=m 55 - CONFIG_IP_NF_TARGET_REJECT=m 56 - CONFIG_IP_NF_MANGLE=m 57 - CONFIG_IP_NF_RAW=m 58 - CONFIG_ATM=m 59 - CONFIG_ATM_BR2684=m 60 - CONFIG_ATM_BR2684_IPFILTER=y 61 - CONFIG_BRIDGE=y 62 - CONFIG_VLAN_8021Q=y 63 - CONFIG_NET_SCHED=y 64 - CONFIG_NET_CLS_ACT=y 65 - CONFIG_NET_ACT_POLICE=y 66 - CONFIG_HAMRADIO=y 67 - CONFIG_CFG80211=m 68 - CONFIG_MAC80211=m 69 - CONFIG_MTD=y 70 - CONFIG_MTD_BLOCK=y 71 - CONFIG_MTD_CFI=y 72 - CONFIG_MTD_CFI_INTELEXT=y 73 - CONFIG_MTD_CFI_AMDSTD=y 74 - CONFIG_MTD_CFI_STAA=y 75 - CONFIG_MTD_COMPLEX_MAPPINGS=y 76 - CONFIG_MTD_PHYSMAP=y 77 - CONFIG_NETDEVICES=y 78 - CONFIG_CPMAC=y 79 - CONFIG_FIXED_PHY=y 80 - CONFIG_PPP=m 81 - CONFIG_PPP_FILTER=y 82 - CONFIG_PPP_MULTILINK=y 83 - CONFIG_PPPOATM=m 84 - CONFIG_PPPOE=m 85 - CONFIG_PPP_ASYNC=m 86 - # CONFIG_INPUT is not set 87 - # CONFIG_SERIO is not set 88 - # CONFIG_VT is not set 89 - # CONFIG_LEGACY_PTYS is not set 90 - CONFIG_SERIAL_8250=y 91 - CONFIG_SERIAL_8250_CONSOLE=y 92 - CONFIG_SERIAL_8250_NR_UARTS=2 93 - CONFIG_SERIAL_8250_RUNTIME_UARTS=2 94 - CONFIG_HW_RANDOM=y 95 - CONFIG_GPIO_SYSFS=y 96 - # CONFIG_HWMON is not set 97 - CONFIG_WATCHDOG=y 98 - CONFIG_AR7_WDT=y 99 - # CONFIG_USB_SUPPORT is not set 100 - CONFIG_NEW_LEDS=y 101 - CONFIG_LEDS_CLASS=y 102 - CONFIG_LEDS_GPIO=y 103 - CONFIG_LEDS_TRIGGERS=y 104 - CONFIG_LEDS_TRIGGER_TIMER=y 105 - CONFIG_LEDS_TRIGGER_HEARTBEAT=y 106 - CONFIG_LEDS_TRIGGER_DEFAULT_ON=y 107 - # CONFIG_DNOTIFY is not set 108 - CONFIG_PROC_KCORE=y 109 - # CONFIG_PROC_PAGE_MONITOR is not set 110 - CONFIG_TMPFS=y 111 - CONFIG_JFFS2_FS=y 112 - CONFIG_JFFS2_SUMMARY=y 113 - CONFIG_JFFS2_COMPRESSION_OPTIONS=y 114 - CONFIG_SQUASHFS=y 115 - # CONFIG_CRYPTO_HW is not set 116 - CONFIG_STRIP_ASM_SYMS=y 117 - CONFIG_DEBUG_FS=y 118 - CONFIG_CMDLINE_BOOL=y 119 - CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
-1
arch/mips/configs/fuloong2e_defconfig
··· 177 177 CONFIG_EXT3_FS=y 178 178 CONFIG_EXT4_FS_POSIX_ACL=y 179 179 CONFIG_EXT4_FS_SECURITY=y 180 - CONFIG_REISERFS_FS=m 181 180 CONFIG_AUTOFS_FS=y 182 181 CONFIG_FUSE_FS=y 183 182 CONFIG_ISO9660_FS=m
-4
arch/mips/configs/jazz_defconfig
··· 70 70 # CONFIG_HWMON is not set 71 71 CONFIG_EXT2_FS=m 72 72 CONFIG_EXT3_FS=y 73 - CONFIG_REISERFS_FS=m 74 - CONFIG_REISERFS_FS_XATTR=y 75 - CONFIG_REISERFS_FS_POSIX_ACL=y 76 - CONFIG_REISERFS_FS_SECURITY=y 77 73 CONFIG_XFS_FS=m 78 74 CONFIG_XFS_QUOTA=y 79 75 CONFIG_AUTOFS_FS=m
-3
arch/mips/configs/lemote2f_defconfig
··· 229 229 CONFIG_EXT3_FS=y 230 230 CONFIG_EXT3_FS_POSIX_ACL=y 231 231 CONFIG_EXT3_FS_SECURITY=y 232 - CONFIG_REISERFS_FS=m 233 - CONFIG_REISERFS_PROC_INFO=y 234 - CONFIG_REISERFS_FS_XATTR=y 235 232 CONFIG_JFS_FS=m 236 233 CONFIG_JFS_POSIX_ACL=y 237 234 CONFIG_XFS_FS=m
-5
arch/mips/configs/malta_defconfig
··· 317 317 CONFIG_UIO_CIF=m 318 318 CONFIG_EXT2_FS=y 319 319 CONFIG_EXT3_FS=y 320 - CONFIG_REISERFS_FS=m 321 - CONFIG_REISERFS_PROC_INFO=y 322 - CONFIG_REISERFS_FS_XATTR=y 323 - CONFIG_REISERFS_FS_POSIX_ACL=y 324 - CONFIG_REISERFS_FS_SECURITY=y 325 320 CONFIG_JFS_FS=m 326 321 CONFIG_JFS_POSIX_ACL=y 327 322 CONFIG_JFS_SECURITY=y
-5
arch/mips/configs/malta_kvm_defconfig
··· 323 323 CONFIG_UIO_CIF=m 324 324 CONFIG_EXT2_FS=y 325 325 CONFIG_EXT3_FS=y 326 - CONFIG_REISERFS_FS=m 327 - CONFIG_REISERFS_PROC_INFO=y 328 - CONFIG_REISERFS_FS_XATTR=y 329 - CONFIG_REISERFS_FS_POSIX_ACL=y 330 - CONFIG_REISERFS_FS_SECURITY=y 331 326 CONFIG_JFS_FS=m 332 327 CONFIG_JFS_POSIX_ACL=y 333 328 CONFIG_JFS_SECURITY=y
-5
arch/mips/configs/maltaup_xpa_defconfig
··· 323 323 CONFIG_UIO_CIF=m 324 324 CONFIG_EXT2_FS=y 325 325 CONFIG_EXT3_FS=y 326 - CONFIG_REISERFS_FS=m 327 - CONFIG_REISERFS_PROC_INFO=y 328 - CONFIG_REISERFS_FS_XATTR=y 329 - CONFIG_REISERFS_FS_POSIX_ACL=y 330 - CONFIG_REISERFS_FS_SECURITY=y 331 326 CONFIG_JFS_FS=m 332 327 CONFIG_JFS_POSIX_ACL=y 333 328 CONFIG_JFS_SECURITY=y
-4
arch/mips/configs/rm200_defconfig
··· 310 310 CONFIG_USB_TEST=m 311 311 CONFIG_EXT2_FS=m 312 312 CONFIG_EXT3_FS=y 313 - CONFIG_REISERFS_FS=m 314 - CONFIG_REISERFS_FS_XATTR=y 315 - CONFIG_REISERFS_FS_POSIX_ACL=y 316 - CONFIG_REISERFS_FS_SECURITY=y 317 313 CONFIG_XFS_FS=m 318 314 CONFIG_XFS_QUOTA=y 319 315 CONFIG_AUTOFS_FS=m
-191
arch/mips/include/asm/mach-ar7/ar7.h
··· 1 - /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 - /* 3 - * Copyright (C) 2006,2007 Felix Fietkau <nbd@openwrt.org> 4 - * Copyright (C) 2006,2007 Eugene Konev <ejka@openwrt.org> 5 - */ 6 - 7 - #ifndef __AR7_H__ 8 - #define __AR7_H__ 9 - 10 - #include <linux/delay.h> 11 - #include <linux/io.h> 12 - #include <linux/errno.h> 13 - 14 - #include <asm/addrspace.h> 15 - 16 - #define AR7_SDRAM_BASE 0x14000000 17 - 18 - #define AR7_REGS_BASE 0x08610000 19 - 20 - #define AR7_REGS_MAC0 (AR7_REGS_BASE + 0x0000) 21 - #define AR7_REGS_GPIO (AR7_REGS_BASE + 0x0900) 22 - /* 0x08610A00 - 0x08610BFF (512 bytes, 128 bytes / clock) */ 23 - #define AR7_REGS_POWER (AR7_REGS_BASE + 0x0a00) 24 - #define AR7_REGS_CLOCKS (AR7_REGS_POWER + 0x80) 25 - #define UR8_REGS_CLOCKS (AR7_REGS_POWER + 0x20) 26 - #define AR7_REGS_UART0 (AR7_REGS_BASE + 0x0e00) 27 - #define AR7_REGS_USB (AR7_REGS_BASE + 0x1200) 28 - #define AR7_REGS_RESET (AR7_REGS_BASE + 0x1600) 29 - #define AR7_REGS_PINSEL (AR7_REGS_BASE + 0x160C) 30 - #define AR7_REGS_VLYNQ0 (AR7_REGS_BASE + 0x1800) 31 - #define AR7_REGS_DCL (AR7_REGS_BASE + 0x1a00) 32 - #define AR7_REGS_VLYNQ1 (AR7_REGS_BASE + 0x1c00) 33 - #define AR7_REGS_MDIO (AR7_REGS_BASE + 0x1e00) 34 - #define AR7_REGS_IRQ (AR7_REGS_BASE + 0x2400) 35 - #define AR7_REGS_MAC1 (AR7_REGS_BASE + 0x2800) 36 - 37 - #define AR7_REGS_WDT (AR7_REGS_BASE + 0x1f00) 38 - #define UR8_REGS_WDT (AR7_REGS_BASE + 0x0b00) 39 - #define UR8_REGS_UART1 (AR7_REGS_BASE + 0x0f00) 40 - 41 - /* Titan registers */ 42 - #define TITAN_REGS_ESWITCH_BASE (0x08640000) 43 - #define TITAN_REGS_MAC0 (TITAN_REGS_ESWITCH_BASE) 44 - #define TITAN_REGS_MAC1 (TITAN_REGS_ESWITCH_BASE + 0x0800) 45 - #define TITAN_REGS_MDIO (TITAN_REGS_ESWITCH_BASE + 0x02000) 46 - #define TITAN_REGS_VLYNQ0 (AR7_REGS_BASE + 0x1c00) 47 - #define TITAN_REGS_VLYNQ1 (AR7_REGS_BASE + 0x1300) 48 - 49 - #define AR7_RESET_PERIPHERAL 0x0 50 - #define AR7_RESET_SOFTWARE 0x4 51 - #define AR7_RESET_STATUS 0x8 52 - 53 - #define AR7_RESET_BIT_CPMAC_LO 17 54 - #define AR7_RESET_BIT_CPMAC_HI 21 55 - #define AR7_RESET_BIT_MDIO 22 56 - #define AR7_RESET_BIT_EPHY 26 57 - 58 - #define TITAN_RESET_BIT_EPHY1 28 59 - 60 - /* GPIO control registers */ 61 - #define AR7_GPIO_INPUT 0x0 62 - #define AR7_GPIO_OUTPUT 0x4 63 - #define AR7_GPIO_DIR 0x8 64 - #define AR7_GPIO_ENABLE 0xc 65 - #define TITAN_GPIO_INPUT_0 0x0 66 - #define TITAN_GPIO_INPUT_1 0x4 67 - #define TITAN_GPIO_OUTPUT_0 0x8 68 - #define TITAN_GPIO_OUTPUT_1 0xc 69 - #define TITAN_GPIO_DIR_0 0x10 70 - #define TITAN_GPIO_DIR_1 0x14 71 - #define TITAN_GPIO_ENBL_0 0x18 72 - #define TITAN_GPIO_ENBL_1 0x1c 73 - 74 - #define AR7_CHIP_7100 0x18 75 - #define AR7_CHIP_7200 0x2b 76 - #define AR7_CHIP_7300 0x05 77 - #define AR7_CHIP_TITAN 0x07 78 - #define TITAN_CHIP_1050 0x0f 79 - #define TITAN_CHIP_1055 0x0e 80 - #define TITAN_CHIP_1056 0x0d 81 - #define TITAN_CHIP_1060 0x07 82 - 83 - /* Interrupts */ 84 - #define AR7_IRQ_UART0 15 85 - #define AR7_IRQ_UART1 16 86 - 87 - /* Clocks */ 88 - #define AR7_AFE_CLOCK 35328000 89 - #define AR7_REF_CLOCK 25000000 90 - #define AR7_XTAL_CLOCK 24000000 91 - 92 - /* DCL */ 93 - #define AR7_WDT_HW_ENA 0x10 94 - 95 - struct plat_cpmac_data { 96 - int reset_bit; 97 - int power_bit; 98 - u32 phy_mask; 99 - char dev_addr[6]; 100 - }; 101 - 102 - struct plat_dsl_data { 103 - int reset_bit_dsl; 104 - int reset_bit_sar; 105 - }; 106 - 107 - static inline int ar7_is_titan(void) 108 - { 109 - return (readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x24)) & 0xffff) == 110 - AR7_CHIP_TITAN; 111 - } 112 - 113 - static inline u16 ar7_chip_id(void) 114 - { 115 - return ar7_is_titan() ? AR7_CHIP_TITAN : (readl((void *) 116 - KSEG1ADDR(AR7_REGS_GPIO + 0x14)) & 0xffff); 117 - } 118 - 119 - static inline u16 titan_chip_id(void) 120 - { 121 - unsigned int val = readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 122 - TITAN_GPIO_INPUT_1)); 123 - return ((val >> 12) & 0x0f); 124 - } 125 - 126 - static inline u8 ar7_chip_rev(void) 127 - { 128 - return (readl((void *)KSEG1ADDR(AR7_REGS_GPIO + (ar7_is_titan() ? 0x24 : 129 - 0x14))) >> 16) & 0xff; 130 - } 131 - 132 - static inline int ar7_has_high_cpmac(void) 133 - { 134 - u16 chip_id = ar7_chip_id(); 135 - switch (chip_id) { 136 - case AR7_CHIP_7100: 137 - case AR7_CHIP_7200: 138 - return 0; 139 - case AR7_CHIP_7300: 140 - return 1; 141 - default: 142 - return -ENXIO; 143 - } 144 - } 145 - #define ar7_has_high_vlynq ar7_has_high_cpmac 146 - #define ar7_has_second_uart ar7_has_high_cpmac 147 - 148 - static inline void ar7_device_enable(u32 bit) 149 - { 150 - void *reset_reg = 151 - (void *)KSEG1ADDR(AR7_REGS_RESET + AR7_RESET_PERIPHERAL); 152 - writel(readl(reset_reg) | (1 << bit), reset_reg); 153 - msleep(20); 154 - } 155 - 156 - static inline void ar7_device_disable(u32 bit) 157 - { 158 - void *reset_reg = 159 - (void *)KSEG1ADDR(AR7_REGS_RESET + AR7_RESET_PERIPHERAL); 160 - writel(readl(reset_reg) & ~(1 << bit), reset_reg); 161 - msleep(20); 162 - } 163 - 164 - static inline void ar7_device_reset(u32 bit) 165 - { 166 - ar7_device_disable(bit); 167 - ar7_device_enable(bit); 168 - } 169 - 170 - static inline void ar7_device_on(u32 bit) 171 - { 172 - void *power_reg = (void *)KSEG1ADDR(AR7_REGS_POWER); 173 - writel(readl(power_reg) | (1 << bit), power_reg); 174 - msleep(20); 175 - } 176 - 177 - static inline void ar7_device_off(u32 bit) 178 - { 179 - void *power_reg = (void *)KSEG1ADDR(AR7_REGS_POWER); 180 - writel(readl(power_reg) & ~(1 << bit), power_reg); 181 - msleep(20); 182 - } 183 - 184 - int __init ar7_gpio_init(void); 185 - void __init ar7_init_clocks(void); 186 - 187 - /* Board specific GPIO functions */ 188 - int ar7_gpio_enable(unsigned gpio); 189 - int ar7_gpio_disable(unsigned gpio); 190 - 191 - #endif /* __AR7_H__ */
-16
arch/mips/include/asm/mach-ar7/irq.h
··· 1 - /* 2 - * This file is subject to the terms and conditions of the GNU General Public 3 - * License. See the file "COPYING" in the main directory of this archive 4 - * for more details. 5 - * 6 - * Shamelessly copied from asm-mips/mach-emma2rh/ 7 - * Copyright (C) 2003 by Ralf Baechle 8 - */ 9 - #ifndef __ASM_AR7_IRQ_H 10 - #define __ASM_AR7_IRQ_H 11 - 12 - #define NR_IRQS 256 13 - 14 - #include <asm/mach-generic/irq.h> 15 - 16 - #endif /* __ASM_AR7_IRQ_H */
-12
arch/mips/include/asm/mach-ar7/prom.h
··· 1 - /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 - /* 3 - * Copyright (C) 2006, 2007 Florian Fainelli <florian@openwrt.org> 4 - */ 5 - 6 - #ifndef __PROM_H__ 7 - #define __PROM_H__ 8 - 9 - extern char *prom_getenv(const char *name); 10 - extern void prom_meminit(void); 11 - 12 - #endif /* __PROM_H__ */
-22
arch/mips/include/asm/mach-ar7/spaces.h
··· 1 - /* 2 - * This file is subject to the terms and conditions of the GNU General Public 3 - * License. See the file "COPYING" in the main directory of this archive 4 - * for more details. 5 - * 6 - * Copyright (C) 1994 - 1999, 2000, 03, 04 Ralf Baechle 7 - * Copyright (C) 2000, 2002 Maciej W. Rozycki 8 - * Copyright (C) 1990, 1999, 2000 Silicon Graphics, Inc. 9 - */ 10 - #ifndef _ASM_AR7_SPACES_H 11 - #define _ASM_AR7_SPACES_H 12 - 13 - /* 14 - * This handles the memory map. 15 - * We handle pages at KSEG0 for kernels with 32 bit address space. 16 - */ 17 - #define PAGE_OFFSET _AC(0x94000000, UL) 18 - #define PHYS_OFFSET _AC(0x14000000, UL) 19 - 20 - #include <asm/mach-generic/spaces.h> 21 - 22 - #endif /* __ASM_AR7_SPACES_H */
-21
arch/mips/include/asm/mach-loongson32/dma.h
··· 1 - /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 - /* 3 - * Copyright (c) 2015 Zhang, Keguang <keguang.zhang@gmail.com> 4 - * 5 - * Loongson 1 NAND platform support. 6 - */ 7 - 8 - #ifndef __ASM_MACH_LOONGSON32_DMA_H 9 - #define __ASM_MACH_LOONGSON32_DMA_H 10 - 11 - #define LS1X_DMA_CHANNEL0 0 12 - #define LS1X_DMA_CHANNEL1 1 13 - #define LS1X_DMA_CHANNEL2 2 14 - 15 - struct plat_ls1x_dma { 16 - int nr_channels; 17 - }; 18 - 19 - extern struct plat_ls1x_dma ls1b_dma_pdata; 20 - 21 - #endif /* __ASM_MACH_LOONGSON32_DMA_H */
-26
arch/mips/include/asm/mach-loongson32/nand.h
··· 1 - /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 - /* 3 - * Copyright (c) 2015 Zhang, Keguang <keguang.zhang@gmail.com> 4 - * 5 - * Loongson 1 NAND platform support. 6 - */ 7 - 8 - #ifndef __ASM_MACH_LOONGSON32_NAND_H 9 - #define __ASM_MACH_LOONGSON32_NAND_H 10 - 11 - #include <linux/dmaengine.h> 12 - #include <linux/mtd/partitions.h> 13 - 14 - struct plat_ls1x_nand { 15 - struct mtd_partition *parts; 16 - unsigned int nr_parts; 17 - 18 - int hold_cycle; 19 - int wait_cycle; 20 - }; 21 - 22 - extern struct plat_ls1x_nand ls1b_nand_pdata; 23 - 24 - bool ls1x_dma_filter_fn(struct dma_chan *chan, void *param); 25 - 26 - #endif /* __ASM_MACH_LOONGSON32_NAND_H */
-3
arch/mips/include/asm/mach-loongson32/platform.h
··· 8 8 9 9 #include <linux/platform_device.h> 10 10 11 - #include <dma.h> 12 - #include <nand.h> 13 - 14 11 extern struct platform_device ls1x_uart_pdev; 15 12 extern struct platform_device ls1x_eth0_pdev; 16 13 extern struct platform_device ls1x_eth1_pdev;
-1
arch/mips/kernel/relocate_kernel.S
··· 66 66 LONG_ADDIU s6, s6, -1 67 67 beq s6, zero, process_entry 68 68 b copy_word 69 - b process_entry 70 69 71 70 done: 72 71 #ifdef CONFIG_SMP
-2
arch/mips/loongson32/common/platform.c
··· 15 15 16 16 #include <platform.h> 17 17 #include <loongson1.h> 18 - #include <dma.h> 19 - #include <nand.h> 20 18 21 19 /* 8250/16550 compatible UART */ 22 20 #define LS1X_UART(_id) \
-2
arch/mips/loongson32/ls1b/board.c
··· 8 8 #include <linux/sizes.h> 9 9 10 10 #include <loongson1.h> 11 - #include <dma.h> 12 - #include <nand.h> 13 11 #include <platform.h> 14 12 15 13 static const struct gpio_led ls1x_gpio_leds[] __initconst = {
+1 -1
arch/mips/pci/fixup-lantiq.c
··· 4 4 * Copyright (C) 2012 John Crispin <john@phrozen.org> 5 5 */ 6 6 7 - #include <linux/of_irq.h> 8 7 #include <linux/of_pci.h> 8 + #include <linux/pci.h> 9 9 10 10 int (*ltq_pci_plat_arch_init)(struct pci_dev *dev) = NULL; 11 11 int (*ltq_pci_plat_dev_init)(struct pci_dev *dev) = NULL;
-2
drivers/Kconfig
··· 135 135 136 136 source "drivers/vfio/Kconfig" 137 137 138 - source "drivers/vlynq/Kconfig" 139 - 140 138 source "drivers/virt/Kconfig" 141 139 142 140 source "drivers/virtio/Kconfig"
-1
drivers/Makefile
··· 151 151 obj-$(CONFIG_VHOST_RING) += vhost/ 152 152 obj-$(CONFIG_VHOST_IOTLB) += vhost/ 153 153 obj-$(CONFIG_VHOST) += vhost/ 154 - obj-$(CONFIG_VLYNQ) += vlynq/ 155 154 obj-$(CONFIG_GREYBUS) += greybus/ 156 155 obj-$(CONFIG_COMEDI) += comedi/ 157 156 obj-$(CONFIG_STAGING) += staging/
-5
drivers/mtd/parsers/Kconfig
··· 1 1 # SPDX-License-Identifier: GPL-2.0-only 2 - config MTD_AR7_PARTS 3 - tristate "TI AR7 partitioning parser" 4 - help 5 - TI AR7 partitioning parser support 6 - 7 2 config MTD_BCM47XX_PARTS 8 3 tristate "BCM47XX partitioning parser" 9 4 depends on BCM47XX || ARCH_BCM_5301X
-1
drivers/mtd/parsers/Makefile
··· 1 1 # SPDX-License-Identifier: GPL-2.0-only 2 - obj-$(CONFIG_MTD_AR7_PARTS) += ar7part.o 3 2 obj-$(CONFIG_MTD_BCM47XX_PARTS) += bcm47xxpart.o 4 3 obj-$(CONFIG_MTD_BCM63XX_PARTS) += bcm63xxpart.o 5 4 obj-$(CONFIG_MTD_BRCM_U_BOOT) += brcm_u-boot.o
-129
drivers/mtd/parsers/ar7part.c
··· 1 - // SPDX-License-Identifier: GPL-2.0-or-later 2 - /* 3 - * Copyright © 2007 Eugene Konev <ejka@openwrt.org> 4 - * 5 - * TI AR7 flash partition table. 6 - * Based on ar7 map by Felix Fietkau <nbd@openwrt.org> 7 - */ 8 - 9 - #include <linux/kernel.h> 10 - #include <linux/slab.h> 11 - 12 - #include <linux/mtd/mtd.h> 13 - #include <linux/mtd/partitions.h> 14 - #include <linux/memblock.h> 15 - #include <linux/module.h> 16 - 17 - #include <uapi/linux/magic.h> 18 - 19 - #define AR7_PARTS 4 20 - #define ROOT_OFFSET 0xe0000 21 - 22 - #define LOADER_MAGIC1 le32_to_cpu(0xfeedfa42) 23 - #define LOADER_MAGIC2 le32_to_cpu(0xfeed1281) 24 - 25 - struct ar7_bin_rec { 26 - unsigned int checksum; 27 - unsigned int length; 28 - unsigned int address; 29 - }; 30 - 31 - static int create_mtd_partitions(struct mtd_info *master, 32 - const struct mtd_partition **pparts, 33 - struct mtd_part_parser_data *data) 34 - { 35 - struct ar7_bin_rec header; 36 - unsigned int offset; 37 - size_t len; 38 - unsigned int pre_size = master->erasesize, post_size = 0; 39 - unsigned int root_offset = ROOT_OFFSET; 40 - 41 - int retries = 10; 42 - struct mtd_partition *ar7_parts; 43 - 44 - ar7_parts = kcalloc(AR7_PARTS, sizeof(*ar7_parts), GFP_KERNEL); 45 - if (!ar7_parts) 46 - return -ENOMEM; 47 - ar7_parts[0].name = "loader"; 48 - ar7_parts[0].offset = 0; 49 - ar7_parts[0].size = master->erasesize; 50 - ar7_parts[0].mask_flags = MTD_WRITEABLE; 51 - 52 - ar7_parts[1].name = "config"; 53 - ar7_parts[1].offset = 0; 54 - ar7_parts[1].size = master->erasesize; 55 - ar7_parts[1].mask_flags = 0; 56 - 57 - do { /* Try 10 blocks starting from master->erasesize */ 58 - offset = pre_size; 59 - mtd_read(master, offset, sizeof(header), &len, 60 - (uint8_t *)&header); 61 - if (!strncmp((char *)&header, "TIENV0.8", 8)) 62 - ar7_parts[1].offset = pre_size; 63 - if (header.checksum == LOADER_MAGIC1) 64 - break; 65 - if (header.checksum == LOADER_MAGIC2) 66 - break; 67 - pre_size += master->erasesize; 68 - } while (retries--); 69 - 70 - pre_size = offset; 71 - 72 - if (!ar7_parts[1].offset) { 73 - ar7_parts[1].offset = master->size - master->erasesize; 74 - post_size = master->erasesize; 75 - } 76 - 77 - switch (header.checksum) { 78 - case LOADER_MAGIC1: 79 - while (header.length) { 80 - offset += sizeof(header) + header.length; 81 - mtd_read(master, offset, sizeof(header), &len, 82 - (uint8_t *)&header); 83 - } 84 - root_offset = offset + sizeof(header) + 4; 85 - break; 86 - case LOADER_MAGIC2: 87 - while (header.length) { 88 - offset += sizeof(header) + header.length; 89 - mtd_read(master, offset, sizeof(header), &len, 90 - (uint8_t *)&header); 91 - } 92 - root_offset = offset + sizeof(header) + 4 + 0xff; 93 - root_offset &= ~(uint32_t)0xff; 94 - break; 95 - default: 96 - printk(KERN_WARNING "Unknown magic: %08x\n", header.checksum); 97 - break; 98 - } 99 - 100 - mtd_read(master, root_offset, sizeof(header), &len, (u8 *)&header); 101 - if (header.checksum != SQUASHFS_MAGIC) { 102 - root_offset += master->erasesize - 1; 103 - root_offset &= ~(master->erasesize - 1); 104 - } 105 - 106 - ar7_parts[2].name = "linux"; 107 - ar7_parts[2].offset = pre_size; 108 - ar7_parts[2].size = master->size - pre_size - post_size; 109 - ar7_parts[2].mask_flags = 0; 110 - 111 - ar7_parts[3].name = "rootfs"; 112 - ar7_parts[3].offset = root_offset; 113 - ar7_parts[3].size = master->size - root_offset - post_size; 114 - ar7_parts[3].mask_flags = 0; 115 - 116 - *pparts = ar7_parts; 117 - return AR7_PARTS; 118 - } 119 - 120 - static struct mtd_part_parser ar7_parser = { 121 - .parse_fn = create_mtd_partitions, 122 - .name = "ar7part", 123 - }; 124 - module_mtd_part_parser(ar7_parser); 125 - 126 - MODULE_LICENSE("GPL"); 127 - MODULE_AUTHOR( "Felix Fietkau <nbd@openwrt.org>, " 128 - "Eugene Konev <ejka@openwrt.org>"); 129 - MODULE_DESCRIPTION("MTD partitioning for TI AR7");
-7
drivers/tty/serial/8250/8250_port.c
··· 170 170 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, 171 171 .flags = UART_CAP_FIFO, 172 172 }, 173 - [PORT_AR7] = { 174 - .name = "AR7", 175 - .fifo_size = 16, 176 - .tx_loadsz = 16, 177 - .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00, 178 - .flags = UART_CAP_FIFO /* | UART_CAP_AFE */, 179 - }, 180 173 [PORT_U6_16550A] = { 181 174 .name = "U6_16550A", 182 175 .fifo_size = 64,
-21
drivers/vlynq/Kconfig
··· 1 - # SPDX-License-Identifier: GPL-2.0-only 2 - menu "TI VLYNQ" 3 - depends on AR7 4 - 5 - config VLYNQ 6 - bool "TI VLYNQ bus support" 7 - help 8 - Support for Texas Instruments(R) VLYNQ bus. 9 - The VLYNQ bus is a high-speed, serial and packetized 10 - data bus which allows external peripherals of a SoC 11 - to appear into the system's main memory. 12 - 13 - If unsure, say N 14 - 15 - config VLYNQ_DEBUG 16 - bool "VLYNQ bus debug" 17 - depends on VLYNQ && DEBUG_KERNEL 18 - help 19 - Turn on VLYNQ bus debugging. 20 - 21 - endmenu
-6
drivers/vlynq/Makefile
··· 1 - # SPDX-License-Identifier: GPL-2.0-only 2 - # 3 - # Makefile for kernel vlynq drivers 4 - # 5 - 6 - obj-$(CONFIG_VLYNQ) += vlynq.o
-799
drivers/vlynq/vlynq.c
··· 1 - // SPDX-License-Identifier: GPL-2.0-or-later 2 - /* 3 - * Copyright (C) 2006, 2007 Eugene Konev <ejka@openwrt.org> 4 - * 5 - * Parts of the VLYNQ specification can be found here: 6 - * http://www.ti.com/litv/pdf/sprue36a 7 - */ 8 - 9 - #include <linux/init.h> 10 - #include <linux/types.h> 11 - #include <linux/kernel.h> 12 - #include <linux/string.h> 13 - #include <linux/device.h> 14 - #include <linux/module.h> 15 - #include <linux/errno.h> 16 - #include <linux/platform_device.h> 17 - #include <linux/interrupt.h> 18 - #include <linux/delay.h> 19 - #include <linux/io.h> 20 - #include <linux/slab.h> 21 - #include <linux/irq.h> 22 - 23 - #include <linux/vlynq.h> 24 - 25 - #define VLYNQ_CTRL_PM_ENABLE 0x80000000 26 - #define VLYNQ_CTRL_CLOCK_INT 0x00008000 27 - #define VLYNQ_CTRL_CLOCK_DIV(x) (((x) & 7) << 16) 28 - #define VLYNQ_CTRL_INT_LOCAL 0x00004000 29 - #define VLYNQ_CTRL_INT_ENABLE 0x00002000 30 - #define VLYNQ_CTRL_INT_VECTOR(x) (((x) & 0x1f) << 8) 31 - #define VLYNQ_CTRL_INT2CFG 0x00000080 32 - #define VLYNQ_CTRL_RESET 0x00000001 33 - 34 - #define VLYNQ_CTRL_CLOCK_MASK (0x7 << 16) 35 - 36 - #define VLYNQ_INT_OFFSET 0x00000014 37 - #define VLYNQ_REMOTE_OFFSET 0x00000080 38 - 39 - #define VLYNQ_STATUS_LINK 0x00000001 40 - #define VLYNQ_STATUS_LERROR 0x00000080 41 - #define VLYNQ_STATUS_RERROR 0x00000100 42 - 43 - #define VINT_ENABLE 0x00000100 44 - #define VINT_TYPE_EDGE 0x00000080 45 - #define VINT_LEVEL_LOW 0x00000040 46 - #define VINT_VECTOR(x) ((x) & 0x1f) 47 - #define VINT_OFFSET(irq) (8 * ((irq) % 4)) 48 - 49 - #define VLYNQ_AUTONEGO_V2 0x00010000 50 - 51 - struct vlynq_regs { 52 - u32 revision; 53 - u32 control; 54 - u32 status; 55 - u32 int_prio; 56 - u32 int_status; 57 - u32 int_pending; 58 - u32 int_ptr; 59 - u32 tx_offset; 60 - struct vlynq_mapping rx_mapping[4]; 61 - u32 chip; 62 - u32 autonego; 63 - u32 unused[6]; 64 - u32 int_device[8]; 65 - }; 66 - 67 - #ifdef CONFIG_VLYNQ_DEBUG 68 - static void vlynq_dump_regs(struct vlynq_device *dev) 69 - { 70 - int i; 71 - 72 - printk(KERN_DEBUG "VLYNQ local=%p remote=%p\n", 73 - dev->local, dev->remote); 74 - for (i = 0; i < 32; i++) { 75 - printk(KERN_DEBUG "VLYNQ: local %d: %08x\n", 76 - i + 1, ((u32 *)dev->local)[i]); 77 - printk(KERN_DEBUG "VLYNQ: remote %d: %08x\n", 78 - i + 1, ((u32 *)dev->remote)[i]); 79 - } 80 - } 81 - 82 - static void vlynq_dump_mem(u32 *base, int count) 83 - { 84 - int i; 85 - 86 - for (i = 0; i < (count + 3) / 4; i++) { 87 - if (i % 4 == 0) 88 - printk(KERN_DEBUG "\nMEM[0x%04x]:", i * 4); 89 - printk(KERN_DEBUG " 0x%08x", *(base + i)); 90 - } 91 - printk(KERN_DEBUG "\n"); 92 - } 93 - #endif 94 - 95 - /* Check the VLYNQ link status with a given device */ 96 - static int vlynq_linked(struct vlynq_device *dev) 97 - { 98 - int i; 99 - 100 - for (i = 0; i < 100; i++) 101 - if (readl(&dev->local->status) & VLYNQ_STATUS_LINK) 102 - return 1; 103 - else 104 - cpu_relax(); 105 - 106 - return 0; 107 - } 108 - 109 - static void vlynq_reset(struct vlynq_device *dev) 110 - { 111 - writel(readl(&dev->local->control) | VLYNQ_CTRL_RESET, 112 - &dev->local->control); 113 - 114 - /* Wait for the devices to finish resetting */ 115 - msleep(5); 116 - 117 - /* Remove reset bit */ 118 - writel(readl(&dev->local->control) & ~VLYNQ_CTRL_RESET, 119 - &dev->local->control); 120 - 121 - /* Give some time for the devices to settle */ 122 - msleep(5); 123 - } 124 - 125 - static void vlynq_irq_unmask(struct irq_data *d) 126 - { 127 - struct vlynq_device *dev = irq_data_get_irq_chip_data(d); 128 - int virq; 129 - u32 val; 130 - 131 - BUG_ON(!dev); 132 - virq = d->irq - dev->irq_start; 133 - val = readl(&dev->remote->int_device[virq >> 2]); 134 - val |= (VINT_ENABLE | virq) << VINT_OFFSET(virq); 135 - writel(val, &dev->remote->int_device[virq >> 2]); 136 - } 137 - 138 - static void vlynq_irq_mask(struct irq_data *d) 139 - { 140 - struct vlynq_device *dev = irq_data_get_irq_chip_data(d); 141 - int virq; 142 - u32 val; 143 - 144 - BUG_ON(!dev); 145 - virq = d->irq - dev->irq_start; 146 - val = readl(&dev->remote->int_device[virq >> 2]); 147 - val &= ~(VINT_ENABLE << VINT_OFFSET(virq)); 148 - writel(val, &dev->remote->int_device[virq >> 2]); 149 - } 150 - 151 - static int vlynq_irq_type(struct irq_data *d, unsigned int flow_type) 152 - { 153 - struct vlynq_device *dev = irq_data_get_irq_chip_data(d); 154 - int virq; 155 - u32 val; 156 - 157 - BUG_ON(!dev); 158 - virq = d->irq - dev->irq_start; 159 - val = readl(&dev->remote->int_device[virq >> 2]); 160 - switch (flow_type & IRQ_TYPE_SENSE_MASK) { 161 - case IRQ_TYPE_EDGE_RISING: 162 - case IRQ_TYPE_EDGE_FALLING: 163 - case IRQ_TYPE_EDGE_BOTH: 164 - val |= VINT_TYPE_EDGE << VINT_OFFSET(virq); 165 - val &= ~(VINT_LEVEL_LOW << VINT_OFFSET(virq)); 166 - break; 167 - case IRQ_TYPE_LEVEL_HIGH: 168 - val &= ~(VINT_TYPE_EDGE << VINT_OFFSET(virq)); 169 - val &= ~(VINT_LEVEL_LOW << VINT_OFFSET(virq)); 170 - break; 171 - case IRQ_TYPE_LEVEL_LOW: 172 - val &= ~(VINT_TYPE_EDGE << VINT_OFFSET(virq)); 173 - val |= VINT_LEVEL_LOW << VINT_OFFSET(virq); 174 - break; 175 - default: 176 - return -EINVAL; 177 - } 178 - writel(val, &dev->remote->int_device[virq >> 2]); 179 - return 0; 180 - } 181 - 182 - static void vlynq_local_ack(struct irq_data *d) 183 - { 184 - struct vlynq_device *dev = irq_data_get_irq_chip_data(d); 185 - u32 status = readl(&dev->local->status); 186 - 187 - pr_debug("%s: local status: 0x%08x\n", 188 - dev_name(&dev->dev), status); 189 - writel(status, &dev->local->status); 190 - } 191 - 192 - static void vlynq_remote_ack(struct irq_data *d) 193 - { 194 - struct vlynq_device *dev = irq_data_get_irq_chip_data(d); 195 - u32 status = readl(&dev->remote->status); 196 - 197 - pr_debug("%s: remote status: 0x%08x\n", 198 - dev_name(&dev->dev), status); 199 - writel(status, &dev->remote->status); 200 - } 201 - 202 - static irqreturn_t vlynq_irq(int irq, void *dev_id) 203 - { 204 - struct vlynq_device *dev = dev_id; 205 - u32 status; 206 - int virq = 0; 207 - 208 - status = readl(&dev->local->int_status); 209 - writel(status, &dev->local->int_status); 210 - 211 - if (unlikely(!status)) 212 - spurious_interrupt(); 213 - 214 - while (status) { 215 - if (status & 1) 216 - do_IRQ(dev->irq_start + virq); 217 - status >>= 1; 218 - virq++; 219 - } 220 - 221 - return IRQ_HANDLED; 222 - } 223 - 224 - static struct irq_chip vlynq_irq_chip = { 225 - .name = "vlynq", 226 - .irq_unmask = vlynq_irq_unmask, 227 - .irq_mask = vlynq_irq_mask, 228 - .irq_set_type = vlynq_irq_type, 229 - }; 230 - 231 - static struct irq_chip vlynq_local_chip = { 232 - .name = "vlynq local error", 233 - .irq_unmask = vlynq_irq_unmask, 234 - .irq_mask = vlynq_irq_mask, 235 - .irq_ack = vlynq_local_ack, 236 - }; 237 - 238 - static struct irq_chip vlynq_remote_chip = { 239 - .name = "vlynq local error", 240 - .irq_unmask = vlynq_irq_unmask, 241 - .irq_mask = vlynq_irq_mask, 242 - .irq_ack = vlynq_remote_ack, 243 - }; 244 - 245 - static int vlynq_setup_irq(struct vlynq_device *dev) 246 - { 247 - u32 val; 248 - int i, virq; 249 - 250 - if (dev->local_irq == dev->remote_irq) { 251 - printk(KERN_ERR 252 - "%s: local vlynq irq should be different from remote\n", 253 - dev_name(&dev->dev)); 254 - return -EINVAL; 255 - } 256 - 257 - /* Clear local and remote error bits */ 258 - writel(readl(&dev->local->status), &dev->local->status); 259 - writel(readl(&dev->remote->status), &dev->remote->status); 260 - 261 - /* Now setup interrupts */ 262 - val = VLYNQ_CTRL_INT_VECTOR(dev->local_irq); 263 - val |= VLYNQ_CTRL_INT_ENABLE | VLYNQ_CTRL_INT_LOCAL | 264 - VLYNQ_CTRL_INT2CFG; 265 - val |= readl(&dev->local->control); 266 - writel(VLYNQ_INT_OFFSET, &dev->local->int_ptr); 267 - writel(val, &dev->local->control); 268 - 269 - val = VLYNQ_CTRL_INT_VECTOR(dev->remote_irq); 270 - val |= VLYNQ_CTRL_INT_ENABLE; 271 - val |= readl(&dev->remote->control); 272 - writel(VLYNQ_INT_OFFSET, &dev->remote->int_ptr); 273 - writel(val, &dev->remote->int_ptr); 274 - writel(val, &dev->remote->control); 275 - 276 - for (i = dev->irq_start; i <= dev->irq_end; i++) { 277 - virq = i - dev->irq_start; 278 - if (virq == dev->local_irq) { 279 - irq_set_chip_and_handler(i, &vlynq_local_chip, 280 - handle_level_irq); 281 - irq_set_chip_data(i, dev); 282 - } else if (virq == dev->remote_irq) { 283 - irq_set_chip_and_handler(i, &vlynq_remote_chip, 284 - handle_level_irq); 285 - irq_set_chip_data(i, dev); 286 - } else { 287 - irq_set_chip_and_handler(i, &vlynq_irq_chip, 288 - handle_simple_irq); 289 - irq_set_chip_data(i, dev); 290 - writel(0, &dev->remote->int_device[virq >> 2]); 291 - } 292 - } 293 - 294 - if (request_irq(dev->irq, vlynq_irq, IRQF_SHARED, "vlynq", dev)) { 295 - printk(KERN_ERR "%s: request_irq failed\n", 296 - dev_name(&dev->dev)); 297 - return -EAGAIN; 298 - } 299 - 300 - return 0; 301 - } 302 - 303 - static void vlynq_device_release(struct device *dev) 304 - { 305 - struct vlynq_device *vdev = to_vlynq_device(dev); 306 - kfree(vdev); 307 - } 308 - 309 - static int vlynq_device_match(struct device *dev, 310 - struct device_driver *drv) 311 - { 312 - struct vlynq_device *vdev = to_vlynq_device(dev); 313 - struct vlynq_driver *vdrv = to_vlynq_driver(drv); 314 - struct vlynq_device_id *ids = vdrv->id_table; 315 - 316 - while (ids->id) { 317 - if (ids->id == vdev->dev_id) { 318 - vdev->divisor = ids->divisor; 319 - vlynq_set_drvdata(vdev, ids); 320 - printk(KERN_INFO "Driver found for VLYNQ " 321 - "device: %08x\n", vdev->dev_id); 322 - return 1; 323 - } 324 - printk(KERN_DEBUG "Not using the %08x VLYNQ device's driver" 325 - " for VLYNQ device: %08x\n", ids->id, vdev->dev_id); 326 - ids++; 327 - } 328 - return 0; 329 - } 330 - 331 - static int vlynq_device_probe(struct device *dev) 332 - { 333 - struct vlynq_device *vdev = to_vlynq_device(dev); 334 - struct vlynq_driver *drv = to_vlynq_driver(dev->driver); 335 - struct vlynq_device_id *id = vlynq_get_drvdata(vdev); 336 - int result = -ENODEV; 337 - 338 - if (drv->probe) 339 - result = drv->probe(vdev, id); 340 - if (result) 341 - put_device(dev); 342 - return result; 343 - } 344 - 345 - static void vlynq_device_remove(struct device *dev) 346 - { 347 - struct vlynq_driver *drv = to_vlynq_driver(dev->driver); 348 - 349 - if (drv->remove) 350 - drv->remove(to_vlynq_device(dev)); 351 - } 352 - 353 - int __vlynq_register_driver(struct vlynq_driver *driver, struct module *owner) 354 - { 355 - driver->driver.name = driver->name; 356 - driver->driver.bus = &vlynq_bus_type; 357 - return driver_register(&driver->driver); 358 - } 359 - EXPORT_SYMBOL(__vlynq_register_driver); 360 - 361 - void vlynq_unregister_driver(struct vlynq_driver *driver) 362 - { 363 - driver_unregister(&driver->driver); 364 - } 365 - EXPORT_SYMBOL(vlynq_unregister_driver); 366 - 367 - /* 368 - * A VLYNQ remote device can clock the VLYNQ bus master 369 - * using a dedicated clock line. In that case, both the 370 - * remove device and the bus master should have the same 371 - * serial clock dividers configured. Iterate through the 372 - * 8 possible dividers until we actually link with the 373 - * device. 374 - */ 375 - static int __vlynq_try_remote(struct vlynq_device *dev) 376 - { 377 - int i; 378 - 379 - vlynq_reset(dev); 380 - for (i = dev->dev_id ? vlynq_rdiv2 : vlynq_rdiv8; dev->dev_id ? 381 - i <= vlynq_rdiv8 : i >= vlynq_rdiv2; 382 - dev->dev_id ? i++ : i--) { 383 - 384 - if (!vlynq_linked(dev)) 385 - break; 386 - 387 - writel((readl(&dev->remote->control) & 388 - ~VLYNQ_CTRL_CLOCK_MASK) | 389 - VLYNQ_CTRL_CLOCK_INT | 390 - VLYNQ_CTRL_CLOCK_DIV(i - vlynq_rdiv1), 391 - &dev->remote->control); 392 - writel((readl(&dev->local->control) 393 - & ~(VLYNQ_CTRL_CLOCK_INT | 394 - VLYNQ_CTRL_CLOCK_MASK)) | 395 - VLYNQ_CTRL_CLOCK_DIV(i - vlynq_rdiv1), 396 - &dev->local->control); 397 - 398 - if (vlynq_linked(dev)) { 399 - printk(KERN_DEBUG 400 - "%s: using remote clock divisor %d\n", 401 - dev_name(&dev->dev), i - vlynq_rdiv1 + 1); 402 - dev->divisor = i; 403 - return 0; 404 - } else { 405 - vlynq_reset(dev); 406 - } 407 - } 408 - 409 - return -ENODEV; 410 - } 411 - 412 - /* 413 - * A VLYNQ remote device can be clocked by the VLYNQ bus 414 - * master using a dedicated clock line. In that case, only 415 - * the bus master configures the serial clock divider. 416 - * Iterate through the 8 possible dividers until we 417 - * actually get a link with the device. 418 - */ 419 - static int __vlynq_try_local(struct vlynq_device *dev) 420 - { 421 - int i; 422 - 423 - vlynq_reset(dev); 424 - 425 - for (i = dev->dev_id ? vlynq_ldiv2 : vlynq_ldiv8; dev->dev_id ? 426 - i <= vlynq_ldiv8 : i >= vlynq_ldiv2; 427 - dev->dev_id ? i++ : i--) { 428 - 429 - writel((readl(&dev->local->control) & 430 - ~VLYNQ_CTRL_CLOCK_MASK) | 431 - VLYNQ_CTRL_CLOCK_INT | 432 - VLYNQ_CTRL_CLOCK_DIV(i - vlynq_ldiv1), 433 - &dev->local->control); 434 - 435 - if (vlynq_linked(dev)) { 436 - printk(KERN_DEBUG 437 - "%s: using local clock divisor %d\n", 438 - dev_name(&dev->dev), i - vlynq_ldiv1 + 1); 439 - dev->divisor = i; 440 - return 0; 441 - } else { 442 - vlynq_reset(dev); 443 - } 444 - } 445 - 446 - return -ENODEV; 447 - } 448 - 449 - /* 450 - * When using external clocking method, serial clock 451 - * is supplied by an external oscillator, therefore we 452 - * should mask the local clock bit in the clock control 453 - * register for both the bus master and the remote device. 454 - */ 455 - static int __vlynq_try_external(struct vlynq_device *dev) 456 - { 457 - vlynq_reset(dev); 458 - if (!vlynq_linked(dev)) 459 - return -ENODEV; 460 - 461 - writel((readl(&dev->remote->control) & 462 - ~VLYNQ_CTRL_CLOCK_INT), 463 - &dev->remote->control); 464 - 465 - writel((readl(&dev->local->control) & 466 - ~VLYNQ_CTRL_CLOCK_INT), 467 - &dev->local->control); 468 - 469 - if (vlynq_linked(dev)) { 470 - printk(KERN_DEBUG "%s: using external clock\n", 471 - dev_name(&dev->dev)); 472 - dev->divisor = vlynq_div_external; 473 - return 0; 474 - } 475 - 476 - return -ENODEV; 477 - } 478 - 479 - static int __vlynq_enable_device(struct vlynq_device *dev) 480 - { 481 - int result; 482 - struct plat_vlynq_ops *ops = dev->dev.platform_data; 483 - 484 - result = ops->on(dev); 485 - if (result) 486 - return result; 487 - 488 - switch (dev->divisor) { 489 - case vlynq_div_external: 490 - case vlynq_div_auto: 491 - /* When the device is brought from reset it should have clock 492 - * generation negotiated by hardware. 493 - * Check which device is generating clocks and perform setup 494 - * accordingly */ 495 - if (vlynq_linked(dev) && readl(&dev->remote->control) & 496 - VLYNQ_CTRL_CLOCK_INT) { 497 - if (!__vlynq_try_remote(dev) || 498 - !__vlynq_try_local(dev) || 499 - !__vlynq_try_external(dev)) 500 - return 0; 501 - } else { 502 - if (!__vlynq_try_external(dev) || 503 - !__vlynq_try_local(dev) || 504 - !__vlynq_try_remote(dev)) 505 - return 0; 506 - } 507 - break; 508 - case vlynq_ldiv1: 509 - case vlynq_ldiv2: 510 - case vlynq_ldiv3: 511 - case vlynq_ldiv4: 512 - case vlynq_ldiv5: 513 - case vlynq_ldiv6: 514 - case vlynq_ldiv7: 515 - case vlynq_ldiv8: 516 - writel(VLYNQ_CTRL_CLOCK_INT | 517 - VLYNQ_CTRL_CLOCK_DIV(dev->divisor - 518 - vlynq_ldiv1), &dev->local->control); 519 - writel(0, &dev->remote->control); 520 - if (vlynq_linked(dev)) { 521 - printk(KERN_DEBUG 522 - "%s: using local clock divisor %d\n", 523 - dev_name(&dev->dev), 524 - dev->divisor - vlynq_ldiv1 + 1); 525 - return 0; 526 - } 527 - break; 528 - case vlynq_rdiv1: 529 - case vlynq_rdiv2: 530 - case vlynq_rdiv3: 531 - case vlynq_rdiv4: 532 - case vlynq_rdiv5: 533 - case vlynq_rdiv6: 534 - case vlynq_rdiv7: 535 - case vlynq_rdiv8: 536 - writel(0, &dev->local->control); 537 - writel(VLYNQ_CTRL_CLOCK_INT | 538 - VLYNQ_CTRL_CLOCK_DIV(dev->divisor - 539 - vlynq_rdiv1), &dev->remote->control); 540 - if (vlynq_linked(dev)) { 541 - printk(KERN_DEBUG 542 - "%s: using remote clock divisor %d\n", 543 - dev_name(&dev->dev), 544 - dev->divisor - vlynq_rdiv1 + 1); 545 - return 0; 546 - } 547 - break; 548 - } 549 - 550 - ops->off(dev); 551 - return -ENODEV; 552 - } 553 - 554 - int vlynq_enable_device(struct vlynq_device *dev) 555 - { 556 - struct plat_vlynq_ops *ops = dev->dev.platform_data; 557 - int result = -ENODEV; 558 - 559 - result = __vlynq_enable_device(dev); 560 - if (result) 561 - return result; 562 - 563 - result = vlynq_setup_irq(dev); 564 - if (result) 565 - ops->off(dev); 566 - 567 - dev->enabled = !result; 568 - return result; 569 - } 570 - EXPORT_SYMBOL(vlynq_enable_device); 571 - 572 - 573 - void vlynq_disable_device(struct vlynq_device *dev) 574 - { 575 - struct plat_vlynq_ops *ops = dev->dev.platform_data; 576 - 577 - dev->enabled = 0; 578 - free_irq(dev->irq, dev); 579 - ops->off(dev); 580 - } 581 - EXPORT_SYMBOL(vlynq_disable_device); 582 - 583 - int vlynq_set_local_mapping(struct vlynq_device *dev, u32 tx_offset, 584 - struct vlynq_mapping *mapping) 585 - { 586 - int i; 587 - 588 - if (!dev->enabled) 589 - return -ENXIO; 590 - 591 - writel(tx_offset, &dev->local->tx_offset); 592 - for (i = 0; i < 4; i++) { 593 - writel(mapping[i].offset, &dev->local->rx_mapping[i].offset); 594 - writel(mapping[i].size, &dev->local->rx_mapping[i].size); 595 - } 596 - return 0; 597 - } 598 - EXPORT_SYMBOL(vlynq_set_local_mapping); 599 - 600 - int vlynq_set_remote_mapping(struct vlynq_device *dev, u32 tx_offset, 601 - struct vlynq_mapping *mapping) 602 - { 603 - int i; 604 - 605 - if (!dev->enabled) 606 - return -ENXIO; 607 - 608 - writel(tx_offset, &dev->remote->tx_offset); 609 - for (i = 0; i < 4; i++) { 610 - writel(mapping[i].offset, &dev->remote->rx_mapping[i].offset); 611 - writel(mapping[i].size, &dev->remote->rx_mapping[i].size); 612 - } 613 - return 0; 614 - } 615 - EXPORT_SYMBOL(vlynq_set_remote_mapping); 616 - 617 - int vlynq_set_local_irq(struct vlynq_device *dev, int virq) 618 - { 619 - int irq = dev->irq_start + virq; 620 - if (dev->enabled) 621 - return -EBUSY; 622 - 623 - if ((irq < dev->irq_start) || (irq > dev->irq_end)) 624 - return -EINVAL; 625 - 626 - if (virq == dev->remote_irq) 627 - return -EINVAL; 628 - 629 - dev->local_irq = virq; 630 - 631 - return 0; 632 - } 633 - EXPORT_SYMBOL(vlynq_set_local_irq); 634 - 635 - int vlynq_set_remote_irq(struct vlynq_device *dev, int virq) 636 - { 637 - int irq = dev->irq_start + virq; 638 - if (dev->enabled) 639 - return -EBUSY; 640 - 641 - if ((irq < dev->irq_start) || (irq > dev->irq_end)) 642 - return -EINVAL; 643 - 644 - if (virq == dev->local_irq) 645 - return -EINVAL; 646 - 647 - dev->remote_irq = virq; 648 - 649 - return 0; 650 - } 651 - EXPORT_SYMBOL(vlynq_set_remote_irq); 652 - 653 - static int vlynq_probe(struct platform_device *pdev) 654 - { 655 - struct vlynq_device *dev; 656 - struct resource *regs_res, *mem_res, *irq_res; 657 - int len, result; 658 - 659 - regs_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs"); 660 - if (!regs_res) 661 - return -ENODEV; 662 - 663 - mem_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mem"); 664 - if (!mem_res) 665 - return -ENODEV; 666 - 667 - irq_res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "devirq"); 668 - if (!irq_res) 669 - return -ENODEV; 670 - 671 - dev = kzalloc(sizeof(*dev), GFP_KERNEL); 672 - if (!dev) { 673 - printk(KERN_ERR 674 - "vlynq: failed to allocate device structure\n"); 675 - return -ENOMEM; 676 - } 677 - 678 - dev->id = pdev->id; 679 - dev->dev.bus = &vlynq_bus_type; 680 - dev->dev.parent = &pdev->dev; 681 - dev_set_name(&dev->dev, "vlynq%d", dev->id); 682 - dev->dev.platform_data = pdev->dev.platform_data; 683 - dev->dev.release = vlynq_device_release; 684 - 685 - dev->regs_start = regs_res->start; 686 - dev->regs_end = regs_res->end; 687 - dev->mem_start = mem_res->start; 688 - dev->mem_end = mem_res->end; 689 - 690 - len = resource_size(regs_res); 691 - if (!request_mem_region(regs_res->start, len, dev_name(&dev->dev))) { 692 - printk(KERN_ERR "%s: Can't request vlynq registers\n", 693 - dev_name(&dev->dev)); 694 - result = -ENXIO; 695 - goto fail_request; 696 - } 697 - 698 - dev->local = ioremap(regs_res->start, len); 699 - if (!dev->local) { 700 - printk(KERN_ERR "%s: Can't remap vlynq registers\n", 701 - dev_name(&dev->dev)); 702 - result = -ENXIO; 703 - goto fail_remap; 704 - } 705 - 706 - dev->remote = (struct vlynq_regs *)((void *)dev->local + 707 - VLYNQ_REMOTE_OFFSET); 708 - 709 - dev->irq = platform_get_irq_byname(pdev, "irq"); 710 - dev->irq_start = irq_res->start; 711 - dev->irq_end = irq_res->end; 712 - dev->local_irq = dev->irq_end - dev->irq_start; 713 - dev->remote_irq = dev->local_irq - 1; 714 - 715 - if (device_register(&dev->dev)) 716 - goto fail_register; 717 - platform_set_drvdata(pdev, dev); 718 - 719 - printk(KERN_INFO "%s: regs 0x%p, irq %d, mem 0x%p\n", 720 - dev_name(&dev->dev), (void *)dev->regs_start, dev->irq, 721 - (void *)dev->mem_start); 722 - 723 - dev->dev_id = 0; 724 - dev->divisor = vlynq_div_auto; 725 - result = __vlynq_enable_device(dev); 726 - if (result == 0) { 727 - dev->dev_id = readl(&dev->remote->chip); 728 - ((struct plat_vlynq_ops *)(dev->dev.platform_data))->off(dev); 729 - } 730 - if (dev->dev_id) 731 - printk(KERN_INFO "Found a VLYNQ device: %08x\n", dev->dev_id); 732 - 733 - return 0; 734 - 735 - fail_register: 736 - iounmap(dev->local); 737 - fail_remap: 738 - fail_request: 739 - release_mem_region(regs_res->start, len); 740 - kfree(dev); 741 - return result; 742 - } 743 - 744 - static int vlynq_remove(struct platform_device *pdev) 745 - { 746 - struct vlynq_device *dev = platform_get_drvdata(pdev); 747 - 748 - device_unregister(&dev->dev); 749 - iounmap(dev->local); 750 - release_mem_region(dev->regs_start, 751 - dev->regs_end - dev->regs_start + 1); 752 - 753 - kfree(dev); 754 - 755 - return 0; 756 - } 757 - 758 - static struct platform_driver vlynq_platform_driver = { 759 - .driver.name = "vlynq", 760 - .probe = vlynq_probe, 761 - .remove = vlynq_remove, 762 - }; 763 - 764 - struct bus_type vlynq_bus_type = { 765 - .name = "vlynq", 766 - .match = vlynq_device_match, 767 - .probe = vlynq_device_probe, 768 - .remove = vlynq_device_remove, 769 - }; 770 - EXPORT_SYMBOL(vlynq_bus_type); 771 - 772 - static int vlynq_init(void) 773 - { 774 - int res = 0; 775 - 776 - res = bus_register(&vlynq_bus_type); 777 - if (res) 778 - goto fail_bus; 779 - 780 - res = platform_driver_register(&vlynq_platform_driver); 781 - if (res) 782 - goto fail_platform; 783 - 784 - return 0; 785 - 786 - fail_platform: 787 - bus_unregister(&vlynq_bus_type); 788 - fail_bus: 789 - return res; 790 - } 791 - 792 - static void vlynq_exit(void) 793 - { 794 - platform_driver_unregister(&vlynq_platform_driver); 795 - bus_unregister(&vlynq_bus_type); 796 - } 797 - 798 - module_init(vlynq_init); 799 - module_exit(vlynq_exit);
-6
drivers/watchdog/Kconfig
··· 1768 1768 To compile this driver as a loadable module, choose M here. 1769 1769 The module will be called sb_wdog. 1770 1770 1771 - config AR7_WDT 1772 - tristate "TI AR7 Watchdog Timer" 1773 - depends on AR7 || (MIPS && 32BIT && COMPILE_TEST) 1774 - help 1775 - Hardware driver for the TI AR7 Watchdog Timer. 1776 - 1777 1771 config TXX9_WDT 1778 1772 tristate "Toshiba TXx9 Watchdog Timer" 1779 1773 depends on CPU_TX49XX || (MIPS && COMPILE_TEST)
-1
drivers/watchdog/Makefile
··· 168 168 obj-$(CONFIG_JZ4740_WDT) += jz4740_wdt.o 169 169 obj-$(CONFIG_WDT_MTX1) += mtx-1_wdt.o 170 170 obj-$(CONFIG_SIBYTE_WDOG) += sb_wdog.o 171 - obj-$(CONFIG_AR7_WDT) += ar7_wdt.o 172 171 obj-$(CONFIG_TXX9_WDT) += txx9wdt.o 173 172 obj-$(CONFIG_OCTEON_WDT) += octeon-wdt.o 174 173 octeon-wdt-y := octeon-wdt-main.o octeon-wdt-nmi.o
-315
drivers/watchdog/ar7_wdt.c
··· 1 - // SPDX-License-Identifier: GPL-2.0+ 2 - /* 3 - * drivers/watchdog/ar7_wdt.c 4 - * 5 - * Copyright (C) 2007 Nicolas Thill <nico@openwrt.org> 6 - * Copyright (c) 2005 Enrik Berkhan <Enrik.Berkhan@akk.org> 7 - * 8 - * Some code taken from: 9 - * National Semiconductor SCx200 Watchdog support 10 - * Copyright (c) 2001,2002 Christer Weinigel <wingel@nano-system.com> 11 - * 12 - */ 13 - 14 - #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 15 - 16 - #include <linux/module.h> 17 - #include <linux/moduleparam.h> 18 - #include <linux/errno.h> 19 - #include <linux/miscdevice.h> 20 - #include <linux/platform_device.h> 21 - #include <linux/watchdog.h> 22 - #include <linux/fs.h> 23 - #include <linux/ioport.h> 24 - #include <linux/io.h> 25 - #include <linux/uaccess.h> 26 - #include <linux/clk.h> 27 - 28 - #include <asm/addrspace.h> 29 - #include <asm/mach-ar7/ar7.h> 30 - 31 - #define LONGNAME "TI AR7 Watchdog Timer" 32 - 33 - MODULE_AUTHOR("Nicolas Thill <nico@openwrt.org>"); 34 - MODULE_DESCRIPTION(LONGNAME); 35 - MODULE_LICENSE("GPL"); 36 - 37 - static int margin = 60; 38 - module_param(margin, int, 0); 39 - MODULE_PARM_DESC(margin, "Watchdog margin in seconds"); 40 - 41 - static bool nowayout = WATCHDOG_NOWAYOUT; 42 - module_param(nowayout, bool, 0); 43 - MODULE_PARM_DESC(nowayout, "Disable watchdog shutdown on close"); 44 - 45 - #define READ_REG(x) readl((void __iomem *)&(x)) 46 - #define WRITE_REG(x, v) writel((v), (void __iomem *)&(x)) 47 - 48 - struct ar7_wdt { 49 - u32 kick_lock; 50 - u32 kick; 51 - u32 change_lock; 52 - u32 change; 53 - u32 disable_lock; 54 - u32 disable; 55 - u32 prescale_lock; 56 - u32 prescale; 57 - }; 58 - 59 - static unsigned long wdt_is_open; 60 - static unsigned expect_close; 61 - static DEFINE_SPINLOCK(wdt_lock); 62 - 63 - /* XXX currently fixed, allows max margin ~68.72 secs */ 64 - #define prescale_value 0xffff 65 - 66 - /* Pointer to the remapped WDT IO space */ 67 - static struct ar7_wdt *ar7_wdt; 68 - 69 - static struct clk *vbus_clk; 70 - 71 - static void ar7_wdt_kick(u32 value) 72 - { 73 - WRITE_REG(ar7_wdt->kick_lock, 0x5555); 74 - if ((READ_REG(ar7_wdt->kick_lock) & 3) == 1) { 75 - WRITE_REG(ar7_wdt->kick_lock, 0xaaaa); 76 - if ((READ_REG(ar7_wdt->kick_lock) & 3) == 3) { 77 - WRITE_REG(ar7_wdt->kick, value); 78 - return; 79 - } 80 - } 81 - pr_err("failed to unlock WDT kick reg\n"); 82 - } 83 - 84 - static void ar7_wdt_prescale(u32 value) 85 - { 86 - WRITE_REG(ar7_wdt->prescale_lock, 0x5a5a); 87 - if ((READ_REG(ar7_wdt->prescale_lock) & 3) == 1) { 88 - WRITE_REG(ar7_wdt->prescale_lock, 0xa5a5); 89 - if ((READ_REG(ar7_wdt->prescale_lock) & 3) == 3) { 90 - WRITE_REG(ar7_wdt->prescale, value); 91 - return; 92 - } 93 - } 94 - pr_err("failed to unlock WDT prescale reg\n"); 95 - } 96 - 97 - static void ar7_wdt_change(u32 value) 98 - { 99 - WRITE_REG(ar7_wdt->change_lock, 0x6666); 100 - if ((READ_REG(ar7_wdt->change_lock) & 3) == 1) { 101 - WRITE_REG(ar7_wdt->change_lock, 0xbbbb); 102 - if ((READ_REG(ar7_wdt->change_lock) & 3) == 3) { 103 - WRITE_REG(ar7_wdt->change, value); 104 - return; 105 - } 106 - } 107 - pr_err("failed to unlock WDT change reg\n"); 108 - } 109 - 110 - static void ar7_wdt_disable(u32 value) 111 - { 112 - WRITE_REG(ar7_wdt->disable_lock, 0x7777); 113 - if ((READ_REG(ar7_wdt->disable_lock) & 3) == 1) { 114 - WRITE_REG(ar7_wdt->disable_lock, 0xcccc); 115 - if ((READ_REG(ar7_wdt->disable_lock) & 3) == 2) { 116 - WRITE_REG(ar7_wdt->disable_lock, 0xdddd); 117 - if ((READ_REG(ar7_wdt->disable_lock) & 3) == 3) { 118 - WRITE_REG(ar7_wdt->disable, value); 119 - return; 120 - } 121 - } 122 - } 123 - pr_err("failed to unlock WDT disable reg\n"); 124 - } 125 - 126 - static void ar7_wdt_update_margin(int new_margin) 127 - { 128 - u32 change; 129 - u32 vbus_rate; 130 - 131 - vbus_rate = clk_get_rate(vbus_clk); 132 - change = new_margin * (vbus_rate / prescale_value); 133 - if (change < 1) 134 - change = 1; 135 - if (change > 0xffff) 136 - change = 0xffff; 137 - ar7_wdt_change(change); 138 - margin = change * prescale_value / vbus_rate; 139 - pr_info("timer margin %d seconds (prescale %d, change %d, freq %d)\n", 140 - margin, prescale_value, change, vbus_rate); 141 - } 142 - 143 - static void ar7_wdt_enable_wdt(void) 144 - { 145 - pr_debug("enabling watchdog timer\n"); 146 - ar7_wdt_disable(1); 147 - ar7_wdt_kick(1); 148 - } 149 - 150 - static void ar7_wdt_disable_wdt(void) 151 - { 152 - pr_debug("disabling watchdog timer\n"); 153 - ar7_wdt_disable(0); 154 - } 155 - 156 - static int ar7_wdt_open(struct inode *inode, struct file *file) 157 - { 158 - /* only allow one at a time */ 159 - if (test_and_set_bit(0, &wdt_is_open)) 160 - return -EBUSY; 161 - ar7_wdt_enable_wdt(); 162 - expect_close = 0; 163 - 164 - return stream_open(inode, file); 165 - } 166 - 167 - static int ar7_wdt_release(struct inode *inode, struct file *file) 168 - { 169 - if (!expect_close) 170 - pr_warn("watchdog device closed unexpectedly, will not disable the watchdog timer\n"); 171 - else if (!nowayout) 172 - ar7_wdt_disable_wdt(); 173 - clear_bit(0, &wdt_is_open); 174 - return 0; 175 - } 176 - 177 - static ssize_t ar7_wdt_write(struct file *file, const char *data, 178 - size_t len, loff_t *ppos) 179 - { 180 - /* check for a magic close character */ 181 - if (len) { 182 - size_t i; 183 - 184 - spin_lock(&wdt_lock); 185 - ar7_wdt_kick(1); 186 - spin_unlock(&wdt_lock); 187 - 188 - expect_close = 0; 189 - for (i = 0; i < len; ++i) { 190 - char c; 191 - if (get_user(c, data + i)) 192 - return -EFAULT; 193 - if (c == 'V') 194 - expect_close = 1; 195 - } 196 - 197 - } 198 - return len; 199 - } 200 - 201 - static long ar7_wdt_ioctl(struct file *file, 202 - unsigned int cmd, unsigned long arg) 203 - { 204 - static const struct watchdog_info ident = { 205 - .identity = LONGNAME, 206 - .firmware_version = 1, 207 - .options = (WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | 208 - WDIOF_MAGICCLOSE), 209 - }; 210 - int new_margin; 211 - 212 - switch (cmd) { 213 - case WDIOC_GETSUPPORT: 214 - if (copy_to_user((struct watchdog_info *)arg, &ident, 215 - sizeof(ident))) 216 - return -EFAULT; 217 - return 0; 218 - case WDIOC_GETSTATUS: 219 - case WDIOC_GETBOOTSTATUS: 220 - if (put_user(0, (int *)arg)) 221 - return -EFAULT; 222 - return 0; 223 - case WDIOC_KEEPALIVE: 224 - ar7_wdt_kick(1); 225 - return 0; 226 - case WDIOC_SETTIMEOUT: 227 - if (get_user(new_margin, (int *)arg)) 228 - return -EFAULT; 229 - if (new_margin < 1) 230 - return -EINVAL; 231 - 232 - spin_lock(&wdt_lock); 233 - ar7_wdt_update_margin(new_margin); 234 - ar7_wdt_kick(1); 235 - spin_unlock(&wdt_lock); 236 - fallthrough; 237 - case WDIOC_GETTIMEOUT: 238 - if (put_user(margin, (int *)arg)) 239 - return -EFAULT; 240 - return 0; 241 - default: 242 - return -ENOTTY; 243 - } 244 - } 245 - 246 - static const struct file_operations ar7_wdt_fops = { 247 - .owner = THIS_MODULE, 248 - .write = ar7_wdt_write, 249 - .unlocked_ioctl = ar7_wdt_ioctl, 250 - .compat_ioctl = compat_ptr_ioctl, 251 - .open = ar7_wdt_open, 252 - .release = ar7_wdt_release, 253 - .llseek = no_llseek, 254 - }; 255 - 256 - static struct miscdevice ar7_wdt_miscdev = { 257 - .minor = WATCHDOG_MINOR, 258 - .name = "watchdog", 259 - .fops = &ar7_wdt_fops, 260 - }; 261 - 262 - static int ar7_wdt_probe(struct platform_device *pdev) 263 - { 264 - int rc; 265 - 266 - ar7_wdt = devm_platform_ioremap_resource_byname(pdev, "regs"); 267 - if (IS_ERR(ar7_wdt)) 268 - return PTR_ERR(ar7_wdt); 269 - 270 - vbus_clk = clk_get(NULL, "vbus"); 271 - if (IS_ERR(vbus_clk)) { 272 - pr_err("could not get vbus clock\n"); 273 - return PTR_ERR(vbus_clk); 274 - } 275 - 276 - ar7_wdt_disable_wdt(); 277 - ar7_wdt_prescale(prescale_value); 278 - ar7_wdt_update_margin(margin); 279 - 280 - rc = misc_register(&ar7_wdt_miscdev); 281 - if (rc) { 282 - pr_err("unable to register misc device\n"); 283 - goto out; 284 - } 285 - return 0; 286 - 287 - out: 288 - clk_put(vbus_clk); 289 - vbus_clk = NULL; 290 - return rc; 291 - } 292 - 293 - static void ar7_wdt_remove(struct platform_device *pdev) 294 - { 295 - misc_deregister(&ar7_wdt_miscdev); 296 - clk_put(vbus_clk); 297 - vbus_clk = NULL; 298 - } 299 - 300 - static void ar7_wdt_shutdown(struct platform_device *pdev) 301 - { 302 - if (!nowayout) 303 - ar7_wdt_disable_wdt(); 304 - } 305 - 306 - static struct platform_driver ar7_wdt_driver = { 307 - .probe = ar7_wdt_probe, 308 - .remove_new = ar7_wdt_remove, 309 - .shutdown = ar7_wdt_shutdown, 310 - .driver = { 311 - .name = "ar7_wdt", 312 - }, 313 - }; 314 - 315 - module_platform_driver(ar7_wdt_driver);
-149
include/linux/vlynq.h
··· 1 - /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 - /* 3 - * Copyright (C) 2006, 2007 Eugene Konev <ejka@openwrt.org> 4 - */ 5 - 6 - #ifndef __VLYNQ_H__ 7 - #define __VLYNQ_H__ 8 - 9 - #include <linux/device.h> 10 - #include <linux/types.h> 11 - 12 - struct module; 13 - 14 - #define VLYNQ_NUM_IRQS 32 15 - 16 - struct vlynq_mapping { 17 - u32 size; 18 - u32 offset; 19 - }; 20 - 21 - enum vlynq_divisor { 22 - vlynq_div_auto = 0, 23 - vlynq_ldiv1, 24 - vlynq_ldiv2, 25 - vlynq_ldiv3, 26 - vlynq_ldiv4, 27 - vlynq_ldiv5, 28 - vlynq_ldiv6, 29 - vlynq_ldiv7, 30 - vlynq_ldiv8, 31 - vlynq_rdiv1, 32 - vlynq_rdiv2, 33 - vlynq_rdiv3, 34 - vlynq_rdiv4, 35 - vlynq_rdiv5, 36 - vlynq_rdiv6, 37 - vlynq_rdiv7, 38 - vlynq_rdiv8, 39 - vlynq_div_external 40 - }; 41 - 42 - struct vlynq_device_id { 43 - u32 id; 44 - enum vlynq_divisor divisor; 45 - unsigned long driver_data; 46 - }; 47 - 48 - struct vlynq_regs; 49 - struct vlynq_device { 50 - u32 id, dev_id; 51 - int local_irq; 52 - int remote_irq; 53 - enum vlynq_divisor divisor; 54 - u32 regs_start, regs_end; 55 - u32 mem_start, mem_end; 56 - u32 irq_start, irq_end; 57 - int irq; 58 - int enabled; 59 - struct vlynq_regs *local; 60 - struct vlynq_regs *remote; 61 - struct device dev; 62 - }; 63 - 64 - struct vlynq_driver { 65 - char *name; 66 - struct vlynq_device_id *id_table; 67 - int (*probe)(struct vlynq_device *dev, struct vlynq_device_id *id); 68 - void (*remove)(struct vlynq_device *dev); 69 - struct device_driver driver; 70 - }; 71 - 72 - struct plat_vlynq_ops { 73 - int (*on)(struct vlynq_device *dev); 74 - void (*off)(struct vlynq_device *dev); 75 - }; 76 - 77 - static inline struct vlynq_driver *to_vlynq_driver(struct device_driver *drv) 78 - { 79 - return container_of(drv, struct vlynq_driver, driver); 80 - } 81 - 82 - static inline struct vlynq_device *to_vlynq_device(struct device *device) 83 - { 84 - return container_of(device, struct vlynq_device, dev); 85 - } 86 - 87 - extern struct bus_type vlynq_bus_type; 88 - 89 - extern int __vlynq_register_driver(struct vlynq_driver *driver, 90 - struct module *owner); 91 - 92 - static inline int vlynq_register_driver(struct vlynq_driver *driver) 93 - { 94 - return __vlynq_register_driver(driver, THIS_MODULE); 95 - } 96 - 97 - static inline void *vlynq_get_drvdata(struct vlynq_device *dev) 98 - { 99 - return dev_get_drvdata(&dev->dev); 100 - } 101 - 102 - static inline void vlynq_set_drvdata(struct vlynq_device *dev, void *data) 103 - { 104 - dev_set_drvdata(&dev->dev, data); 105 - } 106 - 107 - static inline u32 vlynq_mem_start(struct vlynq_device *dev) 108 - { 109 - return dev->mem_start; 110 - } 111 - 112 - static inline u32 vlynq_mem_end(struct vlynq_device *dev) 113 - { 114 - return dev->mem_end; 115 - } 116 - 117 - static inline u32 vlynq_mem_len(struct vlynq_device *dev) 118 - { 119 - return dev->mem_end - dev->mem_start + 1; 120 - } 121 - 122 - static inline int vlynq_virq_to_irq(struct vlynq_device *dev, int virq) 123 - { 124 - int irq = dev->irq_start + virq; 125 - if ((irq < dev->irq_start) || (irq > dev->irq_end)) 126 - return -EINVAL; 127 - 128 - return irq; 129 - } 130 - 131 - static inline int vlynq_irq_to_virq(struct vlynq_device *dev, int irq) 132 - { 133 - if ((irq < dev->irq_start) || (irq > dev->irq_end)) 134 - return -EINVAL; 135 - 136 - return irq - dev->irq_start; 137 - } 138 - 139 - extern void vlynq_unregister_driver(struct vlynq_driver *driver); 140 - extern int vlynq_enable_device(struct vlynq_device *dev); 141 - extern void vlynq_disable_device(struct vlynq_device *dev); 142 - extern int vlynq_set_local_mapping(struct vlynq_device *dev, u32 tx_offset, 143 - struct vlynq_mapping *mapping); 144 - extern int vlynq_set_remote_mapping(struct vlynq_device *dev, u32 tx_offset, 145 - struct vlynq_mapping *mapping); 146 - extern int vlynq_set_local_irq(struct vlynq_device *dev, int virq); 147 - extern int vlynq_set_remote_irq(struct vlynq_device *dev, int virq); 148 - 149 - #endif /* __VLYNQ_H__ */