tg3: Add memory barriers to sync BD data

for weak memory model architectures to ensure that the chip will DMA
valid BD data.

Signed-off-by: Michael Chan <[e-mail]>
Reviewed-by: Benjamin Li <[e-mail]>
Reviewed-by: Matt Carlson <[e-mail]>
Signed-off-by: David S. Miller <[e-mail]>

drivers/net/ethernet/broadcom/tg3.c

···
 
 	/* Refill RX ring(s). */
 	if (!tg3_flag(tp, ENABLE_RSS)) {
+		/* Sync BD data before updating mailbox */
+		wmb();
+
 		if (work_mask & RXD_OPAQUE_RING_STD) {
 			tpr->rx_std_prod_idx = std_prod_idx &
 					       tp->rx_std_ring_mask;
···
 
 	skb_tx_timestamp(skb);
 	netdev_sent_queue(tp->dev, skb->len);
+
+	/* Sync BD data before updating mailbox */
+	wmb();
 
 	/* Packets are ready, update Tx producer idx local and on card. */
 	tw32_tx_mbox(tnapi->prodmbox, entry);
···
 	}
 
 	tnapi->tx_prod++;
+
+	/* Sync BD data before updating mailbox */
+	wmb();
 
 	tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
 	tr32_mailbox(tnapi->prodmbox);