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linux
ARM: dts: Add Goramo MultiLink device tree
This adds a device tree for the Goramo MultiLink IXP425-based
WAN router.
Cc: Krzysztof Hałasa <khalasa@piap.pl>
Cc: openwrt-devel@lists.openwrt.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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arch/arm/boot/dts/Makefile
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arch/arm/boot/dts/Makefile
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arch/arm/boot/dts/intel-ixp42x-goramo-multilink.dts
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arch/arm/boot/dts/intel-ixp42x-goramo-multilink.dts
···
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// SPDX-License-Identifier: ISC
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/*
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* Device Tree file for the Goramo MultiLink Router
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* There are two variants:
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* - MultiLink Basic (a box)
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* - MultiLink Max (19" rack mount)
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* This device tree supports MultiLink Basic.
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* This machine is based on IXP425.
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* This is one of the few devices supporting the IXP4xx High-Speed Serial
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* (HSS) link for a V.35 WAN interface.
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* The hardware originates in Poland.
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*/
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/dts-v1/;
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#include "intel-ixp42x.dtsi"
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#include <dt-bindings/input/input.h>
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/ {
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model = "Goramo MultiLink Router";
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compatible = "goramo,multilink-router", "intel,ixp42x";
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#address-cells = <1>;
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#size-cells = <1>;
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+
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memory@0 {
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/*
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* 64 MB of RAM according to the manual. The MultiLink
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* Max has 128 MB.
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*/
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device_type = "memory";
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reg = <0x00000000 0x4000000>;
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};
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chosen {
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bootargs = "console=ttyS0,115200n8";
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stdout-path = "uart0:115200n8";
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};
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aliases {
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serial0 = &uart0;
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serial1 = &uart1;
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};
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/*
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* 74HC4094 which is used as a rudimentary GPIO expander
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* FIXME:
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* - Create device tree bindings for this as GPIO expander
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* - Write a pure DT GPIO driver using these bindings
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* - Support cascading in the style of gpio-74x164.c (cannot be reused, very different)
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*/
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gpio_74: gpio-74hc4094 {
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compatible = "nxp,74hc4094";
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cp-gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
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d-gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>;
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str-gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>;
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/* oe-gpios is optional */
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gpio-controller;
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#gpio-cells = <2>;
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/* We are not cascaded */
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registers-number = <1>;
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gpio-line-names = "CONTROL_HSS0_CLK_INT", "CONTROL_HSS1_CLK_INT", "CONTROL_HSS0_DTR_N",
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"CONTROL_HSS1_DTR_N", "CONTROL_EXT", "CONTROL_AUTO_RESET",
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"CONTROL_PCI_RESET_N", "CONTROL_EEPROM_WC_N";
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};
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soc {
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bus@c4000000 {
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flash@0,0 {
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compatible = "intel,ixp4xx-flash", "cfi-flash";
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bank-width = <2>;
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/* Enable writes on the expansion bus */
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intel,ixp4xx-eb-write-enable = <1>;
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/* 16 MB of Flash mapped in at CS0 */
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reg = <0 0x00000000 0x1000000>;
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+
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partitions {
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compatible = "redboot-fis";
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/* Eraseblock at 0x0fe0000 */
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fis-index-block = <0x7f>;
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};
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};
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};
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pci@c0000000 {
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status = "ok";
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/*
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* The device has 4 slots (IDSEL) with one dedicated IRQ per slot.
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* The slots have Ethernet, Ethernet, NEC and MPCI.
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* The IDSELs are 11, 12, 13, 14.
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*/
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interrupt-map =
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/* IDSEL 11 - Ethernet A */
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<0x5800 0 0 1 &gpio0 4 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 11 is irq 4 */
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<0x5800 0 0 2 &gpio0 4 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 11 is irq 4 */
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<0x5800 0 0 3 &gpio0 4 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 11 is irq 4 */
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<0x5800 0 0 4 &gpio0 4 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 11 is irq 4 */
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/* IDSEL 12 - Ethernet B */
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<0x6000 0 0 1 &gpio0 5 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 12 is irq 5 */
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<0x6000 0 0 2 &gpio0 5 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 12 is irq 5 */
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<0x6000 0 0 3 &gpio0 5 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 12 is irq 5 */
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<0x6000 0 0 4 &gpio0 5 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 12 is irq 5 */
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/* IDSEL 13 - MPCI */
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<0x6800 0 0 1 &gpio0 12 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 13 is irq 12 */
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<0x6800 0 0 2 &gpio0 12 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 13 is irq 12 */
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<0x6800 0 0 3 &gpio0 12 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 13 is irq 12 */
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<0x6800 0 0 4 &gpio0 12 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 13 is irq 12 */
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/* IDSEL 14 - NEC */
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<0x7000 0 0 1 &gpio0 3 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 14 is irq 3 */
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<0x7000 0 0 2 &gpio0 3 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 14 is irq 3 */
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<0x7000 0 0 3 &gpio0 3 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 14 is irq 3 */
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<0x7000 0 0 4 &gpio0 3 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 14 is irq 3 */
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};
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/* HSS links */
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npe@c8006000 {
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hss@0 {
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status = "okay";
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intel,queue-chl-rxtrig = <&qmgr 12>;
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intel,queue-chl-txready = <&qmgr 34>;
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intel,queue-pkt-rx = <&qmgr 13>;
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intel,queue-pkt-tx = <&qmgr 14>, <&qmgr 15>, <&qmgr 16>, <&qmgr 17>;
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intel,queue-pkt-rxfree = <&qmgr 18>, <&qmgr 19>, <&qmgr 20>, <&qmgr 21>;
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intel,queue-pkt-txdone = <&qmgr 22>;
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/* The Goramo GPIO-based clock etc control */
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cts-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
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rts-gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
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dcd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
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dtr-gpios = <&gpio_74 2 GPIO_ACTIVE_LOW>;
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clk-internal-gpios = <&gpio_74 0 GPIO_ACTIVE_HIGH>;
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};
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hss@1 {
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status = "okay";
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intel,queue-chl-rxtrig = <&qmgr 10>;
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intel,queue-chl-txready = <&qmgr 35>;
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intel,queue-pkt-rx = <&qmgr 0>;
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intel,queue-pkt-tx = <&qmgr 5>, <&qmgr 6>, <&qmgr 7>, <&qmgr 8>;
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intel,queue-pkt-rxfree = <&qmgr 1>, <&qmgr 2>, <&qmgr 3>, <&qmgr 4>;
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intel,queue-pkt-txdone = <&qmgr 9>;
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/* The Goramo GPIO-based clock etc control */
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cts-gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
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rts-gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
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dcd-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
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dtr-gpios = <&gpio_74 3 GPIO_ACTIVE_LOW>;
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clk-internal-gpios = <&gpio_74 1 GPIO_ACTIVE_HIGH>;
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};
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};
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/* EthB */
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ethernet@c8009000 {
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status = "ok";
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queue-rx = <&qmgr 3>;
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queue-txready = <&qmgr 32>;
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phy-mode = "rgmii";
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phy-handle = <&phy0>;
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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phy0: ethernet-phy@0 {
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reg = <0>;
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};
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phy1: ethernet-phy@1 {
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reg = <1>;
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};
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};
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};
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/* EthC */
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ethernet@c800a000 {
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status = "ok";
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queue-rx = <&qmgr 4>;
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queue-txready = <&qmgr 33>;
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phy-mode = "rgmii";
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phy-handle = <&phy1>;
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};
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};
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};
+17
arch/arm/boot/dts/intel-ixp4xx.dtsi
+17
arch/arm/boot/dts/intel-ixp4xx.dtsi
···
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npe: npe@c8006000 {
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compatible = "intel,ixp4xx-network-processing-engine";
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reg = <0xc8006000 0x1000>, <0xc8007000 0x1000>, <0xc8008000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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/* NPE-A contains two high-speed serial links */
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hss@0 {
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compatible = "intel,ixp4xx-hss";
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reg = <0>;
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intel,npe-handle = <&npe 0>;
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status = "disabled";
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};
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hss@1 {
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compatible = "intel,ixp4xx-hss";
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reg = <1>;
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intel,npe-handle = <&npe 0>;
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status = "disabled";
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};
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/* NPE-C contains a crypto accelerator */
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crypto {