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kernel os linux

spi: npcm-fiu: Add NPCM8XX support

Adding FIU NPCM8XX support to NPCM FIU driver.
NPCM8XX FIU supports four controllers.

As part of adding NPCM8XX support:
- Add NPCM8XX specific compatible string.
- Using an internal burst configuration register instead of a GCR
register.
- Support FIU1 controller.

Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
Link: https://lore.kernel.org/r/20220718081146.256070-4-tmaimon77@gmail.com
Signed-off-by: Mark Brown <broonie@kernel.org>

authored by

Tomer Maimon and committed by
Mark Brown
650b014f d50fef8a

+25
+25
drivers/spi/spi-npcm-fiu.c
··· 36 36 #define NPCM_FIU_UMA_DR1 0x34 37 37 #define NPCM_FIU_UMA_DR2 0x38 38 38 #define NPCM_FIU_UMA_DR3 0x3C 39 + #define NPCM_FIU_CFG 0x78 39 40 #define NPCM_FIU_MAX_REG_LIMIT 0x80 40 41 41 42 /* FIU Direct Read Configuration Register */ ··· 152 151 #define NPCM_FIU_UMA_DR3_RB13 GENMASK(15, 8) 153 152 #define NPCM_FIU_UMA_DR3_RB12 GENMASK(7, 0) 154 153 154 + /* FIU Configuration Register */ 155 + #define NPCM_FIU_CFG_FIU_FIX BIT(31) 156 + 155 157 /* FIU Read Mode */ 156 158 enum { 157 159 DRD_SINGLE_WIRE_MODE = 0, ··· 191 187 FIU0 = 0, 192 188 FIU3, 193 189 FIUX, 190 + FIU1, 194 191 }; 195 192 196 193 struct npcm_fiu_info { ··· 217 212 static const struct fiu_data npcm7xx_fiu_data = { 218 213 .npcm_fiu_data_info = npcm7xx_fiu_info, 219 214 .fiu_max = 3, 215 + }; 216 + 217 + static const struct npcm_fiu_info npxm8xx_fiu_info[] = { 218 + {.name = "FIU0", .fiu_id = FIU0, 219 + .max_map_size = MAP_SIZE_128MB, .max_cs = 2}, 220 + {.name = "FIU3", .fiu_id = FIU3, 221 + .max_map_size = MAP_SIZE_128MB, .max_cs = 4}, 222 + {.name = "FIUX", .fiu_id = FIUX, 223 + .max_map_size = MAP_SIZE_16MB, .max_cs = 2}, 224 + {.name = "FIU1", .fiu_id = FIU1, 225 + .max_map_size = MAP_SIZE_16MB, .max_cs = 4} }; 226 + 227 + static const struct fiu_data npxm8xx_fiu_data = { 228 + .npcm_fiu_data_info = npxm8xx_fiu_info, 229 + .fiu_max = 4, 220 230 }; 221 231 222 232 struct npcm_fiu_spi; ··· 644 624 regmap_update_bits(gcr_regmap, NPCM7XX_INTCR3_OFFSET, 645 625 NPCM7XX_INTCR3_FIU_FIX, 646 626 NPCM7XX_INTCR3_FIU_FIX); 627 + } else { 628 + regmap_update_bits(fiu->regmap, NPCM_FIU_CFG, 629 + NPCM_FIU_CFG_FIU_FIX, 630 + NPCM_FIU_CFG_FIU_FIX); 647 631 } 648 632 649 633 if (desc->info.op_tmpl.data.dir == SPI_MEM_DATA_IN) { ··· 688 664 689 665 static const struct of_device_id npcm_fiu_dt_ids[] = { 690 666 { .compatible = "nuvoton,npcm750-fiu", .data = &npcm7xx_fiu_data }, 667 + { .compatible = "nuvoton,npcm845-fiu", .data = &npxm8xx_fiu_data }, 691 668 { /* sentinel */ } 692 669 }; 693 670