gpio: generic: rename BGPIOF_ flags to GPIO_GENERIC_

Make the flags passed to gpio_generic_chip_init() use the same prefix as
the rest of the modernized generic GPIO chip API.

Link: https://lore.kernel.org/r/[e-mail]
Signed-off-by: Bartosz Golaszewski <[e-mail]>

drivers/gpio/gpio-amdpt.c

···
 		.dat = pt_gpio->reg_base + PT_INPUTDATA_REG,
 		.set = pt_gpio->reg_base + PT_OUTPUTDATA_REG,
 		.dirout = pt_gpio->reg_base + PT_DIRECTION_REG,
-		.flags = BGPIOF_READ_OUTPUT_REG_SET,
+		.flags = GPIO_GENERIC_READ_OUTPUT_REG_SET,
 	};
 
 	ret = gpio_generic_chip_init(&pt_gpio->chip, &config);

drivers/gpio/gpio-brcmstb.c

···
 	 * else leave I/O in little endian mode.
 	 */
 #if defined(CONFIG_MIPS) && defined(__BIG_ENDIAN)
-	flags = BGPIOF_BIG_ENDIAN_BYTE_ORDER;
+	flags = GPIO_GENERIC_BIG_ENDIAN_BYTE_ORDER;
 #endif
 
 	of_property_for_each_u32(np, "brcm,gpio-bank-widths", bank_width) {

drivers/gpio/gpio-cadence.c

···
 	config.dat = cgpio->regs + CDNS_GPIO_INPUT_VALUE;
 	config.set = cgpio->regs + CDNS_GPIO_OUTPUT_VALUE;
 	config.dirin = cgpio->regs + CDNS_GPIO_DIRECTION_MODE;
-	config.flags = BGPIOF_READ_OUTPUT_REG_SET;
+	config.flags = GPIO_GENERIC_READ_OUTPUT_REG_SET;
 
 	ret = gpio_generic_chip_init(&cgpio->gen_gc, &config);
 	if (ret) {

drivers/gpio/gpio-ge.c

···
 		.dat = regs + GEF_GPIO_IN,
 		.set = regs + GEF_GPIO_OUT,
 		.dirin = regs + GEF_GPIO_DIRECT,
-		.flags = BGPIOF_BIG_ENDIAN_BYTE_ORDER,
+		.flags = GPIO_GENERIC_BIG_ENDIAN_BYTE_ORDER,
 	};
 
 	ret = gpio_generic_chip_init(chip, &config);

drivers/gpio/gpio-grgpio.c

···
 		.dat = regs + GRGPIO_DATA,
 		.set = regs + GRGPIO_OUTPUT,
 		.dirout = regs + GRGPIO_DIR,
-		.flags = BGPIOF_BIG_ENDIAN_BYTE_ORDER,
+		.flags = GPIO_GENERIC_BIG_ENDIAN_BYTE_ORDER,
 	};
 
 	gc = &priv->chip.gc;

drivers/gpio/gpio-hisi.c

···
 		.clr = hisi_gpio->reg_base + HISI_GPIO_SWPORT_DR_CLR_WX,
 		.dirout = hisi_gpio->reg_base + HISI_GPIO_SWPORT_DDR_SET_WX,
 		.dirin = hisi_gpio->reg_base + HISI_GPIO_SWPORT_DDR_CLR_WX,
-		.flags = BGPIOF_NO_SET_ON_INPUT | BGPIOF_UNREADABLE_REG_DIR,
+		.flags = GPIO_GENERIC_NO_SET_ON_INPUT |
+			 GPIO_GENERIC_UNREADABLE_REG_DIR,
 	};
 
 	ret = gpio_generic_chip_init(&hisi_gpio->chip, &config);

drivers/gpio/gpio-hlwd.c

···
 		.dat = hlwd->regs + HW_GPIOB_IN,
 		.set = hlwd->regs + HW_GPIOB_OUT,
 		.dirout = hlwd->regs + HW_GPIOB_DIR,
-		.flags = BGPIOF_BIG_ENDIAN_BYTE_ORDER,
+		.flags = GPIO_GENERIC_BIG_ENDIAN_BYTE_ORDER,
 	};
 
 	res = gpio_generic_chip_init(&hlwd->gpioc, &config);

drivers/gpio/gpio-ixp4xx.c

···
 	 * for big endian.
 	 */
 #if defined(CONFIG_CPU_BIG_ENDIAN)
-	flags = BGPIOF_BIG_ENDIAN_BYTE_ORDER;
+	flags = GPIO_GENERIC_BIG_ENDIAN_BYTE_ORDER;
 #else
 	flags = 0;
 #endif

drivers/gpio/gpio-mmio.c

···
 		chip->reg_set = cfg->set;
 		gc->set = bgpio_set_set;
 		gc->set_multiple = bgpio_set_multiple_set;
-	} else if (cfg->flags & BGPIOF_NO_OUTPUT) {
+	} else if (cfg->flags & GPIO_GENERIC_NO_OUTPUT) {
 		gc->set = bgpio_set_none;
 		gc->set_multiple = NULL;
 	} else {
···
 		gc->set_multiple = bgpio_set_multiple;
 	}
 
-	if (!(cfg->flags & BGPIOF_UNREADABLE_REG_SET) &&
-	    (cfg->flags & BGPIOF_READ_OUTPUT_REG_SET)) {
+	if (!(cfg->flags & GPIO_GENERIC_UNREADABLE_REG_SET) &&
+	    (cfg->flags & GPIO_GENERIC_READ_OUTPUT_REG_SET)) {
 		gc->get = bgpio_get_set;
 		if (!chip->be_bits)
 			gc->get_multiple = bgpio_get_set_multiple;
···
 	if (cfg->dirout || cfg->dirin) {
 		chip->reg_dir_out = cfg->dirout;
 		chip->reg_dir_in = cfg->dirin;
-		if (cfg->flags & BGPIOF_NO_SET_ON_INPUT)
+		if (cfg->flags & GPIO_GENERIC_NO_SET_ON_INPUT)
 			gc->direction_output = bgpio_dir_out_dir_first;
 		else
 			gc->direction_output = bgpio_dir_out_val_first;
 		gc->direction_input = bgpio_dir_in;
 		gc->get_direction = bgpio_get_dir;
 	} else {
-		if (cfg->flags & BGPIOF_NO_OUTPUT)
+		if (cfg->flags & GPIO_GENERIC_NO_OUTPUT)
 			gc->direction_output = bgpio_dir_out_err;
 		else
 			gc->direction_output = bgpio_simple_dir_out;
 
-		if (cfg->flags & BGPIOF_NO_INPUT)
+		if (cfg->flags & GPIO_GENERIC_NO_INPUT)
 			gc->direction_input = bgpio_dir_in_err;
 		else
 			gc->direction_input = bgpio_simple_dir_in;
···
 	gc->label = dev_name(dev);
 	gc->base = -1;
 	gc->request = bgpio_request;
-	chip->be_bits = !!(flags & BGPIOF_BIG_ENDIAN);
+	chip->be_bits = !!(flags & GPIO_GENERIC_BIG_ENDIAN);
 
 	ret = gpiochip_get_ngpios(gc, dev);
 	if (ret)
···
 		return ret;
 
 	ret = bgpio_setup_accessors(dev, chip,
-				    flags & BGPIOF_BIG_ENDIAN_BYTE_ORDER);
+				    flags & GPIO_GENERIC_BIG_ENDIAN_BYTE_ORDER);
 	if (ret)
 		return ret;
 
···
 	if (ret)
 		return ret;
 
-	if (flags & BGPIOF_PINCTRL_BACKEND) {
+	if (flags & GPIO_GENERIC_PINCTRL_BACKEND) {
 		chip->pinctrl = true;
 		/* Currently this callback is only used for pincontrol */
 		gc->free = gpiochip_generic_free;
···
 
 	chip->sdata = chip->read_reg(chip->reg_dat);
 	if (gc->set == bgpio_set_set &&
-			!(flags & BGPIOF_UNREADABLE_REG_SET))
+			!(flags & GPIO_GENERIC_UNREADABLE_REG_SET))
 		chip->sdata = chip->read_reg(chip->reg_set);
 
-	if (flags & BGPIOF_UNREADABLE_REG_DIR)
+	if (flags & GPIO_GENERIC_UNREADABLE_REG_DIR)
 		chip->dir_unreadable = true;
 
 	/*
 	 * Inspect hardware to find initial direction setting.
 	 */
 	if ((chip->reg_dir_out || chip->reg_dir_in) &&
-	    !(flags & BGPIOF_UNREADABLE_REG_DIR)) {
+	    !(flags & GPIO_GENERIC_UNREADABLE_REG_DIR)) {
 		if (chip->reg_dir_out)
 			chip->sdir = chip->read_reg(chip->reg_dir_out);
 		else if (chip->reg_dir_in)
···
 		return -ENOMEM;
 
 	if (device_is_big_endian(dev))
-		flags |= BGPIOF_BIG_ENDIAN_BYTE_ORDER;
+		flags |= GPIO_GENERIC_BIG_ENDIAN_BYTE_ORDER;
 
 	if (device_property_read_bool(dev, "no-output"))
-		flags |= BGPIOF_NO_OUTPUT;
+		flags |= GPIO_GENERIC_NO_OUTPUT;
 
 	config = (struct gpio_generic_chip_config) {
 		.dev = dev,

drivers/gpio/gpio-mpc8xxx.c

···
 		.sz = 4,
 		.dat = mpc8xxx_gc->regs + GPIO_DAT,
 		.dirout = mpc8xxx_gc->regs + GPIO_DIR,
-		.flags = BGPIOF_BIG_ENDIAN
+		.flags = GPIO_GENERIC_BIG_ENDIAN
 	};
 
 	if (device_property_read_bool(dev, "little-endian")) {
 		dev_dbg(dev, "GPIO registers are LITTLE endian\n");
 	} else {
-		config.flags |= BGPIOF_BIG_ENDIAN_BYTE_ORDER;
+		config.flags |= GPIO_GENERIC_BIG_ENDIAN_BYTE_ORDER;
 		dev_dbg(dev, "GPIO registers are BIG endian\n");
 	}
 

drivers/gpio/gpio-mt7621.c

···
 		.set = set,
 		.clr = ctrl,
 		.dirout = diro,
-		.flags = BGPIOF_NO_SET_ON_INPUT,
+		.flags = GPIO_GENERIC_NO_SET_ON_INPUT,
 	};
 
 	ret = gpio_generic_chip_init(&rg->chip, &config);

drivers/gpio/gpio-mxc.c

···
 	config.dat = port->base + GPIO_PSR;
 	config.set = port->base + GPIO_DR;
 	config.dirout = port->base + GPIO_GDIR;
-	config.flags = BGPIOF_READ_OUTPUT_REG_SET;
+	config.flags = GPIO_GENERIC_READ_OUTPUT_REG_SET;
 
 	err = gpio_generic_chip_init(&port->gen_gc, &config);
 	if (err)

drivers/gpio/gpio-rda.c

···
 		.clr = rda_gpio->base + RDA_GPIO_CLR,
 		.dirout = rda_gpio->base + RDA_GPIO_OEN_SET_OUT,
 		.dirin = rda_gpio->base + RDA_GPIO_OEN_SET_IN,
-		.flags = BGPIOF_READ_OUTPUT_REG_SET,
+		.flags = GPIO_GENERIC_READ_OUTPUT_REG_SET,
 	};
 
 	ret = gpio_generic_chip_init(&rda_gpio->chip, &config);

drivers/gpio/gpio-realtek-otto.c

···
 		ctrl->bank_write = realtek_gpio_bank_write;
 		ctrl->line_imr_pos = realtek_gpio_line_imr_pos;
 	} else {
-		gen_gc_flags = BGPIOF_BIG_ENDIAN_BYTE_ORDER;
+		gen_gc_flags = GPIO_GENERIC_BIG_ENDIAN_BYTE_ORDER;
 		ctrl->bank_read = realtek_gpio_bank_read_swapped;
 		ctrl->bank_write = realtek_gpio_bank_write_swapped;
 		ctrl->line_imr_pos = realtek_gpio_line_imr_pos_swapped;

drivers/gpio/gpio-sifive.c

···
 		.set = chip->base + SIFIVE_GPIO_OUTPUT_VAL,
 		.dirout = chip->base + SIFIVE_GPIO_OUTPUT_EN,
 		.dirin = chip->base + SIFIVE_GPIO_INPUT_EN,
-		.flags = BGPIOF_READ_OUTPUT_REG_SET,
+		.flags = GPIO_GENERIC_READ_OUTPUT_REG_SET,
 	};
 
 	ret = gpio_generic_chip_init(&chip->gen_gc, &config);

drivers/gpio/gpio-spacemit-k1.c

···
 		.clr = clr,
 		.dirout = dirout,
 		.dirin = dirin,
-		.flags = BGPIOF_UNREADABLE_REG_SET | BGPIOF_UNREADABLE_REG_DIR,
+		.flags = GPIO_GENERIC_UNREADABLE_REG_SET |
+			 GPIO_GENERIC_UNREADABLE_REG_DIR,
 	};
 
 	/* This registers 32 GPIO lines per bank */

drivers/gpio/gpio-vf610.c

···
 	}
 
 	gc = &port->chip.gc;
-	flags = BGPIOF_PINCTRL_BACKEND;
+	flags = GPIO_GENERIC_PINCTRL_BACKEND;
 	/*
 	 * We only read the output register for current value on output
 	 * lines if the direction register is available so we can switch
 	 * direction.
 	 */
 	if (port->sdata->have_paddr)
-		flags |= BGPIOF_READ_OUTPUT_REG_SET;
+		flags |= GPIO_GENERIC_READ_OUTPUT_REG_SET;
 
 	config = (struct gpio_generic_chip_config) {
 		.dev = dev,

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

···
 			.dat = pctrl->gpio_bank[id].base + NPCM7XX_GP_N_DIN,
 			.set = pctrl->gpio_bank[id].base + NPCM7XX_GP_N_DOUT,
 			.dirin = pctrl->gpio_bank[id].base + NPCM7XX_GP_N_IEM,
-			.flags = BGPIOF_READ_OUTPUT_REG_SET,
+			.flags = GPIO_GENERIC_READ_OUTPUT_REG_SET,
 		};
 
 		ret = gpio_generic_chip_init(&pctrl->gpio_bank[id].chip, &config);

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

···
 			.dat = pctrl->gpio_bank[id].base + NPCM8XX_GP_N_DIN,
 			.set = pctrl->gpio_bank[id].base + NPCM8XX_GP_N_DOUT,
 			.dirin = pctrl->gpio_bank[id].base + NPCM8XX_GP_N_IEM,
-			.flags = BGPIOF_READ_OUTPUT_REG_SET,
+			.flags = GPIO_GENERIC_READ_OUTPUT_REG_SET,
 		};
 
 		ret = gpio_generic_chip_init(&pctrl->gpio_bank[id].chip, &config);

drivers/pinctrl/nuvoton/pinctrl-wpcm450.c

···
 			set = pctrl->gpio_base + bank->dataout;
 			dirout = pctrl->gpio_base + bank->cfg0;
 		} else {
-			flags = BGPIOF_NO_OUTPUT;
+			flags = GPIO_GENERIC_NO_OUTPUT;
 		}
 
 		config = (typeof(config)){

drivers/pinctrl/stm32/pinctrl-stm32-hdp.c

···
 		.dat = hdp->base + HDP_GPOVAL,
 		.set = hdp->base + HDP_GPOSET,
 		.clr = hdp->base + HDP_GPOCLR,
-		.flags = BGPIOF_NO_INPUT,
+		.flags = GPIO_GENERIC_NO_INPUT,
 	};
 
 	err = gpio_generic_chip_init(&hdp->gpio_chip, &config);

include/linux/gpio/driver.h

···
 
 #endif /* CONFIG_IRQ_DOMAIN_HIERARCHY */
 
-#define BGPIOF_BIG_ENDIAN		BIT(0)
-#define BGPIOF_UNREADABLE_REG_SET	BIT(1) /* reg_set is unreadable */
-#define BGPIOF_UNREADABLE_REG_DIR	BIT(2) /* reg_dir is unreadable */
-#define BGPIOF_BIG_ENDIAN_BYTE_ORDER	BIT(3)
-#define BGPIOF_READ_OUTPUT_REG_SET	BIT(4) /* reg_set stores output value */
-#define BGPIOF_NO_OUTPUT		BIT(5) /* only input */
-#define BGPIOF_NO_SET_ON_INPUT		BIT(6)
-#define BGPIOF_PINCTRL_BACKEND		BIT(7) /* Call pinctrl direction setters */
-#define BGPIOF_NO_INPUT			BIT(8) /* only output */
+#define GPIO_GENERIC_BIG_ENDIAN			BIT(0)
+#define GPIO_GENERIC_UNREADABLE_REG_SET		BIT(1) /* reg_set is unreadable */
+#define GPIO_GENERIC_UNREADABLE_REG_DIR		BIT(2) /* reg_dir is unreadable */
+#define GPIO_GENERIC_BIG_ENDIAN_BYTE_ORDER	BIT(3)
+#define GPIO_GENERIC_READ_OUTPUT_REG_SET	BIT(4) /* reg_set stores output value */
+#define GPIO_GENERIC_NO_OUTPUT			BIT(5) /* only input */
+#define GPIO_GENERIC_NO_SET_ON_INPUT		BIT(6)
+#define GPIO_GENERIC_PINCTRL_BACKEND		BIT(7) /* Call pinctrl direction setters */
+#define GPIO_GENERIC_NO_INPUT			BIT(8) /* only output */
 
 #ifdef CONFIG_GPIOLIB_IRQCHIP
 int gpiochip_irqchip_add_domain(struct gpio_chip *gc,