tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'armsoc-newsoc' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM new SoC family support from Arnd Bergmann:
"Two new SoC families are added this time.
Sugaya Taichi submitted support for the Milbeaut SoC family from
Socionext and explains:
"SC2000 is a SoC of the Milbeaut series. equipped with a DSP
optimized for computer vision. It also features advanced
functionalities such as 360-degree, real-time spherical stitching
with multi cameras, image stabilization for without mechanical
gimbals, and rolling shutter correction. More detail is below:
https://www.socionext.com/en/products/assp/milbeaut/SC2000.html"
Interestingly, this one has a history dating back to older chips made
by Socionext and previously Matsushita/Panasonic based on their own
mn10300 CPU architecture that was removed from the kernel last year.
Manivannan Sadhasivam adds support for another SoC family, this is the
Bitmain BM1880 chip used in the Sophon Edge TPU developer board.
The chip is intended for Deep Learning applications, and comes with
dual-core Arm Cortex-A53 to run Linux as well as a RISC-V
microcontroller core to control the tensor unit. For the moment, the
TPU is not accessible in mainline Linux, so we treat it as a generic
Arm SoC.
More information is available at
https://www.sophon.ai/"
* tag 'armsoc-newsoc' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc:
ARM: multi_v7_defconfig: add ARCH_MILBEAUT and ARCH_MILBEAUT_M10V
ARM: configs: Add Milbeaut M10V defconfig
ARM: dts: milbeaut: Add device tree set for the Milbeaut M10V board
clocksource/drivers/timer-milbeaut: Introduce timer for Milbeaut SoCs
dt-bindings: timer: Add Milbeaut M10V timer description
ARM: milbeaut: Add basic support for Milbeaut m10v SoC
dt-bindings: Add documentation for Milbeaut SoCs
dt-bindings: arm: Add SMP enable-method for Milbeaut
dt-bindings: sram: milbeaut: Add binding for Milbeaut smp-sram
MAINTAINERS: Add entry for Bitmain SoC platform
arm64: dts: bitmain: Add Sophon Egde board support
arm64: dts: bitmain: Add BM1880 SoC support
arm64: Add ARCH_BITMAIN platform
dt-bindings: arm: Document Bitmain BM1880 SoC
+854
+18
Documentation/devicetree/bindings/arm/bitmain.yaml
+18
Documentation/devicetree/bindings/arm/bitmain.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/arm/bitmain.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Bitmain platform device tree bindings
8
+
9
+
maintainers:
10
+
- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
11
+
12
+
properties:
13
+
compatible:
14
+
items:
15
+
- enum:
16
+
- bitmain,sophon-edge
17
+
- const: bitmain,bm1880
18
+
...
+1
Documentation/devicetree/bindings/arm/cpus.yaml
+1
Documentation/devicetree/bindings/arm/cpus.yaml
+22
Documentation/devicetree/bindings/arm/socionext/milbeaut.yaml
+22
Documentation/devicetree/bindings/arm/socionext/milbeaut.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/arm/milbeaut.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Milbeaut platforms device tree bindings
8
+
9
+
maintainers:
10
+
- Taichi Sugaya <sugaya.taichi@socionext.com>
11
+
- Takao Orito <orito.takao@socionext.com>
12
+
13
+
properties:
14
+
$nodename:
15
+
const: '/'
16
+
compatible:
17
+
oneOf:
18
+
- items:
19
+
- enum:
20
+
- socionext,milbeaut-m10v-evb
21
+
- const: socionext,sc2000a
22
+
...
+24
Documentation/devicetree/bindings/sram/milbeaut-smp-sram.txt
+24
Documentation/devicetree/bindings/sram/milbeaut-smp-sram.txt
···
1
+
Milbeaut SRAM for smp bringup
2
+
3
+
Milbeaut SoCs use a part of the sram for the bringup of the secondary cores.
4
+
Once they get powered up in the bootloader, they stay at the specific part
5
+
of the sram.
6
+
Therefore the part needs to be added as the sub-node of mmio-sram.
7
+
8
+
Required sub-node properties:
9
+
- compatible : should be "socionext,milbeaut-smp-sram"
10
+
11
+
Example:
12
+
13
+
sram: sram@0 {
14
+
compatible = "mmio-sram";
15
+
reg = <0x0 0x10000>;
16
+
#address-cells = <1>;
17
+
#size-cells = <1>;
18
+
ranges = <0 0x0 0x10000>;
19
+
20
+
smp-sram@f100 {
21
+
compatible = "socionext,milbeaut-smp-sram";
22
+
reg = <0xf100 0x20>;
23
+
};
24
+
};
+17
Documentation/devicetree/bindings/timer/socionext,milbeaut-timer.txt
+17
Documentation/devicetree/bindings/timer/socionext,milbeaut-timer.txt
···
1
+
Milbeaut SoCs Timer Controller
2
+
3
+
Required properties:
4
+
5
+
- compatible : should be "socionext,milbeaut-timer".
6
+
- reg : Specifies base physical address and size of the registers.
7
+
- interrupts : The interrupt of the first timer.
8
+
- clocks: phandle to the input clk.
9
+
10
+
Example:
11
+
12
+
timer {
13
+
compatible = "socionext,milbeaut-timer";
14
+
reg = <0x1e000050 0x20>
15
+
interrupts = <0 91 4>;
16
+
clocks = <&clk 4>;
17
+
};
+7
MAINTAINERS
+7
MAINTAINERS
···
1371
1371
F: arch/arm/boot/dts/aspeed-*
1372
1372
N: aspeed
1373
1373
1374
+
ARM/BITMAIN ARCHITECTURE
1375
+
M: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
1376
+
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
1377
+
S: Maintained
1378
+
F: arch/arm64/boot/dts/bitmain/
1379
+
F: Documentation/devicetree/bindings/arm/bitmain.yaml
1380
+
1374
1381
ARM/CALXEDA HIGHBANK ARCHITECTURE
1375
1382
M: Rob Herring <robh@kernel.org>
1376
1383
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
+2
arch/arm/Kconfig
+2
arch/arm/Kconfig
+1
arch/arm/Makefile
+1
arch/arm/Makefile
···
190
190
machine-$(CONFIG_ARCH_MVEBU) += mvebu
191
191
machine-$(CONFIG_ARCH_MXC) += imx
192
192
machine-$(CONFIG_ARCH_MEDIATEK) += mediatek
193
+
machine-$(CONFIG_ARCH_MILBEAUT) += milbeaut
193
194
machine-$(CONFIG_ARCH_MXS) += mxs
194
195
machine-$(CONFIG_ARCH_NETX) += netx
195
196
machine-$(CONFIG_ARCH_NOMADIK) += nomadik
+1
arch/arm/boot/dts/Makefile
+1
arch/arm/boot/dts/Makefile
+32
arch/arm/boot/dts/milbeaut-m10v-evb.dts
+32
arch/arm/boot/dts/milbeaut-m10v-evb.dts
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/* Socionext Milbeaut M10V Evaluation Board */
3
+
/dts-v1/;
4
+
#include "milbeaut-m10v.dtsi"
5
+
6
+
/ {
7
+
model = "Socionext M10V EVB";
8
+
compatible = "socionext,milbeaut-m10v-evb", "socionext,sc2000a";
9
+
10
+
aliases {
11
+
serial0 = &uart1;
12
+
};
13
+
14
+
chosen {
15
+
bootargs = "rootwait earlycon";
16
+
stdout-path = "serial0:115200n8";
17
+
};
18
+
19
+
clocks {
20
+
uclk40xi: uclk40xi {
21
+
compatible = "fixed-clock";
22
+
#clock-cells = <0>;
23
+
clock-frequency = <40000000>;
24
+
};
25
+
};
26
+
27
+
memory@40000000 {
28
+
device_type = "memory";
29
+
reg = <0x40000000 0x80000000>;
30
+
};
31
+
32
+
};
+95
arch/arm/boot/dts/milbeaut-m10v.dtsi
+95
arch/arm/boot/dts/milbeaut-m10v.dtsi
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
#include <dt-bindings/interrupt-controller/irq.h>
3
+
#include <dt-bindings/input/input.h>
4
+
#include <dt-bindings/gpio/gpio.h>
5
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
6
+
7
+
/ {
8
+
compatible = "socionext,sc2000a";
9
+
interrupt-parent = <&gic>;
10
+
#address-cells = <1>;
11
+
#size-cells = <1>;
12
+
13
+
cpus {
14
+
#address-cells = <1>;
15
+
#size-cells = <0>;
16
+
enable-method = "socionext,milbeaut-m10v-smp";
17
+
cpu@f00 {
18
+
device_type = "cpu";
19
+
compatible = "arm,cortex-a7";
20
+
reg = <0xf00>;
21
+
};
22
+
cpu@f01 {
23
+
device_type = "cpu";
24
+
compatible = "arm,cortex-a7";
25
+
reg = <0xf01>;
26
+
};
27
+
cpu@f02 {
28
+
device_type = "cpu";
29
+
compatible = "arm,cortex-a7";
30
+
reg = <0xf02>;
31
+
};
32
+
cpu@f03 {
33
+
device_type = "cpu";
34
+
compatible = "arm,cortex-a7";
35
+
reg = <0xf03>;
36
+
};
37
+
};
38
+
39
+
timer { /* The Generic Timer */
40
+
compatible = "arm,armv7-timer";
41
+
interrupts = <GIC_PPI 13
42
+
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
43
+
<GIC_PPI 14
44
+
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
45
+
<GIC_PPI 11
46
+
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
47
+
<GIC_PPI 10
48
+
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
49
+
clock-frequency = <40000000>;
50
+
always-on;
51
+
};
52
+
53
+
soc {
54
+
compatible = "simple-bus";
55
+
#address-cells = <1>;
56
+
#size-cells = <1>;
57
+
ranges;
58
+
interrupt-parent = <&gic>;
59
+
60
+
gic: interrupt-controller@1d000000 {
61
+
compatible = "arm,cortex-a7-gic";
62
+
interrupt-controller;
63
+
#interrupt-cells = <3>;
64
+
reg = <0x1d001000 0x1000>,
65
+
<0x1d002000 0x1000>; /* CPU I/f base and size */
66
+
};
67
+
68
+
timer@1e000050 { /* 32-bit Reload Timers */
69
+
compatible = "socionext,milbeaut-timer";
70
+
reg = <0x1e000050 0x20>;
71
+
interrupts = <0 91 4>;
72
+
};
73
+
74
+
uart1: serial@1e700010 { /* PE4, PE5 */
75
+
/* Enable this as ttyUSI0 */
76
+
compatible = "socionext,milbeaut-usio-uart";
77
+
reg = <0x1e700010 0x10>;
78
+
interrupts = <0 141 0x4>, <0 149 0x4>;
79
+
interrupt-names = "rx", "tx";
80
+
};
81
+
82
+
};
83
+
84
+
sram@0 {
85
+
compatible = "mmio-sram";
86
+
reg = <0x0 0x10000>;
87
+
#address-cells = <1>;
88
+
#size-cells = <1>;
89
+
ranges = <0 0x0 0x10000>;
90
+
smp-sram@f100 {
91
+
compatible = "socionext,milbeaut-smp-sram";
92
+
reg = <0xf100 0x20>;
93
+
};
94
+
};
95
+
};
+119
arch/arm/configs/milbeaut_m10v_defconfig
+119
arch/arm/configs/milbeaut_m10v_defconfig
···
1
+
CONFIG_SYSVIPC=y
2
+
CONFIG_NO_HZ=y
3
+
CONFIG_HIGH_RES_TIMERS=y
4
+
CONFIG_CGROUPS=y
5
+
CONFIG_BLK_DEV_INITRD=y
6
+
CONFIG_EMBEDDED=y
7
+
CONFIG_PERF_EVENTS=y
8
+
CONFIG_ARCH_MILBEAUT=y
9
+
CONFIG_ARCH_MILBEAUT_M10V=y
10
+
CONFIG_ARM_THUMBEE=y
11
+
# CONFIG_VDSO is not set
12
+
# CONFIG_CACHE_L2X0 is not set
13
+
CONFIG_ARM_ERRATA_430973=y
14
+
CONFIG_ARM_ERRATA_720789=y
15
+
CONFIG_ARM_ERRATA_754322=y
16
+
CONFIG_ARM_ERRATA_754327=y
17
+
CONFIG_ARM_ERRATA_764369=y
18
+
CONFIG_ARM_ERRATA_775420=y
19
+
CONFIG_ARM_ERRATA_798181=y
20
+
CONFIG_SMP=y
21
+
# CONFIG_SMP_ON_UP is not set
22
+
# CONFIG_ARM_CPU_TOPOLOGY is not set
23
+
CONFIG_HAVE_ARM_ARCH_TIMER=y
24
+
CONFIG_NR_CPUS=16
25
+
CONFIG_THUMB2_KERNEL=y
26
+
# CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11 is not set
27
+
# CONFIG_ARM_PATCH_IDIV is not set
28
+
CONFIG_HIGHMEM=y
29
+
CONFIG_FORCE_MAX_ZONEORDER=12
30
+
CONFIG_SECCOMP=y
31
+
CONFIG_KEXEC=y
32
+
CONFIG_EFI=y
33
+
CONFIG_CPU_FREQ=y
34
+
CONFIG_CPU_FREQ_STAT=y
35
+
CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
36
+
CONFIG_CPU_FREQ_GOV_POWERSAVE=m
37
+
CONFIG_CPU_FREQ_GOV_USERSPACE=m
38
+
CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m
39
+
CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
40
+
CONFIG_CPUFREQ_DT=y
41
+
CONFIG_QORIQ_CPUFREQ=y
42
+
CONFIG_CPU_IDLE=y
43
+
CONFIG_ARM_CPUIDLE=y
44
+
CONFIG_VFP=y
45
+
CONFIG_NEON=y
46
+
CONFIG_KERNEL_MODE_NEON=y
47
+
CONFIG_EFI_VARS=m
48
+
CONFIG_EFI_CAPSULE_LOADER=m
49
+
CONFIG_ARM_CRYPTO=y
50
+
CONFIG_CRYPTO_SHA1_ARM_NEON=m
51
+
CONFIG_CRYPTO_SHA1_ARM_CE=m
52
+
CONFIG_CRYPTO_SHA2_ARM_CE=m
53
+
CONFIG_CRYPTO_SHA512_ARM=m
54
+
CONFIG_CRYPTO_AES_ARM=m
55
+
CONFIG_CRYPTO_AES_ARM_BS=m
56
+
CONFIG_CRYPTO_AES_ARM_CE=m
57
+
CONFIG_CRYPTO_GHASH_ARM_CE=m
58
+
CONFIG_CRYPTO_CRC32_ARM_CE=m
59
+
CONFIG_CRYPTO_CHACHA20_NEON=m
60
+
CONFIG_MODULES=y
61
+
CONFIG_MODULE_UNLOAD=y
62
+
CONFIG_PARTITION_ADVANCED=y
63
+
CONFIG_CMDLINE_PARTITION=y
64
+
CONFIG_CMA=y
65
+
CONFIG_DEVTMPFS=y
66
+
CONFIG_DEVTMPFS_MOUNT=y
67
+
CONFIG_DMA_CMA=y
68
+
CONFIG_CMA_SIZE_MBYTES=64
69
+
CONFIG_OF_OVERLAY=y
70
+
CONFIG_BLK_DEV_LOOP=y
71
+
CONFIG_BLK_DEV_RAM=y
72
+
CONFIG_BLK_DEV_RAM_SIZE=65536
73
+
CONFIG_SRAM=y
74
+
CONFIG_INPUT_FF_MEMLESS=m
75
+
CONFIG_INPUT_MATRIXKMAP=y
76
+
# CONFIG_INPUT_KEYBOARD is not set
77
+
# CONFIG_INPUT_MOUSE is not set
78
+
CONFIG_SERIO_LIBPS2=y
79
+
CONFIG_VT_HW_CONSOLE_BINDING=y
80
+
CONFIG_SERIAL_DEV_BUS=y
81
+
# CONFIG_HW_RANDOM is not set
82
+
CONFIG_GPIOLIB=y
83
+
CONFIG_GPIO_GENERIC_PLATFORM=y
84
+
# CONFIG_HWMON is not set
85
+
CONFIG_MEDIA_SUPPORT=m
86
+
CONFIG_MEDIA_CAMERA_SUPPORT=y
87
+
CONFIG_MEDIA_CONTROLLER=y
88
+
# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set
89
+
# CONFIG_HID is not set
90
+
# CONFIG_USB_SUPPORT is not set
91
+
CONFIG_SYNC_FILE=y
92
+
# CONFIG_VIRTIO_MENU is not set
93
+
# CONFIG_IOMMU_SUPPORT is not set
94
+
CONFIG_SOC_BRCMSTB=y
95
+
CONFIG_MEMORY=y
96
+
# CONFIG_ARM_PMU is not set
97
+
CONFIG_EXT4_FS=y
98
+
CONFIG_AUTOFS4_FS=y
99
+
CONFIG_MSDOS_FS=y
100
+
CONFIG_VFAT_FS=y
101
+
CONFIG_NTFS_FS=y
102
+
CONFIG_TMPFS=y
103
+
CONFIG_TMPFS_POSIX_ACL=y
104
+
CONFIG_CONFIGFS_FS=y
105
+
# CONFIG_MISC_FILESYSTEMS is not set
106
+
CONFIG_NLS_CODEPAGE_437=y
107
+
CONFIG_NLS_ISO8859_1=y
108
+
CONFIG_NLS_UTF8=y
109
+
CONFIG_KEYS=y
110
+
CONFIG_CRYPTO_MANAGER=y
111
+
# CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set
112
+
CONFIG_CRYPTO_SEQIV=m
113
+
# CONFIG_CRYPTO_ECHAINIV is not set
114
+
CONFIG_CRYPTO_AES=y
115
+
# CONFIG_CRYPTO_HW is not set
116
+
CONFIG_CRC_CCITT=m
117
+
CONFIG_CRC_ITU_T=m
118
+
CONFIG_PRINTK_TIME=y
119
+
CONFIG_MAGIC_SYSRQ=y
+2
arch/arm/configs/multi_v7_defconfig
+2
arch/arm/configs/multi_v7_defconfig
+20
arch/arm/mach-milbeaut/Kconfig
+20
arch/arm/mach-milbeaut/Kconfig
···
1
+
# SPDX-License-Identifier: GPL-2.0
2
+
menuconfig ARCH_MILBEAUT
3
+
bool "Socionext Milbeaut SoCs"
4
+
depends on ARCH_MULTI_V7
5
+
select ARM_GIC
6
+
help
7
+
This enables support for Socionext Milbeaut SoCs
8
+
9
+
if ARCH_MILBEAUT
10
+
11
+
config ARCH_MILBEAUT_M10V
12
+
bool "Milbeaut SC2000/M10V platform"
13
+
select ARM_ARCH_TIMER
14
+
select MILBEAUT_TIMER
15
+
select PINCTRL
16
+
select PINCTRL_MILBEAUT
17
+
help
18
+
Support for Socionext's MILBEAUT M10V based systems
19
+
20
+
endif
+1
arch/arm/mach-milbeaut/Makefile
+1
arch/arm/mach-milbeaut/Makefile
···
1
+
obj-$(CONFIG_SMP) += platsmp.o
+143
arch/arm/mach-milbeaut/platsmp.c
+143
arch/arm/mach-milbeaut/platsmp.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Copyright: (C) 2018 Socionext Inc.
4
+
* Copyright: (C) 2015 Linaro Ltd.
5
+
*/
6
+
7
+
#include <linux/cpu_pm.h>
8
+
#include <linux/irqchip/arm-gic.h>
9
+
#include <linux/of_address.h>
10
+
#include <linux/suspend.h>
11
+
12
+
#include <asm/cacheflush.h>
13
+
#include <asm/cp15.h>
14
+
#include <asm/idmap.h>
15
+
#include <asm/smp_plat.h>
16
+
#include <asm/suspend.h>
17
+
18
+
#define M10V_MAX_CPU 4
19
+
#define KERNEL_UNBOOT_FLAG 0x12345678
20
+
21
+
static void __iomem *m10v_smp_base;
22
+
23
+
static int m10v_boot_secondary(unsigned int l_cpu, struct task_struct *idle)
24
+
{
25
+
unsigned int mpidr, cpu, cluster;
26
+
27
+
if (!m10v_smp_base)
28
+
return -ENXIO;
29
+
30
+
mpidr = cpu_logical_map(l_cpu);
31
+
cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
32
+
cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
33
+
34
+
if (cpu >= M10V_MAX_CPU)
35
+
return -EINVAL;
36
+
37
+
pr_info("%s: cpu %u l_cpu %u cluster %u\n",
38
+
__func__, cpu, l_cpu, cluster);
39
+
40
+
writel(__pa_symbol(secondary_startup), m10v_smp_base + cpu * 4);
41
+
arch_send_wakeup_ipi_mask(cpumask_of(l_cpu));
42
+
43
+
return 0;
44
+
}
45
+
46
+
static void m10v_smp_init(unsigned int max_cpus)
47
+
{
48
+
unsigned int mpidr, cpu, cluster;
49
+
struct device_node *np;
50
+
51
+
np = of_find_compatible_node(NULL, NULL, "socionext,milbeaut-smp-sram");
52
+
if (!np)
53
+
return;
54
+
55
+
m10v_smp_base = of_iomap(np, 0);
56
+
if (!m10v_smp_base)
57
+
return;
58
+
59
+
mpidr = read_cpuid_mpidr();
60
+
cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
61
+
cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
62
+
pr_info("MCPM boot on cpu_%u cluster_%u\n", cpu, cluster);
63
+
64
+
for (cpu = 0; cpu < M10V_MAX_CPU; cpu++)
65
+
writel(KERNEL_UNBOOT_FLAG, m10v_smp_base + cpu * 4);
66
+
}
67
+
68
+
static void m10v_cpu_die(unsigned int l_cpu)
69
+
{
70
+
gic_cpu_if_down(0);
71
+
v7_exit_coherency_flush(louis);
72
+
wfi();
73
+
}
74
+
75
+
static int m10v_cpu_kill(unsigned int l_cpu)
76
+
{
77
+
unsigned int mpidr, cpu;
78
+
79
+
mpidr = cpu_logical_map(l_cpu);
80
+
cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
81
+
82
+
writel(KERNEL_UNBOOT_FLAG, m10v_smp_base + cpu * 4);
83
+
84
+
return 1;
85
+
}
86
+
87
+
static struct smp_operations m10v_smp_ops __initdata = {
88
+
.smp_prepare_cpus = m10v_smp_init,
89
+
.smp_boot_secondary = m10v_boot_secondary,
90
+
.cpu_die = m10v_cpu_die,
91
+
.cpu_kill = m10v_cpu_kill,
92
+
};
93
+
CPU_METHOD_OF_DECLARE(m10v_smp, "socionext,milbeaut-m10v-smp", &m10v_smp_ops);
94
+
95
+
static int m10v_pm_valid(suspend_state_t state)
96
+
{
97
+
return (state == PM_SUSPEND_STANDBY) || (state == PM_SUSPEND_MEM);
98
+
}
99
+
100
+
typedef void (*phys_reset_t)(unsigned long);
101
+
static phys_reset_t phys_reset;
102
+
103
+
static int m10v_die(unsigned long arg)
104
+
{
105
+
setup_mm_for_reboot();
106
+
asm("wfi");
107
+
/* Boot just like a secondary */
108
+
phys_reset = (phys_reset_t)(unsigned long)virt_to_phys(cpu_reset);
109
+
phys_reset(virt_to_phys(cpu_resume));
110
+
111
+
return 0;
112
+
}
113
+
114
+
static int m10v_pm_enter(suspend_state_t state)
115
+
{
116
+
switch (state) {
117
+
case PM_SUSPEND_STANDBY:
118
+
asm("wfi");
119
+
break;
120
+
case PM_SUSPEND_MEM:
121
+
cpu_pm_enter();
122
+
cpu_suspend(0, m10v_die);
123
+
cpu_pm_exit();
124
+
break;
125
+
}
126
+
return 0;
127
+
}
128
+
129
+
static const struct platform_suspend_ops m10v_pm_ops = {
130
+
.valid = m10v_pm_valid,
131
+
.enter = m10v_pm_enter,
132
+
};
133
+
134
+
struct clk *m10v_clclk_register(struct device *cpu_dev);
135
+
136
+
static int __init m10v_pm_init(void)
137
+
{
138
+
if (of_machine_is_compatible("socionext,milbeaut-evb"))
139
+
suspend_set_ops(&m10v_pm_ops);
140
+
141
+
return 0;
142
+
}
143
+
late_initcall(m10v_pm_init);
+5
arch/arm64/Kconfig.platforms
+5
arch/arm64/Kconfig.platforms
+1
arch/arm64/boot/dts/Makefile
+1
arch/arm64/boot/dts/Makefile
+3
arch/arm64/boot/dts/bitmain/Makefile
+3
arch/arm64/boot/dts/bitmain/Makefile
+50
arch/arm64/boot/dts/bitmain/bm1880-sophon-edge.dts
+50
arch/arm64/boot/dts/bitmain/bm1880-sophon-edge.dts
···
1
+
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2
+
/*
3
+
* Copyright (c) 2019 Linaro Ltd.
4
+
* Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
5
+
*/
6
+
7
+
/dts-v1/;
8
+
9
+
#include "bm1880.dtsi"
10
+
11
+
/ {
12
+
compatible = "bitmain,sophon-edge", "bitmain,bm1880";
13
+
model = "Sophon Edge";
14
+
15
+
aliases {
16
+
serial0 = &uart0;
17
+
serial1 = &uart2;
18
+
serial2 = &uart1;
19
+
};
20
+
21
+
chosen {
22
+
stdout-path = "serial0:115200n8";
23
+
};
24
+
25
+
memory@0 {
26
+
device_type = "memory";
27
+
reg = <0x1 0x00000000 0x0 0x40000000>; // 1GB
28
+
};
29
+
30
+
uart_clk: uart-clk {
31
+
compatible = "fixed-clock";
32
+
clock-frequency = <500000000>;
33
+
#clock-cells = <0>;
34
+
};
35
+
};
36
+
37
+
&uart0 {
38
+
status = "okay";
39
+
clocks = <&uart_clk>;
40
+
};
41
+
42
+
&uart1 {
43
+
status = "okay";
44
+
clocks = <&uart_clk>;
45
+
};
46
+
47
+
&uart2 {
48
+
status = "okay";
49
+
clocks = <&uart_clk>;
50
+
};
+119
arch/arm64/boot/dts/bitmain/bm1880.dtsi
+119
arch/arm64/boot/dts/bitmain/bm1880.dtsi
···
1
+
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2
+
/*
3
+
* Copyright (c) 2019 Linaro Ltd.
4
+
* Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
5
+
*/
6
+
7
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
8
+
9
+
/ {
10
+
compatible = "bitmain,bm1880";
11
+
interrupt-parent = <&gic>;
12
+
#address-cells = <2>;
13
+
#size-cells = <2>;
14
+
15
+
cpus {
16
+
#address-cells = <1>;
17
+
#size-cells = <0>;
18
+
19
+
cpu0: cpu@0 {
20
+
device_type = "cpu";
21
+
compatible = "arm,cortex-a53";
22
+
reg = <0x0>;
23
+
enable-method = "psci";
24
+
};
25
+
26
+
cpu1: cpu@1 {
27
+
device_type = "cpu";
28
+
compatible = "arm,cortex-a53";
29
+
reg = <0x1>;
30
+
enable-method = "psci";
31
+
};
32
+
};
33
+
34
+
reserved-memory {
35
+
#address-cells = <2>;
36
+
#size-cells = <2>;
37
+
ranges;
38
+
39
+
secmon@100000000 {
40
+
reg = <0x1 0x00000000 0x0 0x20000>;
41
+
no-map;
42
+
};
43
+
44
+
jpu@130000000 {
45
+
reg = <0x1 0x30000000 0x0 0x08000000>; // 128M
46
+
no-map;
47
+
};
48
+
49
+
vpu@138000000 {
50
+
reg = <0x1 0x38000000 0x0 0x08000000>; // 128M
51
+
no-map;
52
+
};
53
+
};
54
+
55
+
psci {
56
+
compatible = "arm,psci-0.2";
57
+
method = "smc";
58
+
};
59
+
60
+
timer {
61
+
compatible = "arm,armv8-timer";
62
+
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
63
+
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
64
+
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
65
+
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
66
+
};
67
+
68
+
soc {
69
+
compatible = "simple-bus";
70
+
#address-cells = <2>;
71
+
#size-cells = <2>;
72
+
ranges;
73
+
74
+
gic: interrupt-controller@50001000 {
75
+
compatible = "arm,gic-400";
76
+
reg = <0x0 0x50001000 0x0 0x1000>,
77
+
<0x0 0x50002000 0x0 0x2000>;
78
+
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
79
+
interrupt-controller;
80
+
#interrupt-cells = <3>;
81
+
};
82
+
83
+
uart0: serial@58018000 {
84
+
compatible = "snps,dw-apb-uart";
85
+
reg = <0x0 0x58018000 0x0 0x2000>;
86
+
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
87
+
reg-shift = <2>;
88
+
reg-io-width = <4>;
89
+
status = "disabled";
90
+
};
91
+
92
+
uart1: serial@5801A000 {
93
+
compatible = "snps,dw-apb-uart";
94
+
reg = <0x0 0x5801a000 0x0 0x2000>;
95
+
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
96
+
reg-shift = <2>;
97
+
reg-io-width = <4>;
98
+
status = "disabled";
99
+
};
100
+
101
+
uart2: serial@5801C000 {
102
+
compatible = "snps,dw-apb-uart";
103
+
reg = <0x0 0x5801c000 0x0 0x2000>;
104
+
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
105
+
reg-shift = <2>;
106
+
reg-io-width = <4>;
107
+
status = "disabled";
108
+
};
109
+
110
+
uart3: serial@5801E000 {
111
+
compatible = "snps,dw-apb-uart";
112
+
reg = <0x0 0x5801e000 0x0 0x2000>;
113
+
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
114
+
reg-shift = <2>;
115
+
reg-io-width = <4>;
116
+
status = "disabled";
117
+
};
118
+
};
119
+
};
+9
drivers/clocksource/Kconfig
+9
drivers/clocksource/Kconfig
···
645
645
help
646
646
This option enables support for gx6605s SOC's timer.
647
647
648
+
config MILBEAUT_TIMER
649
+
bool "Milbeaut timer driver" if COMPILE_TEST
650
+
depends on OF
651
+
depends on ARM
652
+
select TIMER_OF
653
+
select CLKSRC_MMIO
654
+
help
655
+
Enables the support for Milbeaut timer driver.
656
+
648
657
endmenu
+1
drivers/clocksource/Makefile
+1
drivers/clocksource/Makefile
···
55
55
obj-$(CONFIG_CLKSRC_NPS) += timer-nps.o
56
56
obj-$(CONFIG_OXNAS_RPS_TIMER) += timer-oxnas-rps.o
57
57
obj-$(CONFIG_OWL_TIMER) += timer-owl.o
58
+
obj-$(CONFIG_MILBEAUT_TIMER) += timer-milbeaut.o
58
59
obj-$(CONFIG_SPRD_TIMER) += timer-sprd.o
59
60
obj-$(CONFIG_NPCM7XX_TIMER) += timer-npcm7xx.o
60
61
obj-$(CONFIG_RDA_TIMER) += timer-rda.o
+161
drivers/clocksource/timer-milbeaut.c
+161
drivers/clocksource/timer-milbeaut.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Copyright (C) 2018 Socionext Inc.
4
+
*/
5
+
6
+
#include <linux/clk.h>
7
+
#include <linux/interrupt.h>
8
+
#include <linux/irq.h>
9
+
#include <linux/irqreturn.h>
10
+
#include <linux/sched_clock.h>
11
+
#include "timer-of.h"
12
+
13
+
#define MLB_TMR_TMCSR_OFS 0x0
14
+
#define MLB_TMR_TMR_OFS 0x4
15
+
#define MLB_TMR_TMRLR1_OFS 0x8
16
+
#define MLB_TMR_TMRLR2_OFS 0xc
17
+
#define MLB_TMR_REGSZPCH 0x10
18
+
19
+
#define MLB_TMR_TMCSR_OUTL BIT(5)
20
+
#define MLB_TMR_TMCSR_RELD BIT(4)
21
+
#define MLB_TMR_TMCSR_INTE BIT(3)
22
+
#define MLB_TMR_TMCSR_UF BIT(2)
23
+
#define MLB_TMR_TMCSR_CNTE BIT(1)
24
+
#define MLB_TMR_TMCSR_TRG BIT(0)
25
+
26
+
#define MLB_TMR_TMCSR_CSL_DIV2 0
27
+
#define MLB_TMR_DIV_CNT 2
28
+
29
+
#define MLB_TMR_SRC_CH (1)
30
+
#define MLB_TMR_EVT_CH (0)
31
+
32
+
#define MLB_TMR_SRC_CH_OFS (MLB_TMR_REGSZPCH * MLB_TMR_SRC_CH)
33
+
#define MLB_TMR_EVT_CH_OFS (MLB_TMR_REGSZPCH * MLB_TMR_EVT_CH)
34
+
35
+
#define MLB_TMR_SRC_TMCSR_OFS (MLB_TMR_SRC_CH_OFS + MLB_TMR_TMCSR_OFS)
36
+
#define MLB_TMR_SRC_TMR_OFS (MLB_TMR_SRC_CH_OFS + MLB_TMR_TMR_OFS)
37
+
#define MLB_TMR_SRC_TMRLR1_OFS (MLB_TMR_SRC_CH_OFS + MLB_TMR_TMRLR1_OFS)
38
+
#define MLB_TMR_SRC_TMRLR2_OFS (MLB_TMR_SRC_CH_OFS + MLB_TMR_TMRLR2_OFS)
39
+
40
+
#define MLB_TMR_EVT_TMCSR_OFS (MLB_TMR_EVT_CH_OFS + MLB_TMR_TMCSR_OFS)
41
+
#define MLB_TMR_EVT_TMR_OFS (MLB_TMR_EVT_CH_OFS + MLB_TMR_TMR_OFS)
42
+
#define MLB_TMR_EVT_TMRLR1_OFS (MLB_TMR_EVT_CH_OFS + MLB_TMR_TMRLR1_OFS)
43
+
#define MLB_TMR_EVT_TMRLR2_OFS (MLB_TMR_EVT_CH_OFS + MLB_TMR_TMRLR2_OFS)
44
+
45
+
#define MLB_TIMER_RATING 500
46
+
47
+
static irqreturn_t mlb_timer_interrupt(int irq, void *dev_id)
48
+
{
49
+
struct clock_event_device *clk = dev_id;
50
+
struct timer_of *to = to_timer_of(clk);
51
+
u32 val;
52
+
53
+
val = readl_relaxed(timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
54
+
val &= ~MLB_TMR_TMCSR_UF;
55
+
writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
56
+
57
+
clk->event_handler(clk);
58
+
59
+
return IRQ_HANDLED;
60
+
}
61
+
62
+
static int mlb_set_state_periodic(struct clock_event_device *clk)
63
+
{
64
+
struct timer_of *to = to_timer_of(clk);
65
+
u32 val = MLB_TMR_TMCSR_CSL_DIV2;
66
+
67
+
writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
68
+
69
+
writel_relaxed(to->of_clk.period, timer_of_base(to) +
70
+
MLB_TMR_EVT_TMRLR1_OFS);
71
+
val |= MLB_TMR_TMCSR_RELD | MLB_TMR_TMCSR_CNTE |
72
+
MLB_TMR_TMCSR_TRG | MLB_TMR_TMCSR_INTE;
73
+
writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
74
+
return 0;
75
+
}
76
+
77
+
static int mlb_set_state_oneshot(struct clock_event_device *clk)
78
+
{
79
+
struct timer_of *to = to_timer_of(clk);
80
+
u32 val = MLB_TMR_TMCSR_CSL_DIV2;
81
+
82
+
writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
83
+
return 0;
84
+
}
85
+
86
+
static int mlb_clkevt_next_event(unsigned long event,
87
+
struct clock_event_device *clk)
88
+
{
89
+
struct timer_of *to = to_timer_of(clk);
90
+
91
+
writel_relaxed(event, timer_of_base(to) + MLB_TMR_EVT_TMRLR1_OFS);
92
+
writel_relaxed(MLB_TMR_TMCSR_CSL_DIV2 |
93
+
MLB_TMR_TMCSR_CNTE | MLB_TMR_TMCSR_INTE |
94
+
MLB_TMR_TMCSR_TRG, timer_of_base(to) +
95
+
MLB_TMR_EVT_TMCSR_OFS);
96
+
return 0;
97
+
}
98
+
99
+
static int mlb_config_clock_source(struct timer_of *to)
100
+
{
101
+
writel_relaxed(0, timer_of_base(to) + MLB_TMR_SRC_TMCSR_OFS);
102
+
writel_relaxed(~0, timer_of_base(to) + MLB_TMR_SRC_TMR_OFS);
103
+
writel_relaxed(~0, timer_of_base(to) + MLB_TMR_SRC_TMRLR1_OFS);
104
+
writel_relaxed(~0, timer_of_base(to) + MLB_TMR_SRC_TMRLR2_OFS);
105
+
writel_relaxed(BIT(4) | BIT(1) | BIT(0), timer_of_base(to) +
106
+
MLB_TMR_SRC_TMCSR_OFS);
107
+
return 0;
108
+
}
109
+
110
+
static int mlb_config_clock_event(struct timer_of *to)
111
+
{
112
+
writel_relaxed(0, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
113
+
return 0;
114
+
}
115
+
116
+
static struct timer_of to = {
117
+
.flags = TIMER_OF_IRQ | TIMER_OF_BASE | TIMER_OF_CLOCK,
118
+
119
+
.clkevt = {
120
+
.name = "mlb-clkevt",
121
+
.rating = MLB_TIMER_RATING,
122
+
.cpumask = cpu_possible_mask,
123
+
.features = CLOCK_EVT_FEAT_DYNIRQ | CLOCK_EVT_FEAT_ONESHOT,
124
+
.set_state_oneshot = mlb_set_state_oneshot,
125
+
.set_state_periodic = mlb_set_state_periodic,
126
+
.set_next_event = mlb_clkevt_next_event,
127
+
},
128
+
129
+
.of_irq = {
130
+
.flags = IRQF_TIMER | IRQF_IRQPOLL,
131
+
.handler = mlb_timer_interrupt,
132
+
},
133
+
};
134
+
135
+
static u64 notrace mlb_timer_sched_read(void)
136
+
{
137
+
return ~readl_relaxed(timer_of_base(&to) + MLB_TMR_SRC_TMR_OFS);
138
+
}
139
+
140
+
static int __init mlb_timer_init(struct device_node *node)
141
+
{
142
+
int ret;
143
+
unsigned long rate;
144
+
145
+
ret = timer_of_init(node, &to);
146
+
if (ret)
147
+
return ret;
148
+
149
+
rate = timer_of_rate(&to) / MLB_TMR_DIV_CNT;
150
+
mlb_config_clock_source(&to);
151
+
clocksource_mmio_init(timer_of_base(&to) + MLB_TMR_SRC_TMR_OFS,
152
+
node->name, rate, MLB_TIMER_RATING, 32,
153
+
clocksource_mmio_readl_down);
154
+
sched_clock_register(mlb_timer_sched_read, 32, rate);
155
+
mlb_config_clock_event(&to);
156
+
clockevents_config_and_register(&to.clkevt, timer_of_rate(&to), 15,
157
+
0xffffffff);
158
+
return 0;
159
+
}
160
+
TIMER_OF_DECLARE(mlb_peritimer, "socionext,milbeaut-timer",
161
+
mlb_timer_init);