tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

Merge branch 'for-v4.7/clk/exynos542x' into for-v4.7/clk/next

Sylwester Nawrocki 6466ee32 f6764714

+69 -30
+46 -29
drivers/clk/samsung/clk-exynos5420.c
··· 554 554 }; 555 555 556 556 static struct samsung_div_clock exynos5800_div_clks[] __initdata = { 557 - DIV(0, "dout_aclk400_wcore", "mout_aclk400_wcore", DIV_TOP0, 16, 3), 558 - 557 + DIV(CLK_DOUT_ACLK400_WCORE, "dout_aclk400_wcore", 558 + "mout_aclk400_wcore", DIV_TOP0, 16, 3), 559 559 DIV(0, "dout_aclk550_cam", "mout_aclk550_cam", 560 560 DIV_TOP8, 16, 3), 561 561 DIV(0, "dout_aclkfl1_550_cam", "mout_aclkfl1_550_cam", ··· 607 607 }; 608 608 609 609 static struct samsung_div_clock exynos5420_div_clks[] __initdata = { 610 - DIV(0, "dout_aclk400_wcore", "mout_aclk400_wcore_bpll", 611 - DIV_TOP0, 16, 3), 610 + DIV(CLK_DOUT_ACLK400_WCORE, "dout_aclk400_wcore", 611 + "mout_aclk400_wcore_bpll", DIV_TOP0, 16, 3), 612 612 }; 613 613 614 614 static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = { ··· 785 785 DIV(0, "div_kfc", "mout_kfc", DIV_KFC0, 0, 3), 786 786 DIV(0, "sclk_kpll", "mout_kpll", DIV_KFC0, 24, 3), 787 787 788 - DIV(0, "dout_aclk400_isp", "mout_aclk400_isp", DIV_TOP0, 0, 3), 789 - DIV(0, "dout_aclk400_mscl", "mout_aclk400_mscl", DIV_TOP0, 4, 3), 790 - DIV(0, "dout_aclk200", "mout_aclk200", DIV_TOP0, 8, 3), 791 - DIV(0, "dout_aclk200_fsys2", "mout_aclk200_fsys2", DIV_TOP0, 12, 3), 792 - DIV(0, "dout_aclk100_noc", "mout_aclk100_noc", DIV_TOP0, 20, 3), 793 - DIV(0, "dout_pclk200_fsys", "mout_pclk200_fsys", DIV_TOP0, 24, 3), 794 - DIV(0, "dout_aclk200_fsys", "mout_aclk200_fsys", DIV_TOP0, 28, 3), 788 + DIV(CLK_DOUT_ACLK400_ISP, "dout_aclk400_isp", "mout_aclk400_isp", 789 + DIV_TOP0, 0, 3), 790 + DIV(CLK_DOUT_ACLK400_MSCL, "dout_aclk400_mscl", "mout_aclk400_mscl", 791 + DIV_TOP0, 4, 3), 792 + DIV(CLK_DOUT_ACLK200, "dout_aclk200", "mout_aclk200", 793 + DIV_TOP0, 8, 3), 794 + DIV(CLK_DOUT_ACLK200_FSYS2, "dout_aclk200_fsys2", "mout_aclk200_fsys2", 795 + DIV_TOP0, 12, 3), 796 + DIV(CLK_DOUT_ACLK100_NOC, "dout_aclk100_noc", "mout_aclk100_noc", 797 + DIV_TOP0, 20, 3), 798 + DIV(CLK_DOUT_PCLK200_FSYS, "dout_pclk200_fsys", "mout_pclk200_fsys", 799 + DIV_TOP0, 24, 3), 800 + DIV(CLK_DOUT_ACLK200_FSYS, "dout_aclk200_fsys", "mout_aclk200_fsys", 801 + DIV_TOP0, 28, 3), 802 + DIV(CLK_DOUT_ACLK333_432_GSCL, "dout_aclk333_432_gscl", 803 + "mout_aclk333_432_gscl", DIV_TOP1, 0, 3), 804 + DIV(CLK_DOUT_ACLK333_432_ISP, "dout_aclk333_432_isp", 805 + "mout_aclk333_432_isp", DIV_TOP1, 4, 3), 806 + DIV(CLK_DOUT_ACLK66, "dout_aclk66", "mout_aclk66", 807 + DIV_TOP1, 8, 6), 808 + DIV(CLK_DOUT_ACLK333_432_ISP0, "dout_aclk333_432_isp0", 809 + "mout_aclk333_432_isp0", DIV_TOP1, 16, 3), 810 + DIV(CLK_DOUT_ACLK266, "dout_aclk266", "mout_aclk266", 811 + DIV_TOP1, 20, 3), 812 + DIV(CLK_DOUT_ACLK166, "dout_aclk166", "mout_aclk166", 813 + DIV_TOP1, 24, 3), 814 + DIV(CLK_DOUT_ACLK333, "dout_aclk333", "mout_aclk333", 815 + DIV_TOP1, 28, 3), 795 816 796 - DIV(0, "dout_aclk333_432_gscl", "mout_aclk333_432_gscl", 797 - DIV_TOP1, 0, 3), 798 - DIV(0, "dout_aclk333_432_isp", "mout_aclk333_432_isp", 799 - DIV_TOP1, 4, 3), 800 - DIV(0, "dout_aclk66", "mout_aclk66", DIV_TOP1, 8, 6), 801 - DIV(0, "dout_aclk333_432_isp0", "mout_aclk333_432_isp0", 802 - DIV_TOP1, 16, 3), 803 - DIV(0, "dout_aclk266", "mout_aclk266", DIV_TOP1, 20, 3), 804 - DIV(0, "dout_aclk166", "mout_aclk166", DIV_TOP1, 24, 3), 805 - DIV(0, "dout_aclk333", "mout_aclk333", DIV_TOP1, 28, 3), 806 - 807 - DIV(0, "dout_aclk333_g2d", "mout_aclk333_g2d", DIV_TOP2, 8, 3), 808 - DIV(0, "dout_aclk266_g2d", "mout_aclk266_g2d", DIV_TOP2, 12, 3), 809 - DIV(0, "dout_aclk_g3d", "mout_aclk_g3d", DIV_TOP2, 16, 3), 810 - DIV(0, "dout_aclk300_jpeg", "mout_aclk300_jpeg", DIV_TOP2, 20, 3), 811 - DIV(0, "dout_aclk300_disp1", "mout_aclk300_disp1", DIV_TOP2, 24, 3), 812 - DIV(0, "dout_aclk300_gscl", "mout_aclk300_gscl", DIV_TOP2, 28, 3), 817 + DIV(CLK_DOUT_ACLK333_G2D, "dout_aclk333_g2d", "mout_aclk333_g2d", 818 + DIV_TOP2, 8, 3), 819 + DIV(CLK_DOUT_ACLK266_G2D, "dout_aclk266_g2d", "mout_aclk266_g2d", 820 + DIV_TOP2, 12, 3), 821 + DIV(CLK_DOUT_ACLK_G3D, "dout_aclk_g3d", "mout_aclk_g3d", DIV_TOP2, 822 + 16, 3), 823 + DIV(CLK_DOUT_ACLK300_JPEG, "dout_aclk300_jpeg", "mout_aclk300_jpeg", 824 + DIV_TOP2, 20, 3), 825 + DIV(CLK_DOUT_ACLK300_DISP1, "dout_aclk300_disp1", 826 + "mout_aclk300_disp1", DIV_TOP2, 24, 3), 827 + DIV(CLK_DOUT_ACLK300_GSCL, "dout_aclk300_gscl", "mout_aclk300_gscl", 828 + DIV_TOP2, 28, 3), 813 829 814 830 /* DISP1 Block */ 815 831 DIV(0, "dout_fimd1", "mout_fimd1_final", DIV_DISP10, 0, 4), ··· 833 817 DIV(0, "dout_dp1", "mout_dp1", DIV_DISP10, 24, 4), 834 818 DIV(CLK_DOUT_PIXEL, "dout_hdmi_pixel", "mout_pixel", DIV_DISP10, 28, 4), 835 819 DIV(0, "dout_disp1_blk", "aclk200_disp1", DIV2_RATIO0, 16, 2), 836 - DIV(0, "dout_aclk400_disp1", "mout_aclk400_disp1", DIV_TOP2, 4, 3), 820 + DIV(CLK_DOUT_ACLK400_DISP1, "dout_aclk400_disp1", 821 + "mout_aclk400_disp1", DIV_TOP2, 4, 3), 837 822 838 823 /* Audio Block */ 839 824 DIV(0, "dout_maudio0", "mout_maudio0", DIV_MAU, 20, 4),
+23 -1
include/dt-bindings/clock/exynos5420.h
··· 217 217 218 218 /* divider clocks */ 219 219 #define CLK_DOUT_PIXEL 768 220 + #define CLK_DOUT_ACLK400_WCORE 769 221 + #define CLK_DOUT_ACLK400_ISP 770 222 + #define CLK_DOUT_ACLK400_MSCL 771 223 + #define CLK_DOUT_ACLK200 772 224 + #define CLK_DOUT_ACLK200_FSYS2 773 225 + #define CLK_DOUT_ACLK100_NOC 774 226 + #define CLK_DOUT_PCLK200_FSYS 775 227 + #define CLK_DOUT_ACLK200_FSYS 776 228 + #define CLK_DOUT_ACLK333_432_GSCL 777 229 + #define CLK_DOUT_ACLK333_432_ISP 778 230 + #define CLK_DOUT_ACLK66 779 231 + #define CLK_DOUT_ACLK333_432_ISP0 780 232 + #define CLK_DOUT_ACLK266 781 233 + #define CLK_DOUT_ACLK166 782 234 + #define CLK_DOUT_ACLK333 783 235 + #define CLK_DOUT_ACLK333_G2D 784 236 + #define CLK_DOUT_ACLK266_G2D 785 237 + #define CLK_DOUT_ACLK_G3D 786 238 + #define CLK_DOUT_ACLK300_JPEG 787 239 + #define CLK_DOUT_ACLK300_DISP1 788 240 + #define CLK_DOUT_ACLK300_GSCL 789 241 + #define CLK_DOUT_ACLK400_DISP1 790 220 242 221 243 /* must be greater than maximal clock id */ 222 - #define CLK_NR_CLKS 769 244 + #define CLK_NR_CLKS 791 223 245 224 246 #endif /* _DT_BINDINGS_CLOCK_EXYNOS_5420_H */