drm/amd/amdgpu: consolidate PSP TA context

+8 -8

drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c

··· 341 341 switch (query_fw->index) { 342 342 case TA_FW_TYPE_PSP_XGMI: 343 343 fw_info->ver = adev->psp.ta_fw_version; 344 - fw_info->feature = adev->psp.ta_xgmi_ucode_version; 344 + fw_info->feature = adev->psp.xgmi.feature_version; 345 345 break; 346 346 case TA_FW_TYPE_PSP_RAS: 347 347 fw_info->ver = adev->psp.ta_fw_version; 348 - fw_info->feature = adev->psp.ta_ras_ucode_version; 348 + fw_info->feature = adev->psp.ras.feature_version; 349 349 break; 350 350 case TA_FW_TYPE_PSP_HDCP: 351 351 fw_info->ver = adev->psp.ta_fw_version; 352 - fw_info->feature = adev->psp.ta_hdcp_ucode_version; 352 + fw_info->feature = adev->psp.hdcp.feature_version; 353 353 break; 354 354 case TA_FW_TYPE_PSP_DTM: 355 355 fw_info->ver = adev->psp.ta_fw_version; 356 - fw_info->feature = adev->psp.ta_dtm_ucode_version; 356 + fw_info->feature = adev->psp.dtm.feature_version; 357 357 break; 358 358 case TA_FW_TYPE_PSP_RAP: 359 359 fw_info->ver = adev->psp.ta_fw_version; 360 - fw_info->feature = adev->psp.ta_rap_ucode_version; 360 + fw_info->feature = adev->psp.rap.feature_version; 361 361 break; 362 362 case TA_FW_TYPE_PSP_SECUREDISPLAY: 363 363 fw_info->ver = adev->psp.ta_fw_version; 364 - fw_info->feature = adev->psp.ta_securedisplay_ucode_version; 364 + fw_info->feature = adev->psp.securedisplay.feature_version; 365 365 break; 366 366 default: 367 367 return -EINVAL; ··· 378 378 fw_info->feature = adev->psp.sos.feature_version; 379 379 break; 380 380 case AMDGPU_INFO_FW_ASD: 381 - fw_info->ver = adev->psp.asd_fw_version; 382 - fw_info->feature = adev->psp.asd_feature_version; 381 + fw_info->ver = adev->psp.asd.fw_version; 382 + fw_info->feature = adev->psp.asd.feature_version; 383 383 break; 384 384 case AMDGPU_INFO_FW_DMCU: 385 385 fw_info->ver = adev->dm.dmcu_fw_version;

+81 -81

drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

··· 799 799 * add workaround to bypass it for sriov now. 800 800 * TODO: add version check to make it common 801 801 */ 802 - if (amdgpu_sriov_vf(psp->adev) || !psp->asd_ucode_size) 802 + if (amdgpu_sriov_vf(psp->adev) || !psp->asd.size_bytes) 803 803 return 0; 804 804 805 805 cmd = acquire_psp_cmd_buf(psp); 806 806 807 - psp_copy_fw(psp, psp->asd_start_addr, psp->asd_ucode_size); 807 + psp_copy_fw(psp, psp->asd.start_addr, psp->asd.size_bytes); 808 808 809 809 psp_prep_asd_load_cmd_buf(cmd, psp->fw_pri_mc_addr, 810 - psp->asd_ucode_size); 810 + psp->asd.size_bytes); 811 811 812 812 ret = psp_cmd_submit_buf(psp, NULL, cmd, 813 813 psp->fence_buf_mc_addr); ··· 952 952 953 953 cmd = acquire_psp_cmd_buf(psp); 954 954 955 - psp_copy_fw(psp, psp->ta_xgmi_start_addr, psp->ta_xgmi_ucode_size); 955 + psp_copy_fw(psp, psp->xgmi.start_addr, psp->xgmi.size_bytes); 956 956 957 957 psp_prep_ta_load_cmd_buf(cmd, 958 958 psp->fw_pri_mc_addr, 959 - psp->ta_xgmi_ucode_size, 959 + psp->xgmi.size_bytes, 960 960 psp->xgmi_context.xgmi_shared_mc_addr, 961 961 PSP_XGMI_SHARED_MEM_SIZE); 962 962 ··· 1031 1031 struct ta_xgmi_shared_memory *xgmi_cmd; 1032 1032 int ret; 1033 1033 1034 - if (!psp->adev->psp.ta_fw || 1035 - !psp->adev->psp.ta_xgmi_ucode_size || 1036 - !psp->adev->psp.ta_xgmi_start_addr) 1034 + if (!psp->ta_fw || 1035 + !psp->xgmi.size_bytes || 1036 + !psp->xgmi.start_addr) 1037 1037 return -ENOENT; 1038 1038 1039 1039 if (!psp->xgmi_context.initialized) { ··· 1100 1100 static bool psp_xgmi_peer_link_info_supported(struct psp_context *psp) 1101 1101 { 1102 1102 return psp->adev->asic_type == CHIP_ALDEBARAN && 1103 - psp->ta_xgmi_ucode_version >= 0x2000000b; 1103 + psp->xgmi.feature_version >= 0x2000000b; 1104 1104 } 1105 1105 1106 1106 int psp_xgmi_get_topology_info(struct psp_context *psp, ··· 1206 1206 */ 1207 1207 ret = amdgpu_bo_create_kernel(psp->adev, PSP_RAS_SHARED_MEM_SIZE, 1208 1208 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 1209 - &psp->ras.ras_shared_bo, 1210 - &psp->ras.ras_shared_mc_addr, 1211 - &psp->ras.ras_shared_buf); 1209 + &psp->ras_context.ras_shared_bo, 1210 + &psp->ras_context.ras_shared_mc_addr, 1211 + &psp->ras_context.ras_shared_buf); 1212 1212 1213 1213 return ret; 1214 1214 } ··· 1225 1225 if (amdgpu_sriov_vf(psp->adev)) 1226 1226 return 0; 1227 1227 1228 - psp_copy_fw(psp, psp->ta_ras_start_addr, psp->ta_ras_ucode_size); 1228 + psp_copy_fw(psp, psp->ras.start_addr, psp->ras.size_bytes); 1229 1229 1230 - ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf; 1230 + ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.ras_shared_buf; 1231 1231 1232 1232 if (psp->adev->gmc.xgmi.connected_to_cpu) 1233 1233 ras_cmd->ras_in_message.init_flags.poison_mode_en = 1; ··· 1238 1238 1239 1239 psp_prep_ta_load_cmd_buf(cmd, 1240 1240 psp->fw_pri_mc_addr, 1241 - psp->ta_ras_ucode_size, 1242 - psp->ras.ras_shared_mc_addr, 1241 + psp->ras.size_bytes, 1242 + psp->ras_context.ras_shared_mc_addr, 1243 1243 PSP_RAS_SHARED_MEM_SIZE); 1244 1244 1245 1245 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1246 1246 psp->fence_buf_mc_addr); 1247 1247 1248 1248 if (!ret) { 1249 - psp->ras.session_id = cmd->resp.session_id; 1249 + psp->ras_context.session_id = cmd->resp.session_id; 1250 1250 1251 1251 if (!ras_cmd->ras_status) 1252 - psp->ras.ras_initialized = true; 1252 + psp->ras_context.ras_initialized = true; 1253 1253 else 1254 1254 dev_warn(psp->adev->dev, "RAS Init Status: 0x%X\n", ras_cmd->ras_status); 1255 1255 } ··· 1275 1275 1276 1276 cmd = acquire_psp_cmd_buf(psp); 1277 1277 1278 - psp_prep_ta_unload_cmd_buf(cmd, psp->ras.session_id); 1278 + psp_prep_ta_unload_cmd_buf(cmd, psp->ras_context.session_id); 1279 1279 1280 1280 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1281 1281 psp->fence_buf_mc_addr); ··· 1290 1290 struct ta_ras_shared_memory *ras_cmd; 1291 1291 int ret; 1292 1292 1293 - ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf; 1293 + ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.ras_shared_buf; 1294 1294 1295 1295 /* 1296 1296 * TODO: bypass the loading in sriov for now ··· 1298 1298 if (amdgpu_sriov_vf(psp->adev)) 1299 1299 return 0; 1300 1300 1301 - ret = psp_ta_invoke(psp, ta_cmd_id, psp->ras.session_id); 1301 + ret = psp_ta_invoke(psp, ta_cmd_id, psp->ras_context.session_id); 1302 1302 1303 1303 if (amdgpu_ras_intr_triggered()) 1304 1304 return ret; ··· 1354 1354 struct ta_ras_shared_memory *ras_cmd; 1355 1355 int ret; 1356 1356 1357 - if (!psp->ras.ras_initialized) 1357 + if (!psp->ras_context.ras_initialized) 1358 1358 return -EINVAL; 1359 1359 1360 - ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf; 1360 + ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.ras_shared_buf; 1361 1361 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1362 1362 1363 1363 if (enable) ··· 1384 1384 if (amdgpu_sriov_vf(psp->adev)) 1385 1385 return 0; 1386 1386 1387 - if (!psp->ras.ras_initialized) 1387 + if (!psp->ras_context.ras_initialized) 1388 1388 return 0; 1389 1389 1390 1390 ret = psp_ras_unload(psp); 1391 1391 if (ret) 1392 1392 return ret; 1393 1393 1394 - psp->ras.ras_initialized = false; 1394 + psp->ras_context.ras_initialized = false; 1395 1395 1396 1396 /* free ras shared memory */ 1397 - amdgpu_bo_free_kernel(&psp->ras.ras_shared_bo, 1398 - &psp->ras.ras_shared_mc_addr, 1399 - &psp->ras.ras_shared_buf); 1397 + amdgpu_bo_free_kernel(&psp->ras_context.ras_shared_bo, 1398 + &psp->ras_context.ras_shared_mc_addr, 1399 + &psp->ras_context.ras_shared_buf); 1400 1400 1401 1401 return 0; 1402 1402 } ··· 1413 1413 if (amdgpu_sriov_vf(adev)) 1414 1414 return 0; 1415 1415 1416 - if (!adev->psp.ta_ras_ucode_size || 1417 - !adev->psp.ta_ras_start_addr) { 1416 + if (!adev->psp.ras.size_bytes || 1417 + !adev->psp.ras.start_addr) { 1418 1418 dev_info(adev->dev, "RAS: optional ras ta ucode is not available\n"); 1419 1419 return 0; 1420 1420 } ··· 1460 1460 } 1461 1461 } 1462 1462 1463 - if (!psp->ras.ras_initialized) { 1463 + if (!psp->ras_context.ras_initialized) { 1464 1464 ret = psp_ras_init_shared_buf(psp); 1465 1465 if (ret) 1466 1466 return ret; ··· 1479 1479 struct ta_ras_shared_memory *ras_cmd; 1480 1480 int ret; 1481 1481 1482 - if (!psp->ras.ras_initialized) 1482 + if (!psp->ras_context.ras_initialized) 1483 1483 return -EINVAL; 1484 1484 1485 - ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf; 1485 + ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.ras_shared_buf; 1486 1486 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1487 1487 1488 1488 ras_cmd->cmd_id = TA_RAS_COMMAND__TRIGGER_ERROR; ··· 1530 1530 if (amdgpu_sriov_vf(psp->adev)) 1531 1531 return 0; 1532 1532 1533 - psp_copy_fw(psp, psp->ta_hdcp_start_addr, 1534 - psp->ta_hdcp_ucode_size); 1533 + psp_copy_fw(psp, psp->hdcp.start_addr, 1534 + psp->hdcp.size_bytes); 1535 1535 1536 1536 cmd = acquire_psp_cmd_buf(psp); 1537 1537 1538 1538 psp_prep_ta_load_cmd_buf(cmd, 1539 1539 psp->fw_pri_mc_addr, 1540 - psp->ta_hdcp_ucode_size, 1540 + psp->hdcp.size_bytes, 1541 1541 psp->hdcp_context.hdcp_shared_mc_addr, 1542 1542 PSP_HDCP_SHARED_MEM_SIZE); 1543 1543 ··· 1563 1563 if (amdgpu_sriov_vf(psp->adev)) 1564 1564 return 0; 1565 1565 1566 - if (!psp->adev->psp.ta_hdcp_ucode_size || 1567 - !psp->adev->psp.ta_hdcp_start_addr) { 1566 + if (!psp->hdcp.size_bytes || 1567 + !psp->hdcp.start_addr) { 1568 1568 dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not available\n"); 1569 1569 return 0; 1570 1570 } ··· 1677 1677 if (amdgpu_sriov_vf(psp->adev)) 1678 1678 return 0; 1679 1679 1680 - psp_copy_fw(psp, psp->ta_dtm_start_addr, psp->ta_dtm_ucode_size); 1680 + psp_copy_fw(psp, psp->dtm.start_addr, psp->dtm.size_bytes); 1681 1681 1682 1682 cmd = acquire_psp_cmd_buf(psp); 1683 1683 1684 1684 psp_prep_ta_load_cmd_buf(cmd, 1685 1685 psp->fw_pri_mc_addr, 1686 - psp->ta_dtm_ucode_size, 1686 + psp->dtm.size_bytes, 1687 1687 psp->dtm_context.dtm_shared_mc_addr, 1688 1688 PSP_DTM_SHARED_MEM_SIZE); 1689 1689 ··· 1710 1710 if (amdgpu_sriov_vf(psp->adev)) 1711 1711 return 0; 1712 1712 1713 - if (!psp->adev->psp.ta_dtm_ucode_size || 1714 - !psp->adev->psp.ta_dtm_start_addr) { 1713 + if (!psp->dtm.size_bytes || 1714 + !psp->dtm.start_addr) { 1715 1715 dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not available\n"); 1716 1716 return 0; 1717 1717 } ··· 1818 1818 int ret; 1819 1819 struct psp_gfx_cmd_resp *cmd; 1820 1820 1821 - psp_copy_fw(psp, psp->ta_rap_start_addr, psp->ta_rap_ucode_size); 1821 + psp_copy_fw(psp, psp->rap.start_addr, psp->rap.size_bytes); 1822 1822 1823 1823 cmd = acquire_psp_cmd_buf(psp); 1824 1824 1825 1825 psp_prep_ta_load_cmd_buf(cmd, 1826 1826 psp->fw_pri_mc_addr, 1827 - psp->ta_rap_ucode_size, 1827 + psp->rap.size_bytes, 1828 1828 psp->rap_context.rap_shared_mc_addr, 1829 1829 PSP_RAP_SHARED_MEM_SIZE); 1830 1830 ··· 1866 1866 if (amdgpu_sriov_vf(psp->adev)) 1867 1867 return 0; 1868 1868 1869 - if (!psp->adev->psp.ta_rap_ucode_size || 1870 - !psp->adev->psp.ta_rap_start_addr) { 1869 + if (!psp->rap.size_bytes || 1870 + !psp->rap.start_addr) { 1871 1871 dev_info(psp->adev->dev, "RAP: optional rap ta ucode is not available\n"); 1872 1872 return 0; 1873 1873 } ··· 1979 1979 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 1980 1980 1981 1981 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 1982 - memcpy(psp->fw_pri_buf, psp->ta_securedisplay_start_addr, psp->ta_securedisplay_ucode_size); 1982 + memcpy(psp->fw_pri_buf, psp->securedisplay.start_addr, psp->securedisplay.size_bytes); 1983 1983 1984 1984 psp_prep_ta_load_cmd_buf(cmd, 1985 1985 psp->fw_pri_mc_addr, 1986 - psp->ta_securedisplay_ucode_size, 1986 + psp->securedisplay.size_bytes, 1987 1987 psp->securedisplay_context.securedisplay_shared_mc_addr, 1988 1988 PSP_SECUREDISPLAY_SHARED_MEM_SIZE); 1989 1989 ··· 2025 2025 if (amdgpu_sriov_vf(psp->adev)) 2026 2026 return 0; 2027 2027 2028 - if (!psp->adev->psp.ta_securedisplay_ucode_size || 2029 - !psp->adev->psp.ta_securedisplay_start_addr) { 2028 + if (!psp->securedisplay.size_bytes || 2029 + !psp->securedisplay.start_addr) { 2030 2030 dev_info(psp->adev->dev, "SECUREDISPLAY: securedisplay ta ucode is not available\n"); 2031 2031 return 0; 2032 2032 } ··· 2420 2420 struct amdgpu_device *adev = psp->adev; 2421 2421 struct amdgpu_firmware_info *ucode = 2422 2422 &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC]; 2423 - struct amdgpu_ras *ras = psp->ras.ras; 2423 + struct amdgpu_ras *ras = psp->ras_context.ras; 2424 2424 2425 2425 if (!ucode->fw || amdgpu_sriov_vf(psp->adev)) 2426 2426 return 0; ··· 2625 2625 return ret; 2626 2626 } 2627 2627 2628 - if (psp->adev->psp.ta_fw) { 2628 + if (psp->ta_fw) { 2629 2629 ret = psp_ras_initialize(psp); 2630 2630 if (ret) 2631 2631 dev_err(psp->adev->dev, ··· 2697 2697 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2698 2698 struct psp_context *psp = &adev->psp; 2699 2699 2700 - if (psp->adev->psp.ta_fw) { 2700 + if (psp->ta_fw) { 2701 2701 psp_ras_terminate(psp); 2702 2702 psp_securedisplay_terminate(psp); 2703 2703 psp_rap_terminate(psp); ··· 2735 2735 } 2736 2736 } 2737 2737 2738 - if (psp->adev->psp.ta_fw) { 2738 + if (psp->ta_fw) { 2739 2739 ret = psp_ras_terminate(psp); 2740 2740 if (ret) { 2741 2741 DRM_ERROR("Failed to terminate ras ta\n"); ··· 2826 2826 "XGMI: Failed to initialize XGMI session\n"); 2827 2827 } 2828 2828 2829 - if (psp->adev->psp.ta_fw) { 2829 + if (psp->ta_fw) { 2830 2830 ret = psp_ras_initialize(psp); 2831 2831 if (ret) 2832 2832 dev_err(psp->adev->dev, ··· 2978 2978 goto out; 2979 2979 2980 2980 asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data; 2981 - adev->psp.asd_fw_version = le32_to_cpu(asd_hdr->header.ucode_version); 2982 - adev->psp.asd_feature_version = le32_to_cpu(asd_hdr->sos.fw_version); 2983 - adev->psp.asd_ucode_size = le32_to_cpu(asd_hdr->header.ucode_size_bytes); 2984 - adev->psp.asd_start_addr = (uint8_t *)asd_hdr + 2981 + adev->psp.asd.fw_version = le32_to_cpu(asd_hdr->header.ucode_version); 2982 + adev->psp.asd.feature_version = le32_to_cpu(asd_hdr->sos.fw_version); 2983 + adev->psp.asd.size_bytes = le32_to_cpu(asd_hdr->header.ucode_size_bytes); 2984 + adev->psp.asd.start_addr = (uint8_t *)asd_hdr + 2985 2985 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes); 2986 2986 return 0; 2987 2987 out: ··· 3266 3266 3267 3267 switch (desc->fw_type) { 3268 3268 case TA_FW_TYPE_PSP_ASD: 3269 - psp->asd_fw_version = le32_to_cpu(desc->fw_version); 3270 - psp->asd_feature_version = le32_to_cpu(desc->fw_version); 3271 - psp->asd_ucode_size = le32_to_cpu(desc->size_bytes); 3272 - psp->asd_start_addr = ucode_start_addr; 3269 + psp->asd.fw_version = le32_to_cpu(desc->fw_version); 3270 + psp->asd.feature_version = le32_to_cpu(desc->fw_version); 3271 + psp->asd.size_bytes = le32_to_cpu(desc->size_bytes); 3272 + psp->asd.start_addr = ucode_start_addr; 3273 3273 break; 3274 3274 case TA_FW_TYPE_PSP_XGMI: 3275 - psp->ta_xgmi_ucode_version = le32_to_cpu(desc->fw_version); 3276 - psp->ta_xgmi_ucode_size = le32_to_cpu(desc->size_bytes); 3277 - psp->ta_xgmi_start_addr = ucode_start_addr; 3275 + psp->xgmi.feature_version = le32_to_cpu(desc->fw_version); 3276 + psp->xgmi.size_bytes = le32_to_cpu(desc->size_bytes); 3277 + psp->xgmi.start_addr = ucode_start_addr; 3278 3278 break; 3279 3279 case TA_FW_TYPE_PSP_RAS: 3280 - psp->ta_ras_ucode_version = le32_to_cpu(desc->fw_version); 3281 - psp->ta_ras_ucode_size = le32_to_cpu(desc->size_bytes); 3282 - psp->ta_ras_start_addr = ucode_start_addr; 3280 + psp->ras.feature_version = le32_to_cpu(desc->fw_version); 3281 + psp->ras.size_bytes = le32_to_cpu(desc->size_bytes); 3282 + psp->ras.start_addr = ucode_start_addr; 3283 3283 break; 3284 3284 case TA_FW_TYPE_PSP_HDCP: 3285 - psp->ta_hdcp_ucode_version = le32_to_cpu(desc->fw_version); 3286 - psp->ta_hdcp_ucode_size = le32_to_cpu(desc->size_bytes); 3287 - psp->ta_hdcp_start_addr = ucode_start_addr; 3285 + psp->hdcp.feature_version = le32_to_cpu(desc->fw_version); 3286 + psp->hdcp.size_bytes = le32_to_cpu(desc->size_bytes); 3287 + psp->hdcp.start_addr = ucode_start_addr; 3288 3288 break; 3289 3289 case TA_FW_TYPE_PSP_DTM: 3290 - psp->ta_dtm_ucode_version = le32_to_cpu(desc->fw_version); 3291 - psp->ta_dtm_ucode_size = le32_to_cpu(desc->size_bytes); 3292 - psp->ta_dtm_start_addr = ucode_start_addr; 3290 + psp->dtm.feature_version = le32_to_cpu(desc->fw_version); 3291 + psp->dtm.size_bytes = le32_to_cpu(desc->size_bytes); 3292 + psp->dtm.start_addr = ucode_start_addr; 3293 3293 break; 3294 3294 case TA_FW_TYPE_PSP_RAP: 3295 - psp->ta_rap_ucode_version = le32_to_cpu(desc->fw_version); 3296 - psp->ta_rap_ucode_size = le32_to_cpu(desc->size_bytes); 3297 - psp->ta_rap_start_addr = ucode_start_addr; 3295 + psp->rap.feature_version = le32_to_cpu(desc->fw_version); 3296 + psp->rap.size_bytes = le32_to_cpu(desc->size_bytes); 3297 + psp->rap.start_addr = ucode_start_addr; 3298 3298 break; 3299 3299 case TA_FW_TYPE_PSP_SECUREDISPLAY: 3300 - psp->ta_securedisplay_ucode_version = le32_to_cpu(desc->fw_version); 3301 - psp->ta_securedisplay_ucode_size = le32_to_cpu(desc->size_bytes); 3302 - psp->ta_securedisplay_start_addr = ucode_start_addr; 3300 + psp->securedisplay.feature_version = le32_to_cpu(desc->fw_version); 3301 + psp->securedisplay.size_bytes = le32_to_cpu(desc->size_bytes); 3302 + psp->securedisplay.start_addr = ucode_start_addr; 3303 3303 break; 3304 3304 default: 3305 3305 dev_warn(psp->adev->dev, "Unsupported TA type: %d\n", desc->fw_type);

+9 -28

drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h

··· 327 327 uint64_t tmr_mc_addr; 328 328 329 329 /* asd firmware */ 330 - const struct firmware *asd_fw; 331 - uint32_t asd_fw_version; 332 - uint32_t asd_feature_version; 333 - uint32_t asd_ucode_size; 334 - uint8_t *asd_start_addr; 330 + const struct firmware *asd_fw; 331 + struct psp_bin_desc asd; 335 332 336 333 /* toc firmware */ 337 334 const struct firmware *toc_fw; ··· 353 356 /* xgmi ta firmware and buffer */ 354 357 const struct firmware *ta_fw; 355 358 uint32_t ta_fw_version; 356 - uint32_t ta_xgmi_ucode_version; 357 - uint32_t ta_xgmi_ucode_size; 358 - uint8_t *ta_xgmi_start_addr; 359 - uint32_t ta_ras_ucode_version; 360 - uint32_t ta_ras_ucode_size; 361 - uint8_t *ta_ras_start_addr; 362 - 363 - uint32_t ta_hdcp_ucode_version; 364 - uint32_t ta_hdcp_ucode_size; 365 - uint8_t *ta_hdcp_start_addr; 366 - 367 - uint32_t ta_dtm_ucode_version; 368 - uint32_t ta_dtm_ucode_size; 369 - uint8_t *ta_dtm_start_addr; 370 - 371 - uint32_t ta_rap_ucode_version; 372 - uint32_t ta_rap_ucode_size; 373 - uint8_t *ta_rap_start_addr; 374 - 375 - uint32_t ta_securedisplay_ucode_version; 376 - uint32_t ta_securedisplay_ucode_size; 377 - uint8_t *ta_securedisplay_start_addr; 359 + struct psp_bin_desc xgmi; 360 + struct psp_bin_desc ras; 361 + struct psp_bin_desc hdcp; 362 + struct psp_bin_desc dtm; 363 + struct psp_bin_desc rap; 364 + struct psp_bin_desc securedisplay; 378 365 379 366 struct psp_asd_context asd_context; 380 367 struct psp_xgmi_context xgmi_context; 381 - struct psp_ras_context ras; 368 + struct psp_ras_context ras_context; 382 369 struct psp_hdcp_context hdcp_context; 383 370 struct psp_dtm_context dtm_context; 384 371 struct psp_rap_context rap_context;

+1 -1

drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c

··· 1866 1866 static int amdgpu_ras_load_bad_pages(struct amdgpu_device *adev) 1867 1867 { 1868 1868 struct amdgpu_ras_eeprom_control *control = 1869 - &adev->psp.ras.ras->eeprom_control; 1869 + &adev->psp.ras_context.ras->eeprom_control; 1870 1870 struct eeprom_table_record *bps; 1871 1871 int ret; 1872 1872

+2 -2

drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h

··· 470 470 * 8: feature disable 471 471 */ 472 472 473 - #define amdgpu_ras_get_context(adev) ((adev)->psp.ras.ras) 474 - #define amdgpu_ras_set_context(adev, ras_con) ((adev)->psp.ras.ras = (ras_con)) 473 + #define amdgpu_ras_get_context(adev) ((adev)->psp.ras_context.ras) 474 + #define amdgpu_ras_set_context(adev, ras_con) ((adev)->psp.ras_context.ras = (ras_con)) 475 475 476 476 /* check if ras is supported on block, say, sdma, gfx */ 477 477 static inline int amdgpu_ras_is_supported(struct amdgpu_device *adev,

+3 -3

drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c

··· 525 525 FW_VERSION_ATTR(mec_fw_version, 0444, gfx.mec_fw_version); 526 526 FW_VERSION_ATTR(mec2_fw_version, 0444, gfx.mec2_fw_version); 527 527 FW_VERSION_ATTR(sos_fw_version, 0444, psp.sos.fw_version); 528 - FW_VERSION_ATTR(asd_fw_version, 0444, psp.asd_fw_version); 529 - FW_VERSION_ATTR(ta_ras_fw_version, 0444, psp.ta_ras_ucode_version); 530 - FW_VERSION_ATTR(ta_xgmi_fw_version, 0444, psp.ta_xgmi_ucode_version); 528 + FW_VERSION_ATTR(asd_fw_version, 0444, psp.asd.fw_version); 529 + FW_VERSION_ATTR(ta_ras_fw_version, 0444, psp.ras.feature_version); 530 + FW_VERSION_ATTR(ta_xgmi_fw_version, 0444, psp.xgmi.feature_version); 531 531 FW_VERSION_ATTR(smc_fw_version, 0444, pm.fw_version); 532 532 FW_VERSION_ATTR(sdma_fw_version, 0444, sdma.instance[0].fw_version); 533 533 FW_VERSION_ATTR(sdma2_fw_version, 0444, sdma.instance[1].fw_version);

+5 -15

drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h

··· 136 136 /* version_major=1, version_minor=0 */ 137 137 struct ta_firmware_header_v1_0 { 138 138 struct common_firmware_header header; 139 - uint32_t ta_xgmi_ucode_version; 140 - uint32_t ta_xgmi_offset_bytes; 141 - uint32_t ta_xgmi_size_bytes; 142 - uint32_t ta_ras_ucode_version; 143 - uint32_t ta_ras_offset_bytes; 144 - uint32_t ta_ras_size_bytes; 145 - uint32_t ta_hdcp_ucode_version; 146 - uint32_t ta_hdcp_offset_bytes; 147 - uint32_t ta_hdcp_size_bytes; 148 - uint32_t ta_dtm_ucode_version; 149 - uint32_t ta_dtm_offset_bytes; 150 - uint32_t ta_dtm_size_bytes; 151 - uint32_t ta_securedisplay_ucode_version; 152 - uint32_t ta_securedisplay_offset_bytes; 153 - uint32_t ta_securedisplay_size_bytes; 139 + struct psp_fw_legacy_bin_desc xgmi; 140 + struct psp_fw_legacy_bin_desc ras; 141 + struct psp_fw_legacy_bin_desc hdcp; 142 + struct psp_fw_legacy_bin_desc dtm; 143 + struct psp_fw_legacy_bin_desc securedisplay; 154 144 }; 155 145 156 146 enum ta_fw_type {

+3 -3

drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c

··· 532 532 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_MEC, adev->gfx.mec_fw_version); 533 533 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_MEC2, adev->gfx.mec2_fw_version); 534 534 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_SOS, adev->psp.sos.fw_version); 535 - POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_ASD, adev->psp.asd_fw_version); 536 - POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_TA_RAS, adev->psp.ta_ras_ucode_version); 537 - POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_TA_XGMI, adev->psp.ta_xgmi_ucode_version); 535 + POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_ASD, adev->psp.asd.fw_version); 536 + POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_TA_RAS, adev->psp.ras.feature_version); 537 + POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_TA_XGMI, adev->psp.xgmi.feature_version); 538 538 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_SMC, adev->pm.fw_version); 539 539 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_SDMA, adev->sdma.instance[0].fw_version); 540 540 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_SDMA2, adev->sdma.instance[1].fw_version);

+19 -19

drivers/gpu/drm/amd/amdgpu/psp_v10_0.c

··· 84 84 85 85 ta_hdr = (const struct ta_firmware_header_v1_0 *) 86 86 adev->psp.ta_fw->data; 87 - adev->psp.ta_hdcp_ucode_version = 88 - le32_to_cpu(ta_hdr->ta_hdcp_ucode_version); 89 - adev->psp.ta_hdcp_ucode_size = 90 - le32_to_cpu(ta_hdr->ta_hdcp_size_bytes); 91 - adev->psp.ta_hdcp_start_addr = 87 + adev->psp.hdcp.feature_version = 88 + le32_to_cpu(ta_hdr->hdcp.fw_version); 89 + adev->psp.hdcp.size_bytes = 90 + le32_to_cpu(ta_hdr->hdcp.size_bytes); 91 + adev->psp.hdcp.start_addr = 92 92 (uint8_t *)ta_hdr + 93 93 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 94 94 95 - adev->psp.ta_dtm_ucode_version = 96 - le32_to_cpu(ta_hdr->ta_dtm_ucode_version); 97 - adev->psp.ta_dtm_ucode_size = 98 - le32_to_cpu(ta_hdr->ta_dtm_size_bytes); 99 - adev->psp.ta_dtm_start_addr = 100 - (uint8_t *)adev->psp.ta_hdcp_start_addr + 101 - le32_to_cpu(ta_hdr->ta_dtm_offset_bytes); 95 + adev->psp.dtm.feature_version = 96 + le32_to_cpu(ta_hdr->dtm.fw_version); 97 + adev->psp.dtm.size_bytes = 98 + le32_to_cpu(ta_hdr->dtm.size_bytes); 99 + adev->psp.dtm.start_addr = 100 + (uint8_t *)adev->psp.hdcp.start_addr + 101 + le32_to_cpu(ta_hdr->dtm.offset_bytes); 102 102 103 - adev->psp.ta_securedisplay_ucode_version = 104 - le32_to_cpu(ta_hdr->ta_securedisplay_ucode_version); 105 - adev->psp.ta_securedisplay_ucode_size = 106 - le32_to_cpu(ta_hdr->ta_securedisplay_size_bytes); 107 - adev->psp.ta_securedisplay_start_addr = 108 - (uint8_t *)adev->psp.ta_hdcp_start_addr + 109 - le32_to_cpu(ta_hdr->ta_securedisplay_offset_bytes); 103 + adev->psp.securedisplay.feature_version = 104 + le32_to_cpu(ta_hdr->securedisplay.fw_version); 105 + adev->psp.securedisplay.size_bytes = 106 + le32_to_cpu(ta_hdr->securedisplay.size_bytes); 107 + adev->psp.securedisplay.start_addr = 108 + (uint8_t *)adev->psp.hdcp.start_addr + 109 + le32_to_cpu(ta_hdr->securedisplay.offset_bytes); 110 110 111 111 adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version); 112 112 }

+14 -14

drivers/gpu/drm/amd/amdgpu/psp_v11_0.c

··· 151 151 goto out2; 152 152 153 153 ta_hdr = (const struct ta_firmware_header_v1_0 *)adev->psp.ta_fw->data; 154 - adev->psp.ta_xgmi_ucode_version = le32_to_cpu(ta_hdr->ta_xgmi_ucode_version); 155 - adev->psp.ta_xgmi_ucode_size = le32_to_cpu(ta_hdr->ta_xgmi_size_bytes); 156 - adev->psp.ta_xgmi_start_addr = (uint8_t *)ta_hdr + 154 + adev->psp.xgmi.feature_version = le32_to_cpu(ta_hdr->xgmi.fw_version); 155 + adev->psp.xgmi.size_bytes = le32_to_cpu(ta_hdr->xgmi.size_bytes); 156 + adev->psp.xgmi.start_addr = (uint8_t *)ta_hdr + 157 157 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 158 158 adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version); 159 - adev->psp.ta_ras_ucode_version = le32_to_cpu(ta_hdr->ta_ras_ucode_version); 160 - adev->psp.ta_ras_ucode_size = le32_to_cpu(ta_hdr->ta_ras_size_bytes); 161 - adev->psp.ta_ras_start_addr = (uint8_t *)adev->psp.ta_xgmi_start_addr + 162 - le32_to_cpu(ta_hdr->ta_ras_offset_bytes); 159 + adev->psp.ras.feature_version = le32_to_cpu(ta_hdr->ras.fw_version); 160 + adev->psp.ras.size_bytes = le32_to_cpu(ta_hdr->ras.size_bytes); 161 + adev->psp.ras.start_addr = (uint8_t *)adev->psp.xgmi.start_addr + 162 + le32_to_cpu(ta_hdr->ras.offset_bytes); 163 163 } 164 164 break; 165 165 case CHIP_NAVI10: ··· 186 186 goto out2; 187 187 188 188 ta_hdr = (const struct ta_firmware_header_v1_0 *)adev->psp.ta_fw->data; 189 - adev->psp.ta_hdcp_ucode_version = le32_to_cpu(ta_hdr->ta_hdcp_ucode_version); 190 - adev->psp.ta_hdcp_ucode_size = le32_to_cpu(ta_hdr->ta_hdcp_size_bytes); 191 - adev->psp.ta_hdcp_start_addr = (uint8_t *)ta_hdr + 189 + adev->psp.hdcp.feature_version = le32_to_cpu(ta_hdr->hdcp.fw_version); 190 + adev->psp.hdcp.size_bytes = le32_to_cpu(ta_hdr->hdcp.size_bytes); 191 + adev->psp.hdcp.start_addr = (uint8_t *)ta_hdr + 192 192 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 193 193 194 194 adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version); 195 195 196 - adev->psp.ta_dtm_ucode_version = le32_to_cpu(ta_hdr->ta_dtm_ucode_version); 197 - adev->psp.ta_dtm_ucode_size = le32_to_cpu(ta_hdr->ta_dtm_size_bytes); 198 - adev->psp.ta_dtm_start_addr = (uint8_t *)adev->psp.ta_hdcp_start_addr + 199 - le32_to_cpu(ta_hdr->ta_dtm_offset_bytes); 196 + adev->psp.dtm.feature_version = le32_to_cpu(ta_hdr->dtm.fw_version); 197 + adev->psp.dtm.size_bytes = le32_to_cpu(ta_hdr->dtm.size_bytes); 198 + adev->psp.dtm.start_addr = (uint8_t *)adev->psp.hdcp.start_addr + 199 + le32_to_cpu(ta_hdr->dtm.offset_bytes); 200 200 } 201 201 break; 202 202 case CHIP_SIENNA_CICHLID:

+12 -12

drivers/gpu/drm/amd/amdgpu/psp_v12_0.c

··· 84 84 85 85 ta_hdr = (const struct ta_firmware_header_v1_0 *) 86 86 adev->psp.ta_fw->data; 87 - adev->psp.ta_hdcp_ucode_version = 88 - le32_to_cpu(ta_hdr->ta_hdcp_ucode_version); 89 - adev->psp.ta_hdcp_ucode_size = 90 - le32_to_cpu(ta_hdr->ta_hdcp_size_bytes); 91 - adev->psp.ta_hdcp_start_addr = 87 + adev->psp.hdcp.feature_version = 88 + le32_to_cpu(ta_hdr->hdcp.fw_version); 89 + adev->psp.hdcp.size_bytes = 90 + le32_to_cpu(ta_hdr->hdcp.size_bytes); 91 + adev->psp.hdcp.start_addr = 92 92 (uint8_t *)ta_hdr + 93 93 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 94 94 95 95 adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version); 96 96 97 - adev->psp.ta_dtm_ucode_version = 98 - le32_to_cpu(ta_hdr->ta_dtm_ucode_version); 99 - adev->psp.ta_dtm_ucode_size = 100 - le32_to_cpu(ta_hdr->ta_dtm_size_bytes); 101 - adev->psp.ta_dtm_start_addr = 102 - (uint8_t *)adev->psp.ta_hdcp_start_addr + 103 - le32_to_cpu(ta_hdr->ta_dtm_offset_bytes); 97 + adev->psp.dtm.feature_version = 98 + le32_to_cpu(ta_hdr->dtm.fw_version); 99 + adev->psp.dtm.size_bytes = 100 + le32_to_cpu(ta_hdr->dtm.size_bytes); 101 + adev->psp.dtm.start_addr = 102 + (uint8_t *)adev->psp.hdcp.start_addr + 103 + le32_to_cpu(ta_hdr->dtm.offset_bytes); 104 104 } 105 105 106 106 return 0;