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dt-bindings: net: lan966x: Add lan966x-switch bindings

Document the lan966x switch device driver bindings

Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

authored by

Horatiu Vultur and committed by
David S. Miller
642fcf53 35aefaad

+158
+158
Documentation/devicetree/bindings/net/microchip,lan966x-switch.yaml
··· 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/net/microchip,lan966x-switch.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Microchip Lan966x Ethernet switch controller 8 + 9 + maintainers: 10 + - Horatiu Vultur <horatiu.vultur@microchip.com> 11 + 12 + description: | 13 + The lan966x switch is a multi-port Gigabit AVB/TSN Ethernet Switch with 14 + two integrated 10/100/1000Base-T PHYs. In addition to the integrated PHYs, 15 + it supports up to 2RGMII/RMII, up to 3BASE-X/SERDES/2.5GBASE-X and up to 16 + 2 Quad-SGMII/Quad-USGMII interfaces. 17 + 18 + properties: 19 + $nodename: 20 + pattern: "^switch@[0-9a-f]+$" 21 + 22 + compatible: 23 + const: microchip,lan966x-switch 24 + 25 + reg: 26 + items: 27 + - description: cpu target 28 + - description: general control block target 29 + 30 + reg-names: 31 + items: 32 + - const: cpu 33 + - const: gcb 34 + 35 + interrupts: 36 + minItems: 1 37 + items: 38 + - description: register based extraction 39 + - description: frame dma based extraction 40 + 41 + interrupt-names: 42 + minItems: 1 43 + items: 44 + - const: xtr 45 + - const: fdma 46 + 47 + resets: 48 + items: 49 + - description: Reset controller used for switch core reset (soft reset) 50 + - description: Reset controller used for releasing the phy from reset 51 + 52 + reset-names: 53 + items: 54 + - const: switch 55 + - const: phy 56 + 57 + ethernet-ports: 58 + type: object 59 + patternProperties: 60 + "^port@[0-9a-f]+$": 61 + type: object 62 + 63 + allOf: 64 + - $ref: "http://devicetree.org/schemas/net/ethernet-controller.yaml#" 65 + 66 + properties: 67 + '#address-cells': 68 + const: 1 69 + '#size-cells': 70 + const: 0 71 + 72 + reg: 73 + description: 74 + Switch port number 75 + 76 + phys: 77 + description: 78 + Phandle of a Ethernet SerDes PHY 79 + 80 + phy-mode: 81 + description: 82 + This specifies the interface used by the Ethernet SerDes towards 83 + the PHY or SFP. 84 + enum: 85 + - gmii 86 + - sgmii 87 + - qsgmii 88 + - 1000base-x 89 + - 2500base-x 90 + 91 + phy-handle: 92 + description: 93 + Phandle of a Ethernet PHY. 94 + 95 + sfp: 96 + description: 97 + Phandle of an SFP. 98 + 99 + managed: true 100 + 101 + required: 102 + - reg 103 + - phys 104 + - phy-mode 105 + 106 + oneOf: 107 + - required: 108 + - phy-handle 109 + - required: 110 + - sfp 111 + - managed 112 + 113 + required: 114 + - compatible 115 + - reg 116 + - reg-names 117 + - interrupts 118 + - interrupt-names 119 + - resets 120 + - reset-names 121 + - ethernet-ports 122 + 123 + additionalProperties: false 124 + 125 + examples: 126 + - | 127 + #include <dt-bindings/interrupt-controller/arm-gic.h> 128 + switch: switch@e0000000 { 129 + compatible = "microchip,lan966x-switch"; 130 + reg = <0xe0000000 0x0100000>, 131 + <0xe2000000 0x0800000>; 132 + reg-names = "cpu", "gcb"; 133 + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 134 + interrupt-names = "xtr"; 135 + resets = <&switch_reset 0>, <&phy_reset 0>; 136 + reset-names = "switch", "phy"; 137 + ethernet-ports { 138 + #address-cells = <1>; 139 + #size-cells = <0>; 140 + 141 + port0: port@0 { 142 + reg = <0>; 143 + phy-handle = <&phy0>; 144 + phys = <&serdes 0 0>; 145 + phy-mode = "gmii"; 146 + }; 147 + 148 + port1: port@1 { 149 + reg = <1>; 150 + sfp = <&sfp_eth1>; 151 + managed = "in-band-status"; 152 + phys = <&serdes 2 4>; 153 + phy-mode = "sgmii"; 154 + }; 155 + }; 156 + }; 157 + 158 + ...