+3
Documentation/devicetree/bindings/i2c/renesas,riic.yaml
+3
Documentation/devicetree/bindings/i2c/renesas,riic.yaml
+5
-8
Documentation/i2c/busses/i2c-piix4.rst
+5
-8
Documentation/i2c/busses/i2c-piix4.rst
···
64
64
crashes, data corruption, etc.). Try this only as a last resort (try BIOS
65
65
updates first, for example), and backup first! An even more dangerous
66
66
option is 'force_addr=<IOPORT>'. This will not only enable the PIIX4 like
67
-
'force' foes, but it will also set a new base I/O port address. The SMBus
67
+
'force' does, but it will also set a new base I/O port address. The SMBus
68
68
parts of the PIIX4 needs a range of 8 of these addresses to function
69
69
correctly. If these addresses are already reserved by some other device,
70
70
you will get into big trouble! DON'T USE THIS IF YOU ARE NOT VERY SURE
···
86
86
to change the SMBus Interrupt Select register so the SMBus controller uses
87
87
the SMI mode.
88
88
89
-
1) Use lspci command and locate the PCI device with the SMBus controller:
89
+
1) Use ``lspci`` command and locate the PCI device with the SMBus controller:
90
90
00:0f.0 ISA bridge: ServerWorks OSB4 South Bridge (rev 4f)
91
91
The line may vary for different chipsets. Please consult the driver source
92
-
for all possible PCI ids (and lspci -n to match them). Lets assume the
92
+
for all possible PCI ids (and ``lspci -n`` to match them). Let's assume the
93
93
device is located at 00:0f.0.
94
94
2) Now you just need to change the value in 0xD2 register. Get it first with
95
-
command: lspci -xxx -s 00:0f.0
95
+
command: ``lspci -xxx -s 00:0f.0``
96
96
If the value is 0x3 then you need to change it to 0x1:
97
-
setpci -s 00:0f.0 d2.b=1
97
+
``setpci -s 00:0f.0 d2.b=1``
98
98
99
99
Please note that you don't need to do that in all cases, just when the SMBus is
100
100
not working properly.
···
109
109
Thinkpad laptops, but desktop systems may also be affected. We have no list
110
110
of all affected systems, so the only safe solution was to prevent access to
111
111
the SMBus on all IBM systems (detected using DMI data.)
112
-
113
-
For additional information, read:
114
-
http://www.lm-sensors.org/browser/lm-sensors/trunk/README
+115
-99
Documentation/i2c/i2c-topology.rst
+115
-99
Documentation/i2c/i2c-topology.rst
···
5
5
There are a couple of reasons for building more complex I2C topologies
6
6
than a straight-forward I2C bus with one adapter and one or more devices.
7
7
8
+
Some example use cases are:
9
+
8
10
1. A mux may be needed on the bus to prevent address collisions.
9
11
10
12
2. The bus may be accessible from some external bus master, and arbitration
···
16
14
from the I2C bus, at least most of the time, and sits behind a gate
17
15
that has to be operated before the device can be accessed.
18
16
19
-
Etc
20
-
===
17
+
Several types of hardware components such as I2C muxes, I2C gates and I2C
18
+
arbitrators allow to handle such needs.
21
19
22
-
These constructs are represented as I2C adapter trees by Linux, where
20
+
These components are represented as I2C adapter trees by Linux, where
23
21
each adapter has a parent adapter (except the root adapter) and zero or
24
22
more child adapters. The root adapter is the actual adapter that issues
25
23
I2C transfers, and all adapters with a parent are part of an "i2c-mux"
···
37
35
=======
38
36
39
37
There are two variants of locking available to I2C muxes, they can be
40
-
mux-locked or parent-locked muxes. As is evident from below, it can be
41
-
useful to know if a mux is mux-locked or if it is parent-locked. The
42
-
following list was correct at the time of writing:
43
-
44
-
In drivers/i2c/muxes/:
45
-
46
-
====================== =============================================
47
-
i2c-arb-gpio-challenge Parent-locked
48
-
i2c-mux-gpio Normally parent-locked, mux-locked iff
49
-
all involved gpio pins are controlled by the
50
-
same I2C root adapter that they mux.
51
-
i2c-mux-gpmux Normally parent-locked, mux-locked iff
52
-
specified in device-tree.
53
-
i2c-mux-ltc4306 Mux-locked
54
-
i2c-mux-mlxcpld Parent-locked
55
-
i2c-mux-pca9541 Parent-locked
56
-
i2c-mux-pca954x Parent-locked
57
-
i2c-mux-pinctrl Normally parent-locked, mux-locked iff
58
-
all involved pinctrl devices are controlled
59
-
by the same I2C root adapter that they mux.
60
-
i2c-mux-reg Parent-locked
61
-
====================== =============================================
62
-
63
-
In drivers/iio/:
64
-
65
-
====================== =============================================
66
-
gyro/mpu3050 Mux-locked
67
-
imu/inv_mpu6050/ Mux-locked
68
-
====================== =============================================
69
-
70
-
In drivers/media/:
71
-
72
-
======================= =============================================
73
-
dvb-frontends/lgdt3306a Mux-locked
74
-
dvb-frontends/m88ds3103 Parent-locked
75
-
dvb-frontends/rtl2830 Parent-locked
76
-
dvb-frontends/rtl2832 Mux-locked
77
-
dvb-frontends/si2168 Mux-locked
78
-
usb/cx231xx/ Parent-locked
79
-
======================= =============================================
38
+
mux-locked or parent-locked muxes.
80
39
81
40
82
41
Mux-locked muxes
···
52
89
stages of the transaction. This has the benefit that the mux driver
53
90
may be easier and cleaner to implement, but it has some caveats.
54
91
55
-
==== =====================================================================
56
-
ML1. If you build a topology with a mux-locked mux being the parent
57
-
of a parent-locked mux, this might break the expectation from the
58
-
parent-locked mux that the root adapter is locked during the
59
-
transaction.
60
-
61
-
ML2. It is not safe to build arbitrary topologies with two (or more)
62
-
mux-locked muxes that are not siblings, when there are address
63
-
collisions between the devices on the child adapters of these
64
-
non-sibling muxes.
65
-
66
-
I.e. the select-transfer-deselect transaction targeting e.g. device
67
-
address 0x42 behind mux-one may be interleaved with a similar
68
-
operation targeting device address 0x42 behind mux-two. The
69
-
intension with such a topology would in this hypothetical example
70
-
be that mux-one and mux-two should not be selected simultaneously,
71
-
but mux-locked muxes do not guarantee that in all topologies.
72
-
73
-
ML3. A mux-locked mux cannot be used by a driver for auto-closing
74
-
gates/muxes, i.e. something that closes automatically after a given
75
-
number (one, in most cases) of I2C transfers. Unrelated I2C transfers
76
-
may creep in and close prematurely.
77
-
78
-
ML4. If any non-I2C operation in the mux driver changes the I2C mux state,
79
-
the driver has to lock the root adapter during that operation.
80
-
Otherwise garbage may appear on the bus as seen from devices
81
-
behind the mux, when an unrelated I2C transfer is in flight during
82
-
the non-I2C mux-changing operation.
83
-
==== =====================================================================
84
-
85
-
86
92
Mux-locked Example
87
-
------------------
88
-
93
+
~~~~~~~~~~~~~~~~~~
89
94
90
95
::
91
96
···
84
153
of the entire operation. But accesses to D3 are possibly interleaved
85
154
at any point.
86
155
156
+
Mux-locked caveats
157
+
~~~~~~~~~~~~~~~~~~
158
+
159
+
When using a mux-locked mux, be aware of the following restrictions:
160
+
161
+
[ML1]
162
+
If you build a topology with a mux-locked mux being the parent
163
+
of a parent-locked mux, this might break the expectation from the
164
+
parent-locked mux that the root adapter is locked during the
165
+
transaction.
166
+
167
+
[ML2]
168
+
It is not safe to build arbitrary topologies with two (or more)
169
+
mux-locked muxes that are not siblings, when there are address
170
+
collisions between the devices on the child adapters of these
171
+
non-sibling muxes.
172
+
173
+
I.e. the select-transfer-deselect transaction targeting e.g. device
174
+
address 0x42 behind mux-one may be interleaved with a similar
175
+
operation targeting device address 0x42 behind mux-two. The
176
+
intent with such a topology would in this hypothetical example
177
+
be that mux-one and mux-two should not be selected simultaneously,
178
+
but mux-locked muxes do not guarantee that in all topologies.
179
+
180
+
[ML3]
181
+
A mux-locked mux cannot be used by a driver for auto-closing
182
+
gates/muxes, i.e. something that closes automatically after a given
183
+
number (one, in most cases) of I2C transfers. Unrelated I2C transfers
184
+
may creep in and close prematurely.
185
+
186
+
[ML4]
187
+
If any non-I2C operation in the mux driver changes the I2C mux state,
188
+
the driver has to lock the root adapter during that operation.
189
+
Otherwise garbage may appear on the bus as seen from devices
190
+
behind the mux, when an unrelated I2C transfer is in flight during
191
+
the non-I2C mux-changing operation.
192
+
87
193
88
194
Parent-locked muxes
89
195
-------------------
···
129
161
transfer-deselect transaction. The implication is that the mux driver
130
162
has to ensure that any and all I2C transfers through that parent
131
163
adapter during the transaction are unlocked I2C transfers (using e.g.
132
-
__i2c_transfer), or a deadlock will follow. There are a couple of
133
-
caveats.
134
-
135
-
==== ====================================================================
136
-
PL1. If you build a topology with a parent-locked mux being the child
137
-
of another mux, this might break a possible assumption from the
138
-
child mux that the root adapter is unused between its select op
139
-
and the actual transfer (e.g. if the child mux is auto-closing
140
-
and the parent mux issues I2C transfers as part of its select).
141
-
This is especially the case if the parent mux is mux-locked, but
142
-
it may also happen if the parent mux is parent-locked.
143
-
144
-
PL2. If select/deselect calls out to other subsystems such as gpio,
145
-
pinctrl, regmap or iio, it is essential that any I2C transfers
146
-
caused by these subsystems are unlocked. This can be convoluted to
147
-
accomplish, maybe even impossible if an acceptably clean solution
148
-
is sought.
149
-
==== ====================================================================
150
-
164
+
__i2c_transfer), or a deadlock will follow.
151
165
152
166
Parent-locked Example
153
-
---------------------
167
+
~~~~~~~~~~~~~~~~~~~~~
154
168
155
169
::
156
170
···
162
212
9. M1 unlocks its parent adapter.
163
213
10. M1 unlocks muxes on its parent.
164
214
165
-
166
215
This means that accesses to both D2 and D3 are locked out for the full
167
216
duration of the entire operation.
217
+
218
+
Parent-locked Caveats
219
+
~~~~~~~~~~~~~~~~~~~~~
220
+
221
+
When using a parent-locked mux, be aware of the following restrictions:
222
+
223
+
[PL1]
224
+
If you build a topology with a parent-locked mux being the child
225
+
of another mux, this might break a possible assumption from the
226
+
child mux that the root adapter is unused between its select op
227
+
and the actual transfer (e.g. if the child mux is auto-closing
228
+
and the parent mux issues I2C transfers as part of its select).
229
+
This is especially the case if the parent mux is mux-locked, but
230
+
it may also happen if the parent mux is parent-locked.
231
+
232
+
[PL2]
233
+
If select/deselect calls out to other subsystems such as gpio,
234
+
pinctrl, regmap or iio, it is essential that any I2C transfers
235
+
caused by these subsystems are unlocked. This can be convoluted to
236
+
accomplish, maybe even impossible if an acceptably clean solution
237
+
is sought.
168
238
169
239
170
240
Complex Examples
···
231
261
When device D1 is accessed, accesses to D2 are locked out for the
232
262
full duration of the operation (muxes on the top child adapter of M1
233
263
are locked). But accesses to D3 and D4 are possibly interleaved at
234
-
any point. Accesses to D3 locks out D1 and D2, but accesses to D4
235
-
are still possibly interleaved.
264
+
any point.
265
+
266
+
Accesses to D3 locks out D1 and D2, but accesses to D4 are still possibly
267
+
interleaved.
236
268
237
269
238
270
Mux-locked mux as parent of parent-locked mux
···
366
394
When D1 or D2 are accessed, accesses to D3 and D4 are locked out while
367
395
accesses to D5 may interleave. When D3 or D4 are accessed, accesses to
368
396
all other devices are locked out.
397
+
398
+
399
+
Mux type of existing device drivers
400
+
===================================
401
+
402
+
Whether a device is mux-locked or parent-locked depends on its
403
+
implementation. The following list was correct at the time of writing:
404
+
405
+
In drivers/i2c/muxes/:
406
+
407
+
====================== =============================================
408
+
i2c-arb-gpio-challenge Parent-locked
409
+
i2c-mux-gpio Normally parent-locked, mux-locked iff
410
+
all involved gpio pins are controlled by the
411
+
same I2C root adapter that they mux.
412
+
i2c-mux-gpmux Normally parent-locked, mux-locked iff
413
+
specified in device-tree.
414
+
i2c-mux-ltc4306 Mux-locked
415
+
i2c-mux-mlxcpld Parent-locked
416
+
i2c-mux-pca9541 Parent-locked
417
+
i2c-mux-pca954x Parent-locked
418
+
i2c-mux-pinctrl Normally parent-locked, mux-locked iff
419
+
all involved pinctrl devices are controlled
420
+
by the same I2C root adapter that they mux.
421
+
i2c-mux-reg Parent-locked
422
+
====================== =============================================
423
+
424
+
In drivers/iio/:
425
+
426
+
====================== =============================================
427
+
gyro/mpu3050 Mux-locked
428
+
imu/inv_mpu6050/ Mux-locked
429
+
====================== =============================================
430
+
431
+
In drivers/media/:
432
+
433
+
======================= =============================================
434
+
dvb-frontends/lgdt3306a Mux-locked
435
+
dvb-frontends/m88ds3103 Parent-locked
436
+
dvb-frontends/rtl2830 Parent-locked
437
+
dvb-frontends/rtl2832 Mux-locked
438
+
dvb-frontends/si2168 Mux-locked
439
+
usb/cx231xx/ Parent-locked
440
+
======================= =============================================