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linux
arm64: boot protocol documentation update for GICv3
Linux has some requirements that must be satisfied in order to boot
on a system built with a GICv3.
Acked-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
authored by
Marc Zyngier
and committed by
Christoffer Dall
63f8344c
96f68023
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+8
Documentation/arm64/booting.txt
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Documentation/arm64/booting.txt
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the kernel image will be entered must be initialised by software at a
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higher exception level to prevent execution in an UNKNOWN state.
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For systems with a GICv3 interrupt controller:
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- If EL3 is present:
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ICC_SRE_EL3.Enable (bit 3) must be initialiased to 0b1.
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ICC_SRE_EL3.SRE (bit 0) must be initialised to 0b1.
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- If the kernel is entered at EL1:
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ICC.SRE_EL2.Enable (bit 3) must be initialised to 0b1
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ICC_SRE_EL2.SRE (bit 0) must be initialised to 0b1.
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The requirements described above for CPU mode, caches, MMUs, architected
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timers, coherency and system registers apply to all CPUs. All CPUs must
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enter the kernel in the same exception level.