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dt-bindings: clock: Add Qcom SM8450 GPUCC
Add device tree bindings for the graphics clock controller on Qualcomm
Technology Inc's SM8450 SoCs.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230517-topic-waipio-gpucc-v1-1-4f40e282af1d@linaro.org
authored by
Konrad Dybcio
and committed by
Bjorn Andersson
63f4e4b6
ac9a7868
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Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml
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Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,sm8450-gpucc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Graphics Clock & Reset Controller on SM8450
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maintainers:
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- Konrad Dybcio <konrad.dybcio@linaro.org>
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description: |
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Qualcomm graphics clock control module provides the clocks, resets and power
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domains on Qualcomm SoCs.
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See also::
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include/dt-bindings/clock/qcom,sm8450-gpucc.h
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include/dt-bindings/reset/qcom,sm8450-gpucc.h
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properties:
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compatible:
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enum:
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- qcom,sm8450-gpucc
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clocks:
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items:
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- description: Board XO source
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- description: GPLL0 main branch source
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- description: GPLL0 div branch source
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'#clock-cells':
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const: 1
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'#reset-cells':
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const: 1
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'#power-domain-cells':
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const: 1
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reg:
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maxItems: 1
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required:
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- compatible
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- reg
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- clocks
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- '#clock-cells'
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- '#reset-cells'
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- '#power-domain-cells'
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,gcc-sm8450.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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clock-controller@3d90000 {
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compatible = "qcom,sm8450-gpucc";
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reg = <0 0x03d90000 0 0xa000>;
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clocks = <&rpmhcc RPMH_CXO_CLK>,
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<&gcc GCC_GPU_GPLL0_CLK_SRC>,
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<&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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};
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};
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...
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include/dt-bindings/clock/qcom,sm8450-gpucc.h
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include/dt-bindings/clock/qcom,sm8450-gpucc.h
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) 2020, The Linux Foundation. All rights reserved.
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* Copyright (c) 2023, Linaro Limited
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*/
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#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8450_H
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#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8450_H
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/* Clocks */
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#define GPU_CC_AHB_CLK 0
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#define GPU_CC_CRC_AHB_CLK 1
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#define GPU_CC_CX_APB_CLK 2
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#define GPU_CC_CX_FF_CLK 3
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#define GPU_CC_CX_GMU_CLK 4
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#define GPU_CC_CX_SNOC_DVM_CLK 5
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#define GPU_CC_CXO_AON_CLK 6
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#define GPU_CC_CXO_CLK 7
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#define GPU_CC_DEMET_CLK 8
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#define GPU_CC_DEMET_DIV_CLK_SRC 9
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#define GPU_CC_FF_CLK_SRC 10
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#define GPU_CC_FREQ_MEASURE_CLK 11
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#define GPU_CC_GMU_CLK_SRC 12
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#define GPU_CC_GX_FF_CLK 13
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#define GPU_CC_GX_GFX3D_CLK 14
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#define GPU_CC_GX_GFX3D_RDVM_CLK 15
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#define GPU_CC_GX_GMU_CLK 16
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#define GPU_CC_GX_VSENSE_CLK 17
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#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 18
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#define GPU_CC_HUB_AHB_DIV_CLK_SRC 19
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#define GPU_CC_HUB_AON_CLK 20
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#define GPU_CC_HUB_CLK_SRC 21
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#define GPU_CC_HUB_CX_INT_CLK 22
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#define GPU_CC_HUB_CX_INT_DIV_CLK_SRC 23
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#define GPU_CC_MEMNOC_GFX_CLK 24
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#define GPU_CC_MND1X_0_GFX3D_CLK 25
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#define GPU_CC_MND1X_1_GFX3D_CLK 26
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#define GPU_CC_PLL0 27
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#define GPU_CC_PLL1 28
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#define GPU_CC_SLEEP_CLK 29
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#define GPU_CC_XO_CLK_SRC 30
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#define GPU_CC_XO_DIV_CLK_SRC 31
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/* GDSCs */
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#define GPU_GX_GDSC 0
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#define GPU_CX_GDSC 1
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#endif
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include/dt-bindings/reset/qcom,sm8450-gpucc.h
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include/dt-bindings/reset/qcom,sm8450-gpucc.h
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) 2019, The Linux Foundation. All rights reserved.
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* Copyright (c) 2023, Linaro Limited
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*/
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#ifndef _DT_BINDINGS_RESET_QCOM_GPU_CC_SM8450_H
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#define _DT_BINDINGS_RESET_QCOM_GPU_CC_SM8450_H
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#define GPUCC_GPU_CC_ACD_BCR 0
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#define GPUCC_GPU_CC_CX_BCR 1
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#define GPUCC_GPU_CC_FAST_HUB_BCR 2
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#define GPUCC_GPU_CC_FF_BCR 3
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#define GPUCC_GPU_CC_GFX3D_AON_BCR 4
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#define GPUCC_GPU_CC_GMU_BCR 5
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#define GPUCC_GPU_CC_GX_BCR 6
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#define GPUCC_GPU_CC_XO_BCR 7
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#define GPUCC_GPU_CC_GX_ACD_IROOT_BCR 8
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#endif