Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

ARM: dts: Add support for emtrion emCON-MX6 series

This patch adds support for the emtrion GmbH emCON-MX6 modules.
They are available with imx.6 Solo, Dual-Lite, Dual and Quad
equipped with Memory from 512MB to 2GB (configured by U-Boot).

Our default developer-Kit ships with the Avari baseboard and the
EDT ETM0700G0BDH6 Display (imx6[q|dl]-emcon-avari).

The devicetree is split into the common part providing all module
components and the basic support for all SoC versions
(imx6qdl-emcon.dtsi) and parts which are i.mx6 S|DL and D|Q relevant.
Finally the support for the avari baseboard in the developer-kit
configuration is provided by the emcon-avari dts files.

Signed-off-by: Jan Tuerk <jan.tuerk@emtrion.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

authored by

Jan Tuerk and committed by
Shawn Guo
63e71fed d87cf8ce

+1039
+2
arch/arm/boot/dts/Makefile
··· 396 396 imx6dl-cubox-i-emmc-som-v15.dtb \ 397 397 imx6dl-cubox-i-som-v15.dtb \ 398 398 imx6dl-dfi-fs700-m60.dtb \ 399 + imx6dl-emcon-avari.dtb \ 399 400 imx6dl-gw51xx.dtb \ 400 401 imx6dl-gw52xx.dtb \ 401 402 imx6dl-gw53xx.dtb \ ··· 461 460 imx6q-display5-tianma-tm070-1280x768.dtb \ 462 461 imx6q-dmo-edmqmx6.dtb \ 463 462 imx6q-dms-ba16.dtb \ 463 + imx6q-emcon-avari.dtb \ 464 464 imx6q-evi.dtb \ 465 465 imx6q-gk802.dtb \ 466 466 imx6q-gw51xx.dtb \
+14
arch/arm/boot/dts/imx6dl-emcon-avari.dts
··· 1 + // SPDX-License-Identifier: (GPL-2.0 or MIT) 2 + // 3 + // Copyright (C) 2018 emtrion GmbH 4 + // 5 + 6 + /dts-v1/; 7 + #include "imx6dl.dtsi" 8 + #include "imx6qdl-emcon.dtsi" 9 + #include "imx6qdl-emcon-avari.dtsi" 10 + 11 + / { 12 + model = "emtrion SoM emCON-MX6 Solo/Dual-Lite Avari"; 13 + compatible = "emtrion,emcon-mx6-avari", "fsl,imx6dl"; 14 + };
+14
arch/arm/boot/dts/imx6q-emcon-avari.dts
··· 1 + // SPDX-License-Identifier: (GPL-2.0 or MIT) 2 + // 3 + // Copyright (C) 2018 emtrion GmbH 4 + // 5 + 6 + /dts-v1/; 7 + #include "imx6q.dtsi" 8 + #include "imx6qdl-emcon.dtsi" 9 + #include "imx6qdl-emcon-avari.dtsi" 10 + 11 + / { 12 + model = "emtrion SoM emCON-MX6 Dual/Quad on Avari"; 13 + compatible = "emtrion,emcon-mx6-avari", "fsl,imx6q"; 14 + };
+177
arch/arm/boot/dts/imx6qdl-emcon-avari.dtsi
··· 1 + // SPDX-License-Identifier: (GPL-2.0 or MIT) 2 + // 3 + // Copyright (C) 2018 emtrion GmbH 4 + // 5 + 6 + / { 7 + aliases { 8 + boardid = &boardid; 9 + mmc0 = &usdhc3; 10 + mmc1 = &usdhc2; 11 + mmc2 = &usdhc1; 12 + mmc3 = &usdhc4; 13 + }; 14 + 15 + reg_wall_5p0: reg-wall5p0 { 16 + compatible = "regulator-fixed"; 17 + regulator-name = "Main-Supply"; 18 + regulator-min-microvolt = <5000000>; 19 + regulator-max-microvolt = <5000000>; 20 + regulator-always-on; 21 + regulator-boot-on; 22 + }; 23 + 24 + reg_base3p3: reg-base3p3 { 25 + compatible = "regulator-fixed"; 26 + vin-supply = <&reg_wall_5p0>; 27 + regulator-name = "3V3-avari"; 28 + regulator-min-microvolt = <3300000>; 29 + regulator-max-microvolt = <3300000>; 30 + regulator-always-on; 31 + regulator-boot-on; 32 + }; 33 + 34 + reg_base1p5: reg-base1p5 { 35 + compatible = "regulator-fixed"; 36 + vin-supply = <&reg_base3p3>; 37 + regulator-name = "1V5-avari"; 38 + regulator-min-microvolt = <1500000>; 39 + regulator-max-microvolt = <1500000>; 40 + regulator-always-on; 41 + regulator-boot-on; 42 + }; 43 + 44 + reg_usb_otg: reg-otgvbus { 45 + compatible = "regulator-fixed"; 46 + vin-supply = <&reg_wall_5p0>; 47 + regulator-name = "OTG_VBUS"; 48 + regulator-min-microvolt = <5000000>; 49 + regulator-max-microvolt = <5000000>; 50 + gpio = <&gpio1 8 GPIO_ACTIVE_LOW>; 51 + regulator-always-on; 52 + }; 53 + 54 + clk_codec: clock-codec { 55 + compatible = "fixed-clock"; 56 + #clock-cells = <0>; 57 + clock-frequency = <12000000>; 58 + }; 59 + 60 + sound { 61 + compatible = "fsl,imx-audio-sgtl5000"; 62 + model = "emCON-avari-sgtl5000"; 63 + ssi-controller = <&ssi2>; 64 + audio-codec = <&sgtl5000>; 65 + audio-routing = 66 + "Headphone Jack", "HP_OUT"; 67 + mux-int-port = <2>; 68 + mux-ext-port = <3>; 69 + }; 70 + }; 71 + 72 + &audmux { 73 + pinctrl-names = "default"; 74 + pinctrl-0 = <&pinctrl_audmux>; 75 + status = "okay"; 76 + }; 77 + 78 + &can1 { 79 + status = "okay"; 80 + }; 81 + 82 + &can2 { 83 + status = "okay"; 84 + }; 85 + 86 + &ecspi2 { 87 + status = "okay"; 88 + }; 89 + 90 + &hdmi { 91 + ddc-i2c-bus = <&i2c2>; 92 + status = "okay"; 93 + }; 94 + 95 + &i2c2 { 96 + status = "okay"; 97 + }; 98 + 99 + &i2c3 { 100 + clock-frequency = <100000>; 101 + pinctrl-names = "default"; 102 + pinctrl-0 = <&pinctrl_i2c3>; 103 + status = "okay"; 104 + 105 + sgtl5000: audio-codec@a { 106 + compatible = "fsl,sgtl5000"; 107 + reg = <0x0a>; 108 + #sound-dai-cells = <0>; 109 + clocks = <&clk_codec>; 110 + VDDA-supply = <&reg_base3p3>; 111 + VDDIO-supply = <&reg_base3p3>; 112 + }; 113 + 114 + captouch: touchscreen@38 { 115 + compatible = "edt,edt-ft5406"; 116 + reg = <0x38>; 117 + pinctrl-names = "default"; 118 + pinctrl-0 = <&pinctrl_irq_touch2 &pinctrl_emcon_gpio4>; 119 + interrupt-parent = <&gpio6>; 120 + interrupts = <31 IRQ_TYPE_EDGE_FALLING>; 121 + wake-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>; 122 + wakeup-source; 123 + }; 124 + 125 + boardid: gpio@3a { 126 + compatible = "nxp,pca8574"; 127 + reg = <0x3a>; 128 + gpio-controller; 129 + #gpio-cells = <1>; 130 + }; 131 + }; 132 + 133 + &pcie { 134 + status = "okay"; 135 + }; 136 + 137 + &rgb_encoder { 138 + status = "okay"; 139 + }; 140 + 141 + &rgb_panel { 142 + compatible = "edt,etm0700g0bdh6"; 143 + status = "okay"; 144 + }; 145 + 146 + &ssi2 { 147 + status = "okay"; 148 + }; 149 + 150 + &uart2 { 151 + status = "okay"; 152 + uart-has-rtscts; 153 + }; 154 + 155 + &uart3 { 156 + status = "okay"; 157 + }; 158 + 159 + &uart4 { 160 + status = "okay"; 161 + }; 162 + 163 + &uart5 { 164 + status = "okay"; 165 + }; 166 + 167 + &usbh1 { 168 + status = "okay"; 169 + }; 170 + 171 + &usbotg { 172 + status = "okay"; 173 + }; 174 + 175 + &usdhc1 { 176 + status = "okay"; 177 + };
+832
arch/arm/boot/dts/imx6qdl-emcon.dtsi
··· 1 + // SPDX-License-Identifier: (GPL-2.0 or MIT) 2 + // 3 + // Copyright (C) 2018 emtrion GmbH 4 + // 5 + 6 + #include <dt-bindings/gpio/gpio.h> 7 + #include <dt-bindings/pwm/pwm.h> 8 + #include <dt-bindings/input/input.h> 9 + 10 + / { 11 + 12 + model = "emtrion SoM emCON-MX6"; 13 + compatible = "emtrion,emcon-mx6"; 14 + 15 + aliases { 16 + mmc0 = &usdhc3; 17 + mmc1 = &usdhc2; 18 + mmc2 = &usdhc1; 19 + rtc0 = &ds1307; 20 + }; 21 + 22 + chosen { 23 + stdout-path = &uart1; 24 + }; 25 + 26 + memory@10000000 { 27 + reg = <0x10000000 0x40000000>; 28 + }; 29 + 30 + gpio-keys { 31 + compatible = "gpio-keys"; 32 + pinctrl-names = "default"; 33 + pinctrl-0 = <&pinctrl_emcon_wake>; 34 + 35 + wake { 36 + label = "Wake"; 37 + linux,code = <KEY_WAKEUP>; 38 + gpios = <&gpio3 2 GPIO_ACTIVE_LOW>; 39 + wakeup-source; 40 + }; 41 + }; 42 + 43 + som_leds: leds { 44 + compatible = "gpio-leds"; 45 + pinctrl-names = "default"; 46 + pinctrl-0 = <&pinctrl_som_leds>; 47 + 48 + green { 49 + label = "som:green"; 50 + gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>; 51 + linux,default-trigger = "heartbeat"; 52 + default-state = "on"; 53 + }; 54 + 55 + red { 56 + label = "som:red"; 57 + gpios = <&gpio3 1 GPIO_ACTIVE_LOW>; 58 + default-state = "keep"; 59 + }; 60 + 61 + }; 62 + 63 + lvds_backlight: lvds-backlight { 64 + compatible = "pwm-backlight"; 65 + pinctrl-names = "default"; 66 + pinctrl-0 = <&pinctrl_lvds_bl>; 67 + enable-gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>; 68 + pwms = <&pwm1 0 50000>; 69 + brightness-levels = < 70 + 0 4 8 16 32 64 80 96 112 71 + 128 144 160 176 250 72 + >; 73 + default-brightness-level = <13>; 74 + status = "okay"; 75 + }; 76 + 77 + pwm_fan: pwm-fan { 78 + compatible = "pwm-fan"; 79 + cooling-min-state = <0>; 80 + cooling-max-state = <4>; 81 + #cooling-cells = <2>; 82 + pwms = <&pwm4 0 50000>; 83 + cooling-levels = <0 64 127 191 255>; 84 + status = "disabled"; 85 + }; 86 + 87 + 88 + rgb_encoder: display { 89 + compatible = "fsl,imx-parallel-display"; 90 + #address-cells = <1>; 91 + #size-cells = <0>; 92 + pinctrl-names = "default"; 93 + pinctrl-0 = <&pinctrl_rgb24_display>; 94 + status = "disabled"; 95 + 96 + port@0 { 97 + reg = <0>; 98 + 99 + rgb_encoder_in: endpoint { 100 + remote-endpoint = <&ipu1_di0_disp0>; 101 + }; 102 + }; 103 + 104 + port@1 { 105 + reg = <1>; 106 + 107 + rgb_encoder_out: endpoint { 108 + remote-endpoint = <&rgb_panel_in>; 109 + }; 110 + }; 111 + }; 112 + 113 + rgb_panel: lcd { 114 + backlight = <&rgb_backlight>; 115 + power-supply = <&reg_parallel_disp>; 116 + 117 + port { 118 + rgb_panel_in: endpoint { 119 + remote-endpoint = <&rgb_encoder_out>; 120 + }; 121 + }; 122 + }; 123 + 124 + reg_parallel_disp: reg-parallel-display { 125 + compatible = "regulator-fixed"; 126 + pinctrl-names = "default"; 127 + pinctrl-0 = <&pinctrl_rgb_bl_en>; 128 + regulator-name = "LCD-Supply"; 129 + regulator-min-microvolt = <5000000>; 130 + regulator-max-microvolt = <5000000>; 131 + gpio = <&gpio7 9 GPIO_ACTIVE_HIGH>; 132 + enable-active-high; 133 + }; 134 + 135 + reg_lvds_disp: reg-lvds-display { 136 + compatible = "regulator-fixed"; 137 + regulator-name = "LVDS-Supply"; 138 + regulator-min-microvolt = <5000000>; 139 + regulator-max-microvolt = <5000000>; 140 + gpio = <&gpio7 10 GPIO_ACTIVE_HIGH>; 141 + enable-active-high; 142 + }; 143 + 144 + rgb_backlight: rgb-backlight { 145 + compatible = "pwm-backlight"; 146 + pinctrl-names = "default"; 147 + pinctrl-0 = <&pinctrl_rgb_bl>; 148 + enable-gpios = <&gpio6 8 GPIO_ACTIVE_HIGH>; 149 + pwms = <&pwm3 0 5000000>; 150 + brightness-levels = < 151 + 250 176 160 144 128 112 152 + 96 80 64 48 32 16 8 1 153 + >; 154 + default-brightness-level = <13>; 155 + status = "okay"; 156 + }; 157 + }; 158 + 159 + &can1 { 160 + pinctrl-names = "default"; 161 + pinctrl-0 = <&pinctrl_can1>; 162 + }; 163 + 164 + &can2 { 165 + pinctrl-names = "default"; 166 + pinctrl-0 = <&pinctrl_can2>; 167 + }; 168 + 169 + &ecspi2 { 170 + pinctrl-names = "default"; 171 + pinctrl-0 = <&pinctrl_ecspi2>; 172 + cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>, 173 + <&gpio2 27 GPIO_ACTIVE_HIGH>; 174 + }; 175 + 176 + &ecspi4 { 177 + pinctrl-names = "default"; 178 + pinctrl-0 = <&pinctrl_nor_flash>; 179 + }; 180 + 181 + &fec { 182 + pinctrl-names = "default"; 183 + pinctrl-0 = <&pinctrl_enet>; 184 + phy-mode = "rgmii"; 185 + phy-reset-gpios = <&gpio5 20 GPIO_ACTIVE_LOW>; 186 + phy-reset-duration = <50>; 187 + phy-supply = <&vdd_1V8_reg>; 188 + phy-handle = <&ksz9031>; 189 + status = "okay"; 190 + 191 + mdio { 192 + #address-cells = <1>; 193 + #size-cells = <0>; 194 + 195 + ksz9031: phy@0 { 196 + compatible = "ethernet-phy-ieee802.3-c22"; 197 + reg = <0>; 198 + interrupt-parent = <&gpio1>; 199 + interrupts = <30 IRQ_TYPE_EDGE_FALLING>; 200 + rxdv-skew-ps = <480>; 201 + txen-skew-ps = <480>; 202 + rxd0-skew-ps = <480>; 203 + rxd1-skew-ps = <480>; 204 + rxd2-skew-ps = <480>; 205 + rxd3-skew-ps = <480>; 206 + txd0-skew-ps = <420>; 207 + txd1-skew-ps = <420>; 208 + txd2-skew-ps = <360>; 209 + txd3-skew-ps = <360>; 210 + txc-skew-ps = <1020>; 211 + rxc-skew-ps = <960>; 212 + }; 213 + }; 214 + }; 215 + 216 + &i2c1 { 217 + clock-frequency = <100000>; 218 + pinctrl-names = "default"; 219 + pinctrl-0 = <&pinctrl_i2c1>; 220 + status = "okay"; 221 + 222 + da9063: pmic@58 { 223 + compatible = "dlg,da9063"; 224 + reg = <0x58>; 225 + pinctrl-names = "default"; 226 + pinctrl-0 = <&pinctrl_pmic>; 227 + interrupt-parent = <&gpio2>; 228 + interrupts = <8 IRQ_TYPE_LEVEL_LOW>; 229 + interrupt-controller; 230 + 231 + onkey { 232 + compatible = "dlg,da9063-onkey"; 233 + wakeup-source; 234 + }; 235 + 236 + watchdog { 237 + compatible = "dlg,da9063-watchdog"; 238 + timeout-sec = <0>; 239 + }; 240 + 241 + regulators { 242 + vddcore_reg: bcore1 { 243 + regulator-min-microvolt = <1100000>; 244 + regulator-max-microvolt = <1450000>; 245 + regulator-ramp-delay = <2>; 246 + regulator-name = "DA9063_CORE"; 247 + regulator-always-on; 248 + }; 249 + 250 + vddsoc_reg: bcore2 { 251 + regulator-min-microvolt = <1100000>; 252 + regulator-max-microvolt = <1450000>; 253 + regulator-ramp-delay = <2>; 254 + regulator-name = "DA9063_SOC"; 255 + regulator-always-on; 256 + }; 257 + 258 + vdd_ddr3_reg: bpro { 259 + regulator-min-microvolt = <1500000>; 260 + regulator-max-microvolt = <1500000>; 261 + regulator-ramp-delay = <2>; 262 + regulator-always-on; 263 + }; 264 + 265 + vdd_3v3_reg: bperi { 266 + regulator-min-microvolt = <3300000>; 267 + regulator-max-microvolt = <3300000>; 268 + regulator-ramp-delay = <2>; 269 + regulator-always-on; 270 + }; 271 + 272 + vdd_sata_reg: ldo3 { 273 + regulator-min-microvolt = <2500000>; 274 + regulator-max-microvolt = <2500000>; 275 + regulator-always-on; 276 + }; 277 + vdd_mipi_reg: ldo4 { 278 + regulator-min-microvolt = <2500000>; 279 + regulator-max-microvolt = <2500000>; 280 + regulator-always-on; 281 + }; 282 + 283 + vdd_mx6_snvs_reg: ldo5 { 284 + regulator-min-microvolt = <3300000>; 285 + regulator-max-microvolt = <3300000>; 286 + regulator-always-on; 287 + }; 288 + 289 + vdd_hdmi_reg: ldo6 { 290 + regulator-min-microvolt = <2500000>; 291 + regulator-max-microvolt = <2500000>; 292 + regulator-always-on; 293 + regulator-boot-on; 294 + }; 295 + 296 + vdd_pcie_reg: ldo7 { 297 + regulator-min-microvolt = <2500000>; 298 + regulator-max-microvolt = <2500000>; 299 + regulator-always-on; 300 + }; 301 + 302 + vdd_1V8_reg: ldo8 { 303 + regulator-min-microvolt = <1800000>; 304 + regulator-max-microvolt = <1800000>; 305 + regulator-always-on; 306 + }; 307 + 308 + vdd_3V3_sdc_reg: ldo9 { 309 + regulator-min-microvolt = <1800000>; 310 + regulator-max-microvolt = <3300000>; 311 + regulator-always-on; 312 + }; 313 + 314 + vdd_1V2_reg: ldo10 { 315 + regulator-min-microvolt = <1200000>; 316 + regulator-max-microvolt = <1200000>; 317 + regulator-always-on; 318 + }; 319 + }; 320 + }; 321 + 322 + ds1307: rtc@68 { 323 + compatible = "dallas,ds1307"; 324 + reg = <0x68>; 325 + }; 326 + }; 327 + 328 + &i2c2 { 329 + clock-frequency = <100000>; 330 + pinctrl-names = "default"; 331 + pinctrl-0 = <&pinctrl_i2c2>; 332 + }; 333 + 334 + &iomuxc { 335 + 336 + pinctrl_audmux: audmuxgrp { 337 + fsl,pins = < 338 + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 339 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x1b060 340 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x130B0 341 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x1b060 342 + >; 343 + }; 344 + 345 + pinctrl_can1: can1grp { 346 + fsl,pins = < 347 + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 348 + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 349 + >; 350 + }; 351 + 352 + pinctrl_can2: can2grp { 353 + fsl,pins = < 354 + MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b1 355 + MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b1 356 + >; 357 + }; 358 + 359 + pinctrl_cpi1: csi0grp { 360 + fsl,pins = < 361 + MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0xb0b1 362 + MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b1 363 + MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b1 364 + MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b1 365 + MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b1 366 + MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b1 367 + MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b1 368 + MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b1 369 + MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b1 370 + MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b1 371 + MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b1 372 + >; 373 + }; 374 + 375 + /*camera2-pinctrl is in imx6q-emcon.dtsi or imx6dl-emcon.dtsi*/ 376 + 377 + pinctrl_ecspi2: ecspi2grp { 378 + fsl,pins = < 379 + MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 380 + MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 381 + MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 382 + MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x100b1 383 + MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x100b1 384 + >; 385 + }; 386 + 387 + pinctrl_emcon_gpio1: emcongpio1 { 388 + fsl,pins = < 389 + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x0b0b1 390 + >; 391 + }; 392 + 393 + pinctrl_emcon_gpio2: emcongpio2 { 394 + fsl,pins = < 395 + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x0b0b1 396 + >; 397 + }; 398 + 399 + pinctrl_emcon_gpio3: emcongpio3 { 400 + fsl,pins = < 401 + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x0b0b1 402 + >; 403 + }; 404 + 405 + pinctrl_emcon_gpio4: emcongpio4 { 406 + fsl,pins = < 407 + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x0b0b1 408 + >; 409 + }; 410 + 411 + pinctrl_emcon_gpio5: emcongpio5 { 412 + fsl,pins = < 413 + MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x0b0b1 414 + >; 415 + }; 416 + 417 + pinctrl_emcon_gpio6: emcongpio6 { 418 + fsl,pins = < 419 + MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x0b0b1 420 + >; 421 + }; 422 + 423 + pinctrl_emcon_gpio7: emcongpio7 { 424 + fsl,pins = < 425 + MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x0b0b1 426 + >; 427 + }; 428 + 429 + pinctrl_emcon_gpio8: emcongpio8 { 430 + fsl,pins = < 431 + MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x0b0b1 432 + >; 433 + }; 434 + 435 + pinctrl_emcon_irq_a: emconirqa { 436 + fsl,pins = < 437 + MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x0b0b1 438 + >; 439 + }; 440 + 441 + pinctrl_emcon_irq_b: emconirqb { 442 + fsl,pins = < 443 + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x0b0b1 444 + >; 445 + }; 446 + 447 + pinctrl_emcon_irq_c: emconirqc { 448 + fsl,pins = < 449 + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x0b0b1 450 + >; 451 + }; 452 + 453 + pinctrl_emcon_irq_pwr: emconirqpwr { 454 + fsl,pins = < 455 + MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x0b0b1 456 + >; 457 + }; 458 + 459 + pinctrl_emcon_wake: emconwake { 460 + fsl,pins = < 461 + MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x1b0b1 462 + >; 463 + }; 464 + 465 + pinctrl_enet: enetgrp { 466 + fsl,pins = < 467 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b030 468 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b030 469 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 470 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 471 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 472 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 473 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 474 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 475 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x4001a0b1 476 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 477 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 478 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 479 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 480 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 481 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 482 + MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b058 483 + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 484 + >; 485 + }; 486 + 487 + pinctrl_i2c1: i2c1grp { 488 + fsl,pins = < 489 + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 490 + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 491 + >; 492 + }; 493 + 494 + pinctrl_i2c2: i2c2grp { 495 + fsl,pins = < 496 + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 497 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 498 + >; 499 + }; 500 + 501 + pinctrl_i2c3: i2c3grp { 502 + fsl,pins = < 503 + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4000b070 504 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b870 505 + >; 506 + }; 507 + 508 + pinctrl_irq_touch1: irqtouch1 { 509 + fsl,pins = < 510 + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x0b0b1 511 + >; 512 + }; 513 + 514 + pinctrl_irq_touch2: irqtouch2 { 515 + fsl,pins = < 516 + MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x0b0b1 517 + >; 518 + }; 519 + 520 + pinctrl_lvds_bl: lvdsbacklightgrp { 521 + fsl,pins = < 522 + MX6QDL_PAD_GPIO_9__PWM1_OUT 0x0b0b1 523 + MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x0b0b1 524 + >; 525 + }; 526 + 527 + pinctrl_lvds_reg: lvdsreggrp { 528 + fsl,pins = < 529 + MX6QDL_PAD_SD4_CLK__GPIO7_IO10 0x0b0b1 530 + >; 531 + }; 532 + 533 + 534 + pinctrl_nor_flash: norflashgrp { 535 + fsl,pins = < 536 + MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x1b0b1 537 + MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1 538 + MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1 539 + MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1 540 + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b1 541 + >; 542 + }; 543 + 544 + pinctrl_pcie_ctrl: pciegrp { 545 + fsl,pins = < 546 + MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b1 547 + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b1 548 + >; 549 + }; 550 + 551 + pinctrl_pmic: pmicgrp { 552 + fsl,pins = < 553 + MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x0b0b1 554 + >; 555 + }; 556 + 557 + pinctrl_pwm_fan: pwmfan { 558 + fsl,pins = < 559 + MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x0b0b1 560 + >; 561 + }; 562 + 563 + pinctrl_rgb_bl: rgbbacklightgrp { 564 + fsl,pins = < 565 + MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x0b0b1 566 + MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x0b0b1 567 + >; 568 + }; 569 + 570 + pinctrl_rgb_bl_en: rgbenable { 571 + fsl,pins = < 572 + MX6QDL_PAD_SD4_CMD__GPIO7_IO09 0x0b0b1 573 + >; 574 + }; 575 + 576 + pinctrl_rgb24_display: rgbgrp { 577 + fsl,pins = < 578 + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 579 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 580 + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 581 + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 582 + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 583 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 584 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 585 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 586 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 587 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 588 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 589 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 590 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 591 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 592 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 593 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 594 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 595 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 596 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 597 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 598 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 599 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 600 + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 601 + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 602 + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 603 + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 604 + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 605 + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 606 + >; 607 + }; 608 + 609 + pinctrl_secure: securegrp { 610 + fsl,pins = < 611 + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b1 612 + >; 613 + }; 614 + 615 + pinctrl_som_leds: somledgrp { 616 + fsl,pins = < 617 + MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x0b0b1 618 + MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x0b0b1 619 + >; 620 + }; 621 + 622 + pinctrl_spdif_in: spdifin { 623 + fsl,pins = < 624 + MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0 625 + >; 626 + }; 627 + 628 + pinctrl_spdif_out: spdifout { 629 + fsl,pins = < 630 + MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x13091 631 + >; 632 + }; 633 + 634 + pinctrl_uart1: uart1grp { 635 + fsl,pins = < 636 + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 637 + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 638 + >; 639 + }; 640 + 641 + pinctrl_uart2: uart2grp { 642 + fsl,pins = < 643 + MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1 644 + MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1 645 + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 646 + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 647 + >; 648 + }; 649 + 650 + pinctrl_uart3: uart3grp { 651 + fsl,pins = < 652 + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 653 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 654 + >; 655 + }; 656 + 657 + pinctrl_uart4: uart4grp { 658 + fsl,pins = < 659 + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 660 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 661 + >; 662 + }; 663 + 664 + pinctrl_uart5: uart5grp { 665 + fsl,pins = < 666 + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 667 + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 668 + >; 669 + }; 670 + 671 + pinctrl_usb_host1: usbhgrp { 672 + fsl,pins = < 673 + MX6QDL_PAD_EIM_D31__USB_H1_PWR 0x1B058 674 + MX6QDL_PAD_EIM_D30__USB_H1_OC 0x1B058 675 + >; 676 + }; 677 + 678 + pinctrl_usb_otg: usbotggrp { 679 + fsl,pins = < 680 + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 681 + MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x17059 682 + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x17059 683 + >; 684 + }; 685 + 686 + pinctrl_usdhc1: usdhc1grp { 687 + fsl,pins = < 688 + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 689 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 690 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 691 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 692 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 693 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 694 + MX6QDL_PAD_GPIO_1__SD1_CD_B 0x1b0b1 695 + MX6QDL_PAD_DI0_PIN4__SD1_WP 0x1b0b1 696 + >; 697 + }; 698 + 699 + pinctrl_usdhc2: usdhc2grp { 700 + fsl,pins = < 701 + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 702 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 703 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 704 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 705 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 706 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 707 + MX6QDL_PAD_GPIO_4__SD2_CD_B 0x1b0b1 708 + MX6QDL_PAD_GPIO_2__SD2_WP 0x1b0b1 709 + >; 710 + }; 711 + 712 + pinctrl_usdhc3: usdhc3grp { 713 + fsl,pins = < 714 + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 715 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 716 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 717 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 718 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 719 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 720 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 721 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 722 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 723 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 724 + MX6QDL_PAD_SD3_RST__SD3_RESET 0x1b0b1 725 + >; 726 + }; 727 + }; 728 + 729 + &ipu1_di0_disp0 { 730 + remote-endpoint = <&rgb_encoder_in>; 731 + }; 732 + 733 + &pcie { 734 + pinctrl-names = "default"; 735 + pinctrl-0 = <&pinctrl_pcie_ctrl>; 736 + reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>; 737 + disable-gpio = <&gpio2 22 GPIO_ACTIVE_LOW>; 738 + }; 739 + 740 + &pwm1 { 741 + status = "okay"; 742 + }; 743 + 744 + &pwm3 { 745 + status = "okay"; 746 + }; 747 + 748 + &pwm4 { 749 + status = "okay"; 750 + }; 751 + 752 + &uart1 { 753 + pinctrl-names = "default"; 754 + pinctrl-0 = <&pinctrl_uart1>; 755 + status = "okay"; 756 + }; 757 + 758 + &uart2 { 759 + pinctrl-names = "default"; 760 + pinctrl-0 = <&pinctrl_uart2>; 761 + }; 762 + 763 + &uart3 { 764 + pinctrl-names = "default"; 765 + pinctrl-0 = <&pinctrl_uart3>; 766 + }; 767 + 768 + &uart4 { 769 + pinctrl-names = "default"; 770 + pinctrl-0 = <&pinctrl_uart4>; 771 + }; 772 + 773 + &uart5 { 774 + pinctrl-names = "default"; 775 + pinctrl-0 = <&pinctrl_uart5>; 776 + }; 777 + 778 + &usbh1 { 779 + pinctrl-names = "default"; 780 + pinctrl-0 = <&pinctrl_usb_host1>; 781 + }; 782 + 783 + &usbotg { 784 + pinctrl-names = "default"; 785 + pinctrl-0 = <&pinctrl_usb_otg>; 786 + vbus-supply = <&reg_usb_otg>; 787 + dr_mode = "peripheral"; 788 + }; 789 + 790 + &usdhc1 { 791 + pinctrl-names = "default"; 792 + pinctrl-0 = <&pinctrl_usdhc1>; 793 + fsl,wp-controller; 794 + }; 795 + 796 + &usdhc2 { 797 + pinctrl-names = "default"; 798 + pinctrl-0 = <&pinctrl_usdhc2>; 799 + fsl,wp-controller; 800 + }; 801 + 802 + &usdhc3 { 803 + pinctrl-names = "default"; 804 + pinctrl-0 = <&pinctrl_usdhc3>; 805 + non-removable; 806 + bus-width = <8>; 807 + status = "okay"; 808 + }; 809 + 810 + /******device power Management*********/ 811 + 812 + &cpu0 { 813 + voltage-tolerance = <2>; 814 + }; 815 + 816 + &reg_arm { 817 + vin-supply = <&vddcore_reg>; 818 + }; 819 + 820 + &reg_soc { 821 + vin-supply = <&vddsoc_reg>; 822 + }; 823 + 824 + &reg_pu { 825 + vin-supply = <&vddsoc_reg>; 826 + }; 827 + 828 + /*******Disabled HW following***********/ 829 + 830 + &snvs_rtc { 831 + status = "disabled"; 832 + };