tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
arm64: tegra: Initial Tegra234 VDK support
The NVIDIA Tegra234 VDK is a simulation platform for the Orin SoC. It
supports a subset of the peripherals that will be available in the final
chip and serves as a bootstrapping platform.
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
+264
+1
arch/arm64/boot/dts/nvidia/Makefile
+1
arch/arm64/boot/dts/nvidia/Makefile
+40
arch/arm64/boot/dts/nvidia/tegra234-sim-vdk.dts
+40
arch/arm64/boot/dts/nvidia/tegra234-sim-vdk.dts
···
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// SPDX-License-Identifier: GPL-2.0
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/dts-v1/;
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#include "tegra234.dtsi"
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/ {
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model = "NVIDIA Tegra234 VDK";
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compatible = "nvidia,tegra234-vdk", "nvidia,tegra234";
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aliases {
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sdhci3 = "/cbb@0/sdhci@3460000";
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serial0 = &uarta;
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};
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chosen {
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bootargs = "console=ttyS0,115200n8 earlycon=uart8250,mmio32,0x03100000";
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stdout-path = "serial0:115200n8";
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};
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cbb@0 {
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serial@3100000 {
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status = "okay";
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};
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sdhci@3460000 {
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status = "okay";
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bus-width = <8>;
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non-removable;
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only-1-8-v;
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};
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rtc@c2a0000 {
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status = "okay";
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};
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pmc@c360000 {
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nvidia,invert-interrupt;
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};
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};
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};
+189
arch/arm64/boot/dts/nvidia/tegra234.dtsi
+189
arch/arm64/boot/dts/nvidia/tegra234.dtsi
···
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// SPDX-License-Identifier: GPL-2.0
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#include <dt-bindings/clock/tegra234-clock.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/mailbox/tegra186-hsp.h>
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#include <dt-bindings/reset/tegra234-reset.h>
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/ {
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compatible = "nvidia,tegra234";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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bus@0 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x0 0x0 0x40000000>;
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misc@100000 {
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compatible = "nvidia,tegra234-misc";
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reg = <0x00100000 0xf000>,
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<0x0010f000 0x1000>;
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status = "okay";
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};
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uarta: serial@3100000 {
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compatible = "nvidia,tegra234-uart", "nvidia,tegra20-uart";
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reg = <0x03100000 0x10000>;
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interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bpmp TEGRA234_CLK_UARTA>;
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clock-names = "serial";
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resets = <&bpmp TEGRA234_RESET_UARTA>;
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reset-names = "serial";
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status = "disabled";
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};
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mmc@3460000 {
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compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci";
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reg = <0x03460000 0x20000>;
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interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bpmp TEGRA234_CLK_SDMMC4>;
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clock-names = "sdhci";
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resets = <&bpmp TEGRA234_RESET_SDMMC4>;
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reset-names = "sdhci";
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dma-coherent;
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status = "disabled";
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};
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fuse@3810000 {
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compatible = "nvidia,tegra234-efuse";
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reg = <0x03810000 0x10000>;
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clocks = <&bpmp TEGRA234_CLK_FUSE>;
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clock-names = "fuse";
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};
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hsp_top0: hsp@3c00000 {
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compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp";
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reg = <0x03c00000 0xa0000>;
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interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "doorbell", "shared0", "shared1", "shared2",
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"shared3", "shared4", "shared5", "shared6",
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"shared7";
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#mbox-cells = <2>;
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};
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hsp_aon: hsp@c150000 {
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compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp";
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reg = <0x0c150000 0x90000>;
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interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
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/*
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* Shared interrupt 0 is routed only to AON/SPE, so
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* we only have 4 shared interrupts for the CCPLEX.
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*/
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interrupt-names = "shared1", "shared2", "shared3", "shared4";
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#mbox-cells = <2>;
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};
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rtc@c2a0000 {
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compatible = "nvidia,tegra234-rtc", "nvidia,tegra20-rtc";
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reg = <0x0c2a0000 0x10000>;
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interrupt-parent = <&pmc>;
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interrupts = <73 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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pmc: pmc@c360000 {
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compatible = "nvidia,tegra234-pmc";
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reg = <0x0c360000 0x10000>,
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<0x0c370000 0x10000>,
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<0x0c380000 0x10000>,
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<0x0c390000 0x10000>,
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<0x0c3a0000 0x10000>;
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reg-names = "pmc", "wake", "aotag", "scratch", "misc";
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#interrupt-cells = <2>;
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interrupt-controller;
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};
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gic: interrupt-controller@f400000 {
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compatible = "arm,gic-v3";
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reg = <0x0f400000 0x010000>, /* GICD */
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<0x0f440000 0x200000>; /* GICR */
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interrupt-parent = <&gic>;
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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#redistributor-regions = <1>;
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#interrupt-cells = <3>;
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interrupt-controller;
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};
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};
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sysram@40000000 {
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compatible = "nvidia,tegra234-sysram", "mmio-sram";
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reg = <0x0 0x40000000 0x0 0x50000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x0 0x40000000 0x50000>;
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cpu_bpmp_tx: shmem@4e000 {
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reg = <0x4e000 0x1000>;
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label = "cpu-bpmp-tx";
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pool;
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};
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cpu_bpmp_rx: shmem@4f000 {
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reg = <0x4f000 0x1000>;
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label = "cpu-bpmp-rx";
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pool;
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};
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};
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bpmp: bpmp {
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compatible = "nvidia,tegra234-bpmp", "nvidia,tegra186-bpmp";
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mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB
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TEGRA_HSP_DB_MASTER_BPMP>;
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shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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bpmp_i2c: i2c {
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compatible = "nvidia,tegra186-bpmp-i2c";
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nvidia,bpmp-bus-id = <5>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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reg = <0x000>;
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enable-method = "psci";
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};
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};
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psci {
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compatible = "arm,psci-1.0";
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status = "okay";
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method = "smc";
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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interrupt-parent = <&gic>;
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always-on;
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};
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};
+10
drivers/soc/tegra/Kconfig
+10
drivers/soc/tegra/Kconfig
···
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help
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Enable support for the NVIDIA Tegra194 SoC.
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config ARCH_TEGRA_234_SOC
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bool "NVIDIA Tegra234 SoC"
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select MAILBOX
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select TEGRA_BPMP
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select TEGRA_HSP_MBOX
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select TEGRA_IVC
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select SOC_TEGRA_PMC
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help
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Enable support for the NVIDIA Tegra234 SoC.
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endif
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endif
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+14
include/dt-bindings/clock/tegra234-clock.h
+14
include/dt-bindings/clock/tegra234-clock.h
···
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/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. */
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#ifndef DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H
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#define DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H
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/** @brief output of gate CLK_ENB_FUSE */
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#define TEGRA234_CLK_FUSE 40
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 */
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#define TEGRA234_CLK_SDMMC4 123
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTA */
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#define TEGRA234_CLK_UARTA 155
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#endif
+10
include/dt-bindings/reset/tegra234-reset.h
+10
include/dt-bindings/reset/tegra234-reset.h
···
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/* SPDX-License-Identifier: GPL-2.0 */
2
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/* Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved. */
3
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4
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#ifndef DT_BINDINGS_RESET_TEGRA234_RESET_H
5
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#define DT_BINDINGS_RESET_TEGRA234_RESET_H
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#define TEGRA234_RESET_SDMMC4 85
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#define TEGRA234_RESET_UARTA 100
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#endif