tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

MIPS: Remove useless parentheses

Based on the spatch

@@
expression e;
@@
- return (e);
+ return e;

with heavy hand editing because some of the changes are either whitespace
or identation only or result in excessivly long lines.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

Ralf Baechle 635c9907 5d01410f

+42 -46
+1 -1
arch/mips/bcm63xx/cpu.c
··· 263 263 264 264 if (BCMCPU_IS_6345()) { 265 265 val = bcm_sdram_readl(SDRAM_MBASE_REG); 266 - return (val * 8 * 1024 * 1024); 266 + return val * 8 * 1024 * 1024; 267 267 } 268 268 269 269 if (BCMCPU_IS_6338() || BCMCPU_IS_6348()) {
+1 -1
arch/mips/kernel/cpu-probe.c
··· 140 140 */ 141 141 static inline int __cpu_has_fpu(void) 142 142 { 143 - return ((cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE); 143 + return (cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE; 144 144 } 145 145 146 146 static inline unsigned long cpu_get_msa_id(void)
+1 -1
arch/mips/kernel/irq-gic.c
··· 98 98 99 99 GICWRITE(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), 0); 100 100 GICREAD(GIC_REG(VPE_OTHER, GIC_VPE_PEND), vpe_pending); 101 - return (vpe_pending & GIC_VPE_PEND_TIMER_MSK); 101 + return vpe_pending & GIC_VPE_PEND_TIMER_MSK; 102 102 } 103 103 104 104 void gic_bind_eic_interrupt(int irq, int set)
+18 -18
arch/mips/kernel/process.c
··· 187 187 */ 188 188 if (mm_insn_16bit(ip->halfword[0])) { 189 189 mmi.word = (ip->halfword[0] << 16); 190 - return ((mmi.mm16_r5_format.opcode == mm_swsp16_op && 191 - mmi.mm16_r5_format.rt == 31) || 192 - (mmi.mm16_m_format.opcode == mm_pool16c_op && 193 - mmi.mm16_m_format.func == mm_swm16_op)); 190 + return (mmi.mm16_r5_format.opcode == mm_swsp16_op && 191 + mmi.mm16_r5_format.rt == 31) || 192 + (mmi.mm16_m_format.opcode == mm_pool16c_op && 193 + mmi.mm16_m_format.func == mm_swm16_op); 194 194 } 195 195 else { 196 196 mmi.halfword[0] = ip->halfword[1]; 197 197 mmi.halfword[1] = ip->halfword[0]; 198 - return ((mmi.mm_m_format.opcode == mm_pool32b_op && 199 - mmi.mm_m_format.rd > 9 && 200 - mmi.mm_m_format.base == 29 && 201 - mmi.mm_m_format.func == mm_swm32_func) || 202 - (mmi.i_format.opcode == mm_sw32_op && 203 - mmi.i_format.rs == 29 && 204 - mmi.i_format.rt == 31)); 198 + return (mmi.mm_m_format.opcode == mm_pool32b_op && 199 + mmi.mm_m_format.rd > 9 && 200 + mmi.mm_m_format.base == 29 && 201 + mmi.mm_m_format.func == mm_swm32_func) || 202 + (mmi.i_format.opcode == mm_sw32_op && 203 + mmi.i_format.rs == 29 && 204 + mmi.i_format.rt == 31); 205 205 } 206 206 #else 207 207 /* sw / sd $ra, offset($sp) */ ··· 233 233 if (ip->r_format.opcode != mm_pool32a_op || 234 234 ip->r_format.func != mm_pool32axf_op) 235 235 return 0; 236 - return (((ip->u_format.uimmediate >> 6) & mm_jalr_op) == mm_jalr_op); 236 + return ((ip->u_format.uimmediate >> 6) & mm_jalr_op) == mm_jalr_op; 237 237 #else 238 238 if (ip->j_format.opcode == j_op) 239 239 return 1; ··· 260 260 union mips_instruction mmi; 261 261 262 262 mmi.word = (ip->halfword[0] << 16); 263 - return ((mmi.mm16_r3_format.opcode == mm_pool16d_op && 264 - mmi.mm16_r3_format.simmediate && mm_addiusp_func) || 265 - (mmi.mm16_r5_format.opcode == mm_pool16d_op && 266 - mmi.mm16_r5_format.rt == 29)); 263 + return (mmi.mm16_r3_format.opcode == mm_pool16d_op && 264 + mmi.mm16_r3_format.simmediate && mm_addiusp_func) || 265 + (mmi.mm16_r5_format.opcode == mm_pool16d_op && 266 + mmi.mm16_r5_format.rt == 29); 267 267 } 268 - return (ip->mm_i_format.opcode == mm_addiu32_op && 269 - ip->mm_i_format.rt == 29 && ip->mm_i_format.rs == 29); 268 + return ip->mm_i_format.opcode == mm_addiu32_op && 269 + ip->mm_i_format.rt == 29 && ip->mm_i_format.rs == 29; 270 270 #else 271 271 /* addiu/daddiu sp,sp,-imm */ 272 272 if (ip->i_format.rs != 29 || ip->i_format.rt != 29)
+1 -1
arch/mips/loongson/common/gpio.c
··· 37 37 val = LOONGSON_GPIODATA; 38 38 spin_unlock(&gpio_lock); 39 39 40 - return ((val & mask) != 0); 40 + return (val & mask) != 0; 41 41 } 42 42 EXPORT_SYMBOL(gpio_get_value); 43 43
+1 -1
arch/mips/math-emu/ieee754dp.c
··· 38 38 static inline int ieee754dp_issnan(union ieee754dp x) 39 39 { 40 40 assert(ieee754dp_isnan(x)); 41 - return ((DPMANT(x) & DP_MBIT(DP_FBITS-1)) == DP_MBIT(DP_FBITS-1)); 41 + return (DPMANT(x) & DP_MBIT(DP_FBITS - 1)) == DP_MBIT(DP_FBITS - 1); 42 42 } 43 43 44 44
+1 -1
arch/mips/math-emu/ieee754sp.c
··· 38 38 static inline int ieee754sp_issnan(union ieee754sp x) 39 39 { 40 40 assert(ieee754sp_isnan(x)); 41 - return (SPMANT(x) & SP_MBIT(SP_FBITS-1)); 41 + return SPMANT(x) & SP_MBIT(SP_FBITS - 1); 42 42 } 43 43 44 44
+1 -1
arch/mips/mm/sc-r5k.c
··· 81 81 unsigned long config = read_c0_config(); 82 82 83 83 if (config & CONF_SC) 84 - return(0); 84 + return 0; 85 85 86 86 scache_size = (512 * 1024) << ((config & R5K_CONF_SS) >> 20); 87 87
+1 -1
arch/mips/pci/ops-bcm63xx.c
··· 469 469 { 470 470 switch (bus->number) { 471 471 case PCIE_BUS_BRIDGE: 472 - return (PCI_SLOT(devfn) == 0); 472 + return PCI_SLOT(devfn) == 0; 473 473 case PCIE_BUS_DEVICE: 474 474 if (PCI_SLOT(devfn) == 0) 475 475 return bcm_pcie_readl(PCIE_DLSTATUS_REG)
+1 -1
arch/mips/pmcs-msp71xx/msp_prom.c
··· 295 295 296 296 while (*var) { 297 297 if (strncmp(env_name, *var, i) == 0) { 298 - return (*var + strlen(env_name) + 1); 298 + return *var + strlen(env_name) + 1; 299 299 } 300 300 var++; 301 301 }
+1 -1
arch/mips/rb532/gpio.c
··· 79 79 */ 80 80 static inline int rb532_get_bit(unsigned offset, void __iomem *ioaddr) 81 81 { 82 - return (readl(ioaddr) & (1 << offset)); 82 + return readl(ioaddr) & (1 << offset); 83 83 } 84 84 85 85 /*
+2 -4
arch/mips/sgi-ip22/ip22-mc.c
··· 24 24 25 25 static inline unsigned long get_bank_addr(unsigned int memconfig) 26 26 { 27 - return ((memconfig & SGIMC_MCONFIG_BASEADDR) << 28 - ((sgimc->systemid & SGIMC_SYSID_MASKREV) >= 5 ? 24 : 22)); 27 + return (memconfig & SGIMC_MCONFIG_BASEADDR) << ((sgimc->systemid & SGIMC_SYSID_MASKREV) >= 5 ? 24 : 22); 29 28 } 30 29 31 30 static inline unsigned long get_bank_size(unsigned int memconfig) 32 31 { 33 - return ((memconfig & SGIMC_MCONFIG_RMASK) + 0x0100) << 34 - ((sgimc->systemid & SGIMC_SYSID_MASKREV) >= 5 ? 16 : 14); 32 + return ((memconfig & SGIMC_MCONFIG_RMASK) + 0x0100) << ((sgimc->systemid & SGIMC_SYSID_MASKREV) >= 5 ? 16 : 14); 35 33 } 36 34 37 35 static inline unsigned int get_bank_config(int bank)
+3 -3
arch/mips/sgi-ip22/ip28-berr.c
··· 338 338 PHYS_TO_XKSEG_UNCACHED(pte); 339 339 a = (a & 0x3f) << 6; /* PFN */ 340 340 a += vaddr & ((1 << pgsz) - 1); 341 - return (cpu_err_addr == a); 341 + return cpu_err_addr == a; 342 342 } 343 343 } 344 344 } ··· 351 351 u32 a = sgimc->maddronly; 352 352 353 353 if (!(sgimc->dma_ctrl & 0x100)) /* Xlate-bit clear ? */ 354 - return (cpu_err_addr == a); 354 + return cpu_err_addr == a; 355 355 356 356 if (check_microtlb(sgimc->dtlb_hi0, sgimc->dtlb_lo0, a) || 357 357 check_microtlb(sgimc->dtlb_hi1, sgimc->dtlb_lo1, a) || ··· 367 367 if (gio_err_stat & GIO_ERRMASK) { 368 368 u32 a = sgimc->gio_dma_trans; 369 369 a = (sgimc->gmaddronly & ~a) | (sgimc->gio_dma_sbits & a); 370 - return (gio_err_addr == a); 370 + return gio_err_addr == a; 371 371 } 372 372 return 0; 373 373 }
+2 -3
arch/mips/sgi-ip27/ip27-klnuma.c
··· 125 125 #endif 126 126 offset = PAGE_ALIGN((unsigned long)(&_end)) - loadbase; 127 127 if ((cnode == 0) || (cpu_isset(cnode, ktext_repmask))) 128 - return (TO_NODE(nasid, offset) >> PAGE_SHIFT); 128 + return TO_NODE(nasid, offset) >> PAGE_SHIFT; 129 129 else 130 - return (KDM_TO_PHYS(PAGE_ALIGN(SYMMON_STK_ADDR(nasid, 0))) >> 131 - PAGE_SHIFT); 130 + return KDM_TO_PHYS(PAGE_ALIGN(SYMMON_STK_ADDR(nasid, 0))) >> PAGE_SHIFT; 132 131 }
+2 -3
arch/mips/sgi-ip27/ip27-memory.c
··· 42 42 43 43 static int is_fine_dirmode(void) 44 44 { 45 - return (((LOCAL_HUB_L(NI_STATUS_REV_ID) & NSRI_REGIONSIZE_MASK) 46 - >> NSRI_REGIONSIZE_SHFT) & REGIONSIZE_FINE); 45 + return ((LOCAL_HUB_L(NI_STATUS_REV_ID) & NSRI_REGIONSIZE_MASK) >> NSRI_REGIONSIZE_SHFT) & REGIONSIZE_FINE; 47 46 } 48 47 49 48 static hubreg_t get_region(cnodeid_t cnode) ··· 287 288 if (size <= 128) { 288 289 if (slot % 4 == 0) { 289 290 size <<= 20; /* size in bytes */ 290 - return(size >> PAGE_SHIFT); 291 + return size >> PAGE_SHIFT; 291 292 } else 292 293 return 0; 293 294 } else {
+2 -2
arch/mips/sibyte/swarm/rtc_m41t81.c
··· 109 109 return -1; 110 110 } 111 111 112 - return (__raw_readq(SMB_CSR(R_SMB_DATA)) & 0xff); 112 + return __raw_readq(SMB_CSR(R_SMB_DATA)) & 0xff; 113 113 } 114 114 115 115 static int m41t81_write(uint8_t addr, int b) ··· 229 229 tmp = m41t81_read(M41T81REG_SC); 230 230 m41t81_write(M41T81REG_SC, tmp & 0x7f); 231 231 232 - return (m41t81_read(M41T81REG_SC) != -1); 232 + return m41t81_read(M41T81REG_SC) != -1; 233 233 }
+2 -2
arch/mips/sibyte/swarm/rtc_xicor1241.c
··· 84 84 return -1; 85 85 } 86 86 87 - return (__raw_readq(SMB_CSR(R_SMB_DATA)) & 0xff); 87 + return __raw_readq(SMB_CSR(R_SMB_DATA)) & 0xff; 88 88 } 89 89 90 90 static int xicor_write(uint8_t addr, int b) ··· 206 206 207 207 int xicor_probe(void) 208 208 { 209 - return (xicor_read(X1241REG_SC) != -1); 209 + return xicor_read(X1241REG_SC) != -1; 210 210 }
+1 -1
arch/mips/sibyte/swarm/setup.c
··· 76 76 printk("DBE physical address: %010Lx\n", 77 77 __read_64bit_c0_register($26, 1)); 78 78 } 79 - return (is_fixup ? MIPS_BE_FIXUP : MIPS_BE_FATAL); 79 + return is_fixup ? MIPS_BE_FIXUP : MIPS_BE_FATAL; 80 80 } 81 81 82 82 enum swarm_rtc_type {